mirrors/llvm-project
0
0
Fork 0
mirror of https://github.com/llvm/llvm-project.git synced 2025-04-27 17:46:06 +00:00
Code Issues Projects Releases Wiki Activity
llvm-project/llvm/utils/TableGen/GlobalISelEmitter.cpp

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

2471 lines
96 KiB
C++
Raw Normal View History

[GlobalISel][TableGen] Take first result for multi-output instructions (#81130) Previously, tblgen would reject patterns where one of its nested instructions produced more than one result. These arise when the instruction definition contains 'outs' as well as 'Defs'. This patch fixes that by always taking the first result, which is how these situations are handled in SelectionIDAG. Original patch: https://reviews.llvm.org/D86617 Continued as: https://github.com/llvm/llvm-project/pull/81130
2023-11-03 12:44:38 +01:00
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
//===- GlobalISelEmitter.cpp - Generate an instruction selector -----------===//
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 08:50:56 +00:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
//
//===----------------------------------------------------------------------===//
//
/// \file
/// This tablegen backend emits code for use by the GlobalISel instruction
[GISelEmitter][NFC] Correct path of GISel's td file in the comment. `include/llvm/CodeGen/TargetGlobalISel.td` no longer exists.
2023-02-20 10:05:37 +08:00
/// selector. See include/llvm/Target/GlobalISel/Target.td.
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
///
/// This file analyzes the patterns recognized by the SelectionDAGISel tablegen
/// backend, filters out the ones that are unsupported, maps
/// SelectionDAG-specific constructs to their GlobalISel counterpart
/// (when applicable: MVT to LLT; SDNode to generic Instruction).
///
/// Not all patterns are supported: pass the tablegen invocation
/// "-warn-on-skipped-patterns" to emit a warning when a pattern is skipped,
/// as well as why.
///
/// The generated file defines a single method:
/// bool <Target>InstructionSelector::selectImpl(MachineInstr &I) const;
/// intended to be used in InstructionSelector::select as the first-step
/// selector for the patterns that don't require complex C++.
///
/// FIXME: We'll probably want to eventually define a base
/// "TargetGenInstructionSelector" class.
///
//===----------------------------------------------------------------------===//
[RFC][TableGen] Restructure TableGen Source (#80847) Refactor of the llvm-tblgen source into: - a "Basic" library, which contains the bare minimum utilities to build `llvm-min-tablegen` - a "Common" library which contains all of the helpers for TableGen backends. Such helpers can be shared by more than one backend, and even unit tested (e.g. CodeExpander is, maybe we can add more over time) Fixes #80647
2024-03-25 09:40:35 +01:00
#include "Basic/CodeGenIntrinsics.h"
#include "Common/CodeGenDAGPatterns.h"
#include "Common/CodeGenInstruction.h"
#include "Common/CodeGenRegisters.h"
#include "Common/CodeGenTarget.h"
#include "Common/GlobalISel/GlobalISelMatchTable.h"
#include "Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h"
#include "Common/InfoByHwMode.h"
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
#include "llvm/ADT/Statistic.h"
[llvm] Move CodeGenTypes library to its own directory (#79444) Finally addresses https://reviews.llvm.org/D148769#4311232 :) No behavior change.
2024-01-25 12:01:31 -05:00
#include "llvm/CodeGenTypes/LowLevelType.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
2017-11-16 00:46:35 +00:00
#include "llvm/Support/CodeGenCoverage.h"
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
#include "llvm/Support/CommandLine.h"
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
#include "llvm/Support/Error.h"
tablegen: Fix android build use llvm::to_string instead of std:: version. llvm-svn: 295711
2017-02-21 09:19:41 +00:00
#include "llvm/Support/ScopedPrinter.h"
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
2017-11-16 00:46:35 +00:00
#include <string>
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
using namespace llvm;
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
using namespace llvm::gi;
using action_iterator = RuleMatcher::action_iterator;
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
#define DEBUG_TYPE "gisel-emitter"
STATISTIC(NumPatternTotal, "Total number of patterns");
[globalisel] Separate the SelectionDAG importer from the emitter. NFC Summary: In the near future the rules will be sorted between these two steps to ensure that more important rules are not prevented by less important ones. Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29709 llvm-svn: 295661
2017-02-20 14:31:27 +00:00
STATISTIC(NumPatternImported, "Number of patterns imported from SelectionDAG");
STATISTIC(NumPatternImportsSkipped, "Number of SelectionDAG imports skipped");
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
STATISTIC(NumPatternsTested,
"Number of patterns executed according to coverage information");
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
[tablegen] Use categories on options that only matter to one emitter. Summary: The categories are emitted in a strange order in this patch due to a bug in the CommandLine library. Reviewers: ab Reviewed By: ab Subscribers: ab, llvm-commits Differential Revision: https://reviews.llvm.org/D30995 llvm-svn: 298843
2017-03-27 13:15:13 +00:00
cl::OptionCategory GlobalISelEmitterCat("Options for -gen-global-isel");
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
static cl::opt<bool> WarnOnSkippedPatterns(
"warn-on-skipped-patterns",
cl::desc("Explain why a pattern was skipped for inclusion "
"in the GlobalISel selector"),
[tablegen] Use categories on options that only matter to one emitter. Summary: The categories are emitted in a strange order in this patch due to a bug in the CommandLine library. Reviewers: ab Reviewed By: ab Subscribers: ab, llvm-commits Differential Revision: https://reviews.llvm.org/D30995 llvm-svn: 298843
2017-03-27 13:15:13 +00:00
cl::init(false), cl::cat(GlobalISelEmitterCat));
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
2017-11-16 00:46:35 +00:00
static cl::opt<bool> GenerateCoverage(
"instrument-gisel-coverage",
cl::desc("Generate coverage instrumentation for GlobalISel"),
cl::init(false), cl::cat(GlobalISelEmitterCat));
static cl::opt<std::string> UseCoverageFile(
"gisel-coverage-file", cl::init(""),
cl::desc("Specify file to retrieve coverage information from"),
cl::cat(GlobalISelEmitterCat));
[TableGen][GlobalISel] Optimize MatchTable for faster instruction selection *** Context *** Prior to this patchw, the table generated for matching instruction was straight forward but highly inefficient. Basically, each pattern generates its own set of self contained checks and actions. E.g., TableGen generated: // First pattern CheckNumOperand 3 CheckOpcode G_ADD ... Build ADDrr // Second pattern CheckNumOperand 3 CheckOpcode G_ADD ... Build ADDri // Third pattern CheckNumOperand 3 CheckOpcode G_SUB ... Build SUBrr *** Problem *** Because of that generation, a *lot* of check were redundant between each pattern and were checked every single time until we reach the pattern that matches. E.g., Taking the previous table, let say we are matching a G_SUB, that means we were going to check all the rules for G_ADD before looking at the G_SUB rule. In particular we are going to do: check 3 operands; PASS check G_ADD; FAIL ; Next rule check 3 operands; PASS (but we already knew that!) check G_ADD; FAIL (well it is still not true) ; Next rule check 3 operands; PASS (really!!) check G_SUB; PASS (at last :P) *** Proposed Solution *** This patch introduces a concept of group of rules (GroupMatcher) that share some predicates and only get checked once for the whole group. This patch only creates groups with one nesting level. Conceptually there is nothing preventing us for having deeper nest level. However, the current implementation is not smart enough to share the recording (aka capturing) of values. That limits its ability to do more sharing. For the given example the current patch will generate: // First group CheckOpcode G_ADD // First pattern CheckNumOperand 3 ... Build ADDrr // Second pattern CheckNumOperand 3 ... Build ADDri // Second group CheckOpcode G_SUB // Third pattern CheckNumOperand 3 ... Build SUBrr But if we allowed several nesting level, it could create a sub group for the checknumoperand 3. (We would need to call optimizeRules on the rules within a group.) *** Result *** With only one level of nesting, the instruction selection pass is up to 4x faster. For instance, one instruction now takes 500 checks, instead of 24k! With more nesting we could get in the tens I believe. Differential Revision: https://reviews.llvm.org/D39034 rdar://problem/34670699 llvm-svn: 321017
2017-12-18 19:47:41 +00:00
static cl::opt<bool> OptimizeMatchTable(
"optimize-match-table",
cl::desc("Generate an optimized version of the match table"),
cl::init(true), cl::cat(GlobalISelEmitterCat));
[tablegen][globalisel] Trivial changes to reduce size of following patch. NFC. Summary: * Move namespace { * Trivial: Typo * RuleMatcher: Separate class and definition * Trivial: const findNodeEquiv Reviewers: t.p.northover, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: rovka Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30531 llvm-svn: 297884
2017-03-15 20:18:38 +00:00
namespace {
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
static std::string explainPredicates(const TreePatternNode &N) {
[llvm] Remove redundant string initialization (NFC) Identified with readability-redundant-string-init.
2021-01-12 21:43:46 -08:00
std::string Explanation;
[globalisel][tablegen] Report more detail in some SelectionDAG import failures. NFC Reviewers: ab, t.p.northover, qcolombet, aditya_nandakumar, rovka Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31325 llvm-svn: 300186
2017-04-13 09:45:37 +00:00
StringRef Separator = "";
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
for (const TreePredicateCall &Call : N.getPredicateCalls()) {
TableGen/ISel: Allow PatFrag predicate code to access captured operands Summary: This simplifies writing predicates for pattern fragments that are automatically re-associated or commuted. For example, a followup patch adds patterns for fragments of the form (add (shl $x, $y), $z) to the AMDGPU backend. Such patterns are automatically commuted to (add $z, (shl $x, $y)), which makes it basically impossible to refer to $x, $y, and $z generically in the PredicateCode. With this change, the PredicateCode can refer to $x, $y, and $z simply as `Operands[i]`. Test confirmed that there are no changes to any of the generated files when building all (non-experimental) targets. Change-Id: I61c00ace7eed42c1d4edc4c5351174b56b77a79c Reviewers: arsenm, rampitec, RKSimon, craig.topper, hfinkel, uweigand Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D51994 llvm-svn: 347992
2018-11-30 14:15:13 +00:00
const TreePredicateFn &P = Call.Fn;
[globalisel][tablegen] Report more detail in some SelectionDAG import failures. NFC Reviewers: ab, t.p.northover, qcolombet, aditya_nandakumar, rovka Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31325 llvm-svn: 300186
2017-04-13 09:45:37 +00:00
Explanation +=
(Separator + P.getOrigPatFragRecord()->getRecord()->getName()).str();
[globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG. GIM_CheckNonAtomic has been replaced by GIM_CheckAtomicOrdering to allow it to support a wider range of orderings. This has then been used to import patterns using nodes such as atomic_cmp_swap, atomic_swap, and atomic_load_*. llvm-svn: 319232
2017-11-28 22:07:05 +00:00
Separator = ", ";
[globalisel][tablegen] Report more detail in some SelectionDAG import failures. NFC Reviewers: ab, t.p.northover, qcolombet, aditya_nandakumar, rovka Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31325 llvm-svn: 300186
2017-04-13 09:45:37 +00:00
if (P.isAlwaysTrue())
Explanation += " always-true";
if (P.isImmediatePattern())
Explanation += " immediate";
[tablegen] Handle common load/store predicates inside tablegen. NFC. Summary: GlobalISel and SelectionDAG require different code for the common load/store predicates due to differences in the representation. For example: SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr)) Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common load/store predicates into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. Depends on D36618 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37443 Includes a partial revert of r315826 since this patch makes it necessary for getPredCode() to return a std::string and getImmCode() should have the same interface as getPredCode(). llvm-svn: 315841
2017-10-15 02:06:44 +00:00
if (P.isUnindexed())
Explanation += " unindexed";
if (P.isNonExtLoad())
Explanation += " non-extload";
if (P.isAnyExtLoad())
Explanation += " extload";
if (P.isSignExtLoad())
Explanation += " sextload";
if (P.isZeroExtLoad())
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
Explanation += " zextload";
Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp" This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:37:51 +02:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (P.isNonTruncStore())
Explanation += " non-truncstore";
if (P.isTruncStore())
Explanation += " truncstore";
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
[TableGen] Change CodeGenInstruction record members to const (#107921) Change CodeGenInstruction::{TheDef, InfereredFrom} to const pointers. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-11 08:52:26 -07:00
if (const Record *VT = P.getMemoryVT())
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
Explanation += (" MemVT=" + VT->getName()).str();
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
if (const Record *VT = P.getScalarMemoryVT())
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
Explanation += (" ScalarVT(MemVT)=" + VT->getName()).str();
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
if (const ListInit *AddrSpaces = P.getAddressSpaces()) {
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
raw_string_ostream OS(Explanation);
OS << " AddressSpaces=[";
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
StringRef AddrSpaceSeparator;
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
for (const Init *Val : AddrSpaces->getValues()) {
const IntInit *IntVal = dyn_cast<IntInit>(Val);
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (!IntVal)
continue;
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
OS << AddrSpaceSeparator << IntVal->getValue();
AddrSpaceSeparator = ", ";
}
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
OS << ']';
}
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
int64_t MinAlign = P.getMinAlignment();
if (MinAlign > 0)
Explanation += " MinAlign=" + utostr(MinAlign);
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (P.isAtomicOrderingMonotonic())
Explanation += " monotonic";
if (P.isAtomicOrderingAcquire())
Explanation += " acquire";
if (P.isAtomicOrderingRelease())
Explanation += " release";
if (P.isAtomicOrderingAcquireRelease())
Explanation += " acq_rel";
if (P.isAtomicOrderingSequentiallyConsistent())
Explanation += " seq_cst";
if (P.isAtomicOrderingAcquireOrStronger())
Explanation += " >=acquire";
if (P.isAtomicOrderingWeakerThanAcquire())
Explanation += " <acquire";
if (P.isAtomicOrderingReleaseOrStronger())
Explanation += " >=release";
if (P.isAtomicOrderingWeakerThanRelease())
Explanation += " <release";
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
}
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
return Explanation;
Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp" This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:37:51 +02:00
}
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
[TableGen] Change CodeGenInstruction record members to const (#107921) Change CodeGenInstruction::{TheDef, InfereredFrom} to const pointers. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-11 08:52:26 -07:00
std::string explainOperator(const Record *Operator) {
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Operator->isSubClassOf("SDNode"))
return (" (" + Operator->getValueAsString("Opcode") + ")").str();
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Operator->isSubClassOf("Intrinsic"))
return (" (Operator is an Intrinsic, " + Operator->getName() + ")").str();
[globalisel][tablegen] Add support for importing 'imm' operands. Summary: This patch enables the import of rules containing 'imm' operands that do not constrain the acceptable values using predicates. Support for ImmLeaf will arrive in a later patch. Depends on D35681 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35833 llvm-svn: 310343
2017-08-08 10:44:31 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Operator->isSubClassOf("ComplexPattern"))
return (" (Operator is an unmapped ComplexPattern, " + Operator->getName() +
")")
.str();
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Operator->isSubClassOf("SDNodeXForm"))
return (" (Operator is an unmapped SDNodeXForm, " + Operator->getName() +
")")
.str();
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
return (" (Operator " + Operator->getName() + " not understood)").str();
Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp" This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:37:51 +02:00
}
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
/// Helper function to let the emitter report skip reason error messages.
static Error failedImport(const Twine &Reason) {
return make_error<StringError>(Reason, inconvertibleErrorCode());
Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp" This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:37:51 +02:00
}
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
static Error isTrivialOperatorNode(const TreePatternNode &N) {
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
std::string Explanation;
std::string Separator;
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
bool HasUnsupportedPredicate = false;
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
for (const TreePredicateCall &Call : N.getPredicateCalls()) {
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
const TreePredicateFn &Predicate = Call.Fn;
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.isAlwaysTrue())
continue;
[tablegen][globalisel] Capture instructions into locals and related infrastructure for multiple instructions matches. Summary: Prepare the way for nested instruction matching support by having actions like CopyRenderer look up operands in the RuleMatcher rather than a specific InstructionMatcher. This allows actions to reference any operand from any matched instruction. It works by checking the 'shape' of the match and capturing each matched instruction to a local variable. If the shape is wrong (not enough operands, leaf nodes where non-leafs are expected, etc.), then the rule exits early without checking the predicates. Once we've captured the instructions, we then test the predicates as before (except using the local variables). If the match is successful, then we render the new instruction as before using the local variables. It's not noticable in this patch but by the time we support multiple instruction matching, this patch will also cause a significant improvement to readability of the emitted code since MRI.getVRegDef(I->getOperand(0).getReg()) will simply be MI1 after emitCxxCaptureStmts(). This isn't quite NFC because I've also fixed a bug that I'm surprised we haven't encountered yet. It now checks there are at least the expected number of operands before accessing them with getOperand(). Depends on D30531 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: rovka Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30535 llvm-svn: 298257
2017-03-20 15:20:42 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.isImmediatePattern())
continue;
[globalisel][tablegen] Partially fix compile-time regressions by converting matcher to state-machine(s) Summary: Replace the matcher if-statements for each rule with a state-machine. This significantly reduces compile time, memory allocations, and cumulative memory allocation when compiling AArch64InstructionSelector.cpp.o after r303259 is recommitted. The following patches will expand on this further to fully fix the regressions. Reviewers: rovka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: vitalybuka, aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33758 llvm-svn: 307079
2017-07-04 14:35:06 +00:00
[TableGen] HasOneUse builtin predicate on PatFrags (#91578) This predicate tells GlobalISelEmitter and DAGISelEmitter to check that the instruction to emit has only one use of its result. This can be used on a PatFrag instead of defining custom predicates for both emitters per record that requires it.
2024-05-20 06:18:49 -08:00
if (Predicate.hasNoUse() || Predicate.hasOneUse())
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
continue;
Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp" This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:37:51 +02:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.isNonExtLoad() || Predicate.isAnyExtLoad() ||
Predicate.isSignExtLoad() || Predicate.isZeroExtLoad())
continue;
Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp" This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:37:51 +02:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.isNonTruncStore() || Predicate.isTruncStore())
continue;
Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp" This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:37:51 +02:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.isLoad() && Predicate.getMemoryVT())
continue;
Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp" This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:37:51 +02:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.isLoad() || Predicate.isStore()) {
if (Predicate.isUnindexed())
[tablegen][globalisel] Add support for nested instruction matching. Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
2017-04-04 13:25:23 +00:00
continue;
Fixed nondeterminism in RuleMatcher::emit. llvm-svn: 303829
2017-05-25 01:51:53 +00:00
}
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) {
const ListInit *AddrSpaces = Predicate.getAddressSpaces();
if (AddrSpaces && !AddrSpaces->empty())
continue;
[tablegen][globalisel] Add support for nested instruction matching. Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
2017-04-04 13:25:23 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.getMinAlignment() > 0)
continue;
[tablegen][globalisel] Add support for nested instruction matching. Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
2017-04-04 13:25:23 +00:00
}
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.isAtomic() && Predicate.getMemoryVT())
continue;
[globalisel] Sort RuleMatchers by priority. Summary: This makes more important rules have priority over less important rules. For example, '%a = G_ADD $b:s64, $c:s64' has priority over '%a = G_ADD $b:s32, $c:s32'. Previously these rules were emitted in the correct order by chance. NFC in this patch but it is required to make the next patch work correctly. Depends on D29710 Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka Reviewed By: ab, rovka Subscribers: javed.absar, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D29711 llvm-svn: 296121
2017-02-24 13:58:11 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.isAtomic() &&
(Predicate.isAtomicOrderingMonotonic() ||
Predicate.isAtomicOrderingAcquire() ||
Predicate.isAtomicOrderingRelease() ||
Predicate.isAtomicOrderingAcquireRelease() ||
Predicate.isAtomicOrderingSequentiallyConsistent() ||
Predicate.isAtomicOrderingAcquireOrStronger() ||
Predicate.isAtomicOrderingWeakerThanAcquire() ||
Predicate.isAtomicOrderingReleaseOrStronger() ||
Predicate.isAtomicOrderingWeakerThanRelease()))
continue;
Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp" This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:37:51 +02:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (Predicate.hasGISelPredicateCode())
continue;
Revert "[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp" This reverts commit 79caedf5f8992ac16313157470f529344972c2ee.
2023-06-05 09:37:51 +02:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
HasUnsupportedPredicate = true;
Explanation = Separator + "Has a predicate (" + explainPredicates(N) + ")";
Separator = ", ";
Explanation += (Separator + "first-failing:" +
Predicate.getOrigPatFragRecord()->getRecord()->getName())
.str();
break;
[globalisel][tblgen] Add support for ComplexPatterns Summary: Adds a new kind of MachineOperand: MO_Placeholder. This operand must not appear in the MIR and only exists as a way of creating an 'uninitialized' operand until a matcher function overwrites it. Depends on D30046, D29712 Reviewers: t.p.northover, ab, rovka, aditya_nandakumar, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30089 llvm-svn: 297782
2017-03-14 21:32:08 +00:00
}
[tablegen][globalisel] Trivial changes to reduce size of following patch. NFC. Summary: * Move namespace { * Trivial: Typo * RuleMatcher: Separate class and definition * Trivial: const findNodeEquiv Reviewers: t.p.northover, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: rovka Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30531 llvm-svn: 297884
2017-03-15 20:18:38 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (!HasUnsupportedPredicate)
return Error::success();
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
return failedImport(Explanation);
[tablegen][globalisel] Trivial changes to reduce size of following patch. NFC. Summary: * Move namespace { * Trivial: Typo * RuleMatcher: Separate class and definition * Trivial: const findNodeEquiv Reviewers: t.p.northover, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: rovka Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30531 llvm-svn: 297884
2017-03-15 20:18:38 +00:00
}
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
static const Record *getInitValueAsRegClass(const Init *V) {
if (const DefInit *VDefInit = dyn_cast<DefInit>(V)) {
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
if (VDefInit->getDef()->isSubClassOf("RegisterOperand"))
return VDefInit->getDef()->getValueAsDef("RegClass");
if (VDefInit->getDef()->isSubClassOf("RegisterClass"))
return VDefInit->getDef();
[globalisel][tablegen] Add support for importing 'imm' operands. Summary: This patch enables the import of rules containing 'imm' operands that do not constrain the acceptable values using predicates. Support for ImmLeaf will arrive in a later patch. Depends on D35681 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35833 llvm-svn: 310343
2017-08-08 10:44:31 +00:00
}
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
return nullptr;
[globalisel][tablegen] Remove unnecessary ; to satisfy ubuntu-gcc7.1-werror. llvm-svn: 310357
2017-08-08 13:21:26 +00:00
}
[globalisel][tablegen] Add support for importing 'imm' operands. Summary: This patch enables the import of rules containing 'imm' operands that do not constrain the acceptable values using predicates. Support for ImmLeaf will arrive in a later patch. Depends on D35681 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35833 llvm-svn: 310343
2017-08-08 10:44:31 +00:00
[NFC][RFC][TableGen] Split GlobalISelEmitter.cpp This patch splits the GlobalISelEmitter.cpp file, which imports DAG ISel patterns for GISel, into separate "GISelMatchTable.h/cpp" files. The main motive is readability & maintainability. GlobalISelEmitter.cpp was about 6400 lines of mixed code, some bits implementing the match table codegen, some others dedicated to importing DAG patterns. Now it's down to 2700 + a 2150 header + 2000 impl. It's a tiny bit more lines overall but that's to be expected - moving inline definitions to out-of-line, adding comments in the .cpp, etc. all of that takes additional space, but I think the tradeoff is worth it. I did as little unrelated code changes as possible, I would say the biggest change is the introduction of the `gi` namespace used to prevent name conflicts/ODR violations with type common names such as `Matcher`. It was previously not an issue because all of the code was in an anonymous namespace. This moves all of the "match table" code out of the file, so predicates, rules, and actions are all separated now. I believe this helps separating concerns, now `GlobalISelEmitter.cpp` is more focused on importing DAG patterns into GI, instead of also containing the whole match table internals as well. Note: the new files have a "GISel" prefix to make them distinct from the other "GI" files in the same folder, which are for the combiner. Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D151432
2023-05-25 14:19:08 +02:00
static std::string getScopedName(unsigned Scope, const std::string &Name) {
return ("pred:" + Twine(Scope) + ":" + Name).str();
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
}
[GISel][TableGen] Fix accidental operand name clashes in patterns (#74492) When importing instruction selection patterns into GlobalISel, the operands matched in the "source" DAG are copied into corresponding operands of the "destination" DAG according to their names (such as Rd). If multiple operands in the source DAG share the same name, a GIM_CheckIsSameOperand predicate makes instruction selector check the corresponding operands for equality (at compiler run-time) as part of matching the source pattern. The Def operands of the root node of the destination DAG are handled specially. The operands of the instruction corresponding to the root node are taken and GIM_CheckRegBankForClass predicates are tablegen-erated accordingly. If by coincidence the Def operand in question has the same name as one of the named operands in the pattern, a GIM_CheckIsSameOperand predicate is automatically added that is likely to prevent matching the source of otherwise applicable selection pattern at compiler run-time. This patch mangles the Def operand names taken from the instruction corresponding to the root of the destination DAG (for example, "Rd" becomes "DstI[Rd]") preventing unexpected name clashes with pattern's named operands. The patch consists of three sets of changes: * changes to the GlobalISelEmitter.cpp file are the actual fix * a test case is added to GlobalISelEmitter.td file as a regression test * everything else is the biggest and least interesting part - updates to the existing test cases: renames of the form Rd -> DstI[Rd] inside the inline comments in tablegen-erated code
2023-12-10 13:25:11 +03:00
static std::string getMangledRootDefName(StringRef DefOperandName) {
return ("DstI[" + DefOperandName + "]").str();
}
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
//===- GlobalISelEmitter class --------------------------------------------===//
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130) Previously, tblgen would reject patterns where one of its nested instructions produced more than one result. These arise when the instruction definition contains 'outs' as well as 'Defs'. This patch fixes that by always taking the first result, which is how these situations are handled in SelectionIDAG. Original patch: https://reviews.llvm.org/D86617 Continued as: https://github.com/llvm/llvm-project/pull/81130
2023-11-03 12:44:38 +01:00
static Expected<LLTCodeGen> getInstResultType(const TreePatternNode &Dst,
const CodeGenTarget &Target) {
// While we allow more than one output (both implicit and explicit defs)
// below, we only expect one explicit def here.
assert(Dst.getOperator()->isSubClassOf("Instruction"));
CodeGenInstruction &InstInfo = Target.getInstruction(Dst.getOperator());
[GlobalISel][AMDGPU] Import patterns with multiple defs (#84171) Fixes #63216
2024-03-08 09:39:10 +01:00
if (!InstInfo.Operands.NumDefs)
return failedImport("Dst pattern child needs a def");
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130) Previously, tblgen would reject patterns where one of its nested instructions produced more than one result. These arise when the instruction definition contains 'outs' as well as 'Defs'. This patch fixes that by always taking the first result, which is how these situations are handled in SelectionIDAG. Original patch: https://reviews.llvm.org/D86617 Continued as: https://github.com/llvm/llvm-project/pull/81130
2023-11-03 12:44:38 +01:00
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
ArrayRef<TypeSetByHwMode> ChildTypes = Dst.getExtTypes();
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130) Previously, tblgen would reject patterns where one of its nested instructions produced more than one result. These arise when the instruction definition contains 'outs' as well as 'Defs'. This patch fixes that by always taking the first result, which is how these situations are handled in SelectionIDAG. Original patch: https://reviews.llvm.org/D86617 Continued as: https://github.com/llvm/llvm-project/pull/81130
2023-11-03 12:44:38 +01:00
if (ChildTypes.size() < 1)
return failedImport("Dst pattern child has no result");
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130) Previously, tblgen would reject patterns where one of its nested instructions produced more than one result. These arise when the instruction definition contains 'outs' as well as 'Defs'. This patch fixes that by always taking the first result, which is how these situations are handled in SelectionIDAG. Original patch: https://reviews.llvm.org/D86617 Continued as: https://github.com/llvm/llvm-project/pull/81130
2023-11-03 12:44:38 +01:00
// If there are multiple results, just take the first one (this is how
// SelectionDAG does it).
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<LLTCodeGen> MaybeOpTy;
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
if (ChildTypes.front().isMachineValueType()) {
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
MaybeOpTy = MVTToLLT(ChildTypes.front().getMachineValueType().SimpleTy);
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
}
if (!MaybeOpTy)
return failedImport("Dst operand has an unsupported type");
return *MaybeOpTy;
}
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
class GlobalISelEmitter final : public GlobalISelMatchTableExecutorEmitter {
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
public:
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
explicit GlobalISelEmitter(const RecordKeeper &RK);
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
void emitAdditionalImpl(raw_ostream &OS) override;
void emitMIPredicateFns(raw_ostream &OS) override;
void emitI64ImmPredicateFns(raw_ostream &OS) override;
void emitAPFloatImmPredicateFns(raw_ostream &OS) override;
void emitAPIntImmPredicateFns(raw_ostream &OS) override;
[RFC][TableGen][GlobalISel] Add Combiner Match Table Backend Adds a new backend to power the GISel Combiners using the InstructionSelector's match tables. This does not depend on any of the data structures created for the current combiner and is intended to replace it entirely. See the RFC for more details: https://discourse.llvm.org/t/rfc-matchtable-based-globalisel-combiners/71457/6 Note: this would replace D141135. Reviewed By: aemerson, arsenm Differential Revision: https://reviews.llvm.org/D153757
2023-06-26 13:23:18 +02:00
void emitTestSimplePredicate(raw_ostream &OS) override;
void emitRunCustomAction(raw_ostream &OS) override;
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
[GlobalISel] Add dead flags to implicit defs in ISel Checks for implicit defs that are unused within a pattern and mark them as dead. This is done directly at the TableGen level forr efficiency. The instructions are directly created with the "dead" operand and no further analysis is needed later. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D157273
2023-08-07 12:59:24 +02:00
void postProcessRule(RuleMatcher &M);
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
const CodeGenTarget &getTarget() const override { return Target; }
StringRef getClassName() const override { return ClassName; }
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
void run(raw_ostream &OS);
private:
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
std::string ClassName;
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
const RecordKeeper &RK;
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
const CodeGenDAGPatterns CGP;
const CodeGenTarget &Target;
TableGen/GlobalISel: Don't reconstruct CodeGenRegBank The maps for dealing with the relationships between different register classes and subregister indexes rely on unique pointers for every class/index. By constructing a second copy of CodeGenRegBank, two different pointer values existed for a given subregister depending on where you were querying. Use the existing CodeGenRegBank owned by the CodeGenTarget instead of constructing a second copy. This avoids incorrectly failing map lookups in a future change.
2020-01-14 13:48:34 -05:00
CodeGenRegBank &CGRegs;
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
ArrayRef<const Record *> AllPatFrags;
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
[globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFC Summary: There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load and atomic loads are handled by a separate node. However, this is not true of GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity of the operation. As a result, this mapping must also add a predicate that checks for non-atomic MachineMemOperands. This is NFC since these nodes always have predicates in practice and are therefore always rejected at the moment. Depends on D37443 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37445 llvm-svn: 315843
2017-10-15 02:41:12 +00:00
/// Keep track of the equivalence between SDNodes and Instruction by mapping
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
2017-12-05 05:52:07 +00:00
/// SDNodes to the GINodeEquiv mapping. We need to map to the GINodeEquiv to
/// check for attributes on the relation such as CheckMMOIsNonAtomic.
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
/// This is defined using 'GINodeEquiv' in the target description.
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
DenseMap<const Record *, const Record *> NodeEquivs;
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
[globalisel][tblgen] Add support for ComplexPatterns Summary: Adds a new kind of MachineOperand: MO_Placeholder. This operand must not appear in the MIR and only exists as a way of creating an 'uninitialized' operand until a matcher function overwrites it. Depends on D30046, D29712 Reviewers: t.p.northover, ab, rovka, aditya_nandakumar, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30089 llvm-svn: 297782
2017-03-14 21:32:08 +00:00
/// Keep track of the equivalence between ComplexPattern's and
/// GIComplexOperandMatcher. Map entries are specified by subclassing
/// GIComplexPatternEquiv.
DenseMap<const Record *, const Record *> ComplexPatternEquivs;
[GlobalISel][TableGen] Add support for SDNodeXForm Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
2018-01-16 18:44:05 +00:00
/// Keep track of the equivalence between SDNodeXForm's and
/// GICustomOperandRenderer. Map entries are specified by subclassing
/// GISDNodeXFormEquiv.
DenseMap<const Record *, const Record *> SDNodeXFormEquivs;
[GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAG This patch changes GlobalISelEmitter to rank patterns similar to how the DAG does it (ie it computes a score for a pattern and adds the added complexity to it). This is so that the decision tree for GISelSelector remains compatible with that of SelectionDAG. https://reviews.llvm.org/D43270 llvm-svn: 325401
2018-02-16 22:37:15 +00:00
/// Keep track of Scores of PatternsToMatch similar to how the DAG does.
/// This adds compatibility for RuleMatchers to use this for ordering rules.
DenseMap<uint64_t, int> RuleMatcherScores;
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
2017-11-16 00:46:35 +00:00
// Rule coverage information.
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<CodeGenCoverage> RuleCoverage;
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
2017-11-16 00:46:35 +00:00
AMDGPU/GlobalISel/Emitter Support for predicate code that uses operands Predicates with 'let PredicateCodeUsesOperands = 1' want to examine matched operands. When we encounter predicate code that uses operands, analyze its named operand arguments and create a map between argument index and name. Later, when leaf node with name is encountered, emit GIM_RecordNamedOperand that will store that operand at its argument index in operand list. This operand list will be an argument to c++ code of the predicate. Differential Revision: https://reviews.llvm.org/D87285
2020-09-14 10:39:25 +02:00
/// Variables used to help with collecting of named operands for predicates
/// with 'let PredicateCodeUsesOperands = 1'. WaitingForNamedOperands is set
/// to the number of named operands that predicate expects. Store locations in
/// StoreIdxForName correspond to the order in which operand names appear in
/// predicate's argument list.
[TableGen][GISel] Fix incorrect binding of predicate operands upon `PredicateUsesOperands = 1` (#68125) When `PredicateUsesOperands` is set to true, GlobalISelEmitter preserves the original index of predicate operands and uses that information on each predicate usage. However, previously it only looked up the original index for "actual" operands (i.e. operands of a predicate usage) that are leaf nodes, which is an incorrect assumption. This patch fix it by generalizing the acceptable kinds of actual operands for predicate as well as checking the existance of bound predicate operands.
2023-10-05 08:57:15 -07:00
/// When we visit named operand and WaitingForNamedOperands is not zero, add
/// matcher that will record operand and decrease counter.
AMDGPU/GlobalISel/Emitter Support for predicate code that uses operands Predicates with 'let PredicateCodeUsesOperands = 1' want to examine matched operands. When we encounter predicate code that uses operands, analyze its named operand arguments and create a map between argument index and name. Later, when leaf node with name is encountered, emit GIM_RecordNamedOperand that will store that operand at its argument index in operand list. This operand list will be an argument to c++ code of the predicate. Differential Revision: https://reviews.llvm.org/D87285
2020-09-14 10:39:25 +02:00
unsigned WaitingForNamedOperands = 0;
StringMap<unsigned> StoreIdxForName;
Reapply r332907 "[GlobalISel] Improving InstructionSelect's performance by reducing MatchTable..." Apparently the compile time problem was caused by the fact that not all compilers / STL implementations can automatically convert std::unique_ptr<Derived> to std::unique_ptr<Base>. Fixed (hopefully) by making sure it's std::unique_ptr<Derived>&& (rvalue ref) to std::unique_ptr<Base> conversion instead. llvm-svn: 332917
2018-05-21 23:28:51 +00:00
void gatherOpcodeValues();
void gatherTypeIDValues();
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
void gatherNodeEquivs();
[globalisel][tablegen] Add support for C++ predicates on PatFrags and use it to support BFC on ARM. So far, we've only handled special cases of PatFrag like ImmLeaf. This patch adds support for the remaining cases using similar mechanisms. Like most C++ code from SelectionDAG, GISel and DAGISel expect to operate on different types and representations and as such the code is not compatible between the two. It's therefore necessary to add an alternative implementation in the GISelPredicateCode field. The target test for this feature could easily be done with IntImmLeaf and this would save on a little boilerplate. The reason I've chosen to implement this using PatFrag.GISelPredicateCode and not IntImmLeaf is because I was unable to find a rule that was blocked solely by lack of support for PatFrag predicates. I found that the ones I investigated as being likely candidates for the test were further blocked by other things. llvm-svn: 334871
2018-06-15 23:13:43 +00:00
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
const Record *findNodeEquiv(const Record *N) const;
const CodeGenInstruction *getEquivNode(const Record &Equiv,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &N) const;
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
Error importRulePredicates(RuleMatcher &M,
ArrayRef<const Record *> Predicates);
[globalisel][tablegen] Add support for C++ predicates on PatFrags and use it to support BFC on ARM. So far, we've only handled special cases of PatFrag like ImmLeaf. This patch adds support for the remaining cases using similar mechanisms. Like most C++ code from SelectionDAG, GISel and DAGISel expect to operate on different types and representations and as such the code is not compatible between the two. It's therefore necessary to add an alternative implementation in the GISelPredicateCode field. The target test for this feature could easily be done with IntImmLeaf and this would save on a little boilerplate. The reason I've chosen to implement this using PatFrag.GISelPredicateCode and not IntImmLeaf is because I was unable to find a rule that was blocked solely by lack of support for PatFrag predicates. I found that the ones I investigated as being likely candidates for the test were further blocked by other things. llvm-svn: 334871
2018-06-15 23:13:43 +00:00
Expected<InstructionMatcher &>
createAndImportSelDAGMatcher(RuleMatcher &Rule,
InstructionMatcher &InsnMatcher,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &Src, unsigned &TempOpIdx);
[TableGen] Change CodeGenInstruction record members to const (#107921) Change CodeGenInstruction::{TheDef, InfereredFrom} to const pointers. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-11 08:52:26 -07:00
Error importComplexPatternOperandMatcher(OperandMatcher &OM, const Record *R,
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
unsigned &TempOpIdx) const;
Error importChildMatcher(RuleMatcher &Rule, InstructionMatcher &InsnMatcher,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &SrcChild,
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
bool OperandIsAPointer, bool OperandIsImmArg,
unsigned OpIdx, unsigned &TempOpIdx);
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
Expected<BuildMIAction &> createAndImportInstructionRenderer(
RuleMatcher &M, InstructionMatcher &InsnMatcher,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &Src, const TreePatternNode &Dst);
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
Expected<action_iterator> createAndImportSubInstructionRenderer(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
action_iterator InsertPt, RuleMatcher &M, const TreePatternNode &Dst,
const TreePatternNode &Src, unsigned TempReg);
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
Expected<action_iterator>
createInstructionRenderer(action_iterator InsertPt, RuleMatcher &M,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &Dst);
TableGen/GlobalISel: Allow output instructions with multiple defs The DAG behavior allows matchching input patterns with a single result to the first result of an output instruction that defines multiple results. The remaining defs are implicitly dead. This starts to fix using manual selection for AMDGPU add/sub (although it's still needed, mostly because it's also still needed for G_PTR_ADD).
2020-07-13 08:59:38 -04:00
[GlobalISel][AMDGPU] Import patterns with multiple defs (#84171) Fixes #63216
2024-03-08 09:39:10 +01:00
Expected<action_iterator>
importExplicitDefRenderers(action_iterator InsertPt, RuleMatcher &M,
BuildMIAction &DstMIBuilder,
const TreePatternNode &Src,
const TreePatternNode &Dst, unsigned Start = 0);
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
[GlobalISelEmitter] handle operand without MVT/class There are some patterns in td files without MVT/class set for some operands in target pattern that are from the source pattern. This prevents GlobalISelEmitter from adding them as a valid rule, because the target child operand is an unsupported kind operand. For now, for a leaf child, only IntInit and DefInit are handled in GlobalISelEmitter. This issue can be workaround by adding MVT/class to the patterns in the td files, like the workarounds for patterns anyext and setcc in PPCInstrInfo.td in D140878. To avoid adding the same workarounds for other patterns in td files, this patch tries to handle the UnsetInit case in GlobalISelEmitter. Adding the new handling allows us to remove the workarounds in the td files and also generates many selection rules for PPC target. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D141247
2023-01-09 04:07:52 +00:00
Expected<action_iterator> importExplicitUseRenderers(
action_iterator InsertPt, RuleMatcher &M, BuildMIAction &DstMIBuilder,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const llvm::TreePatternNode &Dst, const TreePatternNode &Src);
[GlobalISelEmitter] handle operand without MVT/class There are some patterns in td files without MVT/class set for some operands in target pattern that are from the source pattern. This prevents GlobalISelEmitter from adding them as a valid rule, because the target child operand is an unsupported kind operand. For now, for a leaf child, only IntInit and DefInit are handled in GlobalISelEmitter. This issue can be workaround by adding MVT/class to the patterns in the td files, like the workarounds for patterns anyext and setcc in PPCInstrInfo.td in D140878. To avoid adding the same workarounds for other patterns in td files, this patch tries to handle the UnsetInit case in GlobalISelEmitter. Adding the new handling allows us to remove the workarounds in the td files and also generates many selection rules for PPC target. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D141247
2023-01-09 04:07:52 +00:00
Expected<action_iterator> importExplicitUseRenderer(
action_iterator InsertPt, RuleMatcher &Rule, BuildMIAction &DstMIBuilder,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &DstChild, const TreePatternNode &Src);
[TableGen] New default operand "undef_tied_input" This is a new special identifier which you can use as a default in OperandWithDefaultOps. The idea is that you use it for an input operand of an instruction that's tied to an output operand, and its semantics are that (in the default case) the input operand's value is not used at all. The detailed effect is that when instruction selection emits the instruction in the form of a pre-regalloc MachineInstr, it creates an IMPLICIT_DEF node to use as that input. If you're creating an MCInst with explicit register names, then the right handling would be to set the input operand to the same register as the output one (honouring the tie) and to add the 'undef' flag indicating that that register is deemed to acquire a new don't-care definition just before we read it. But I haven't done that in this commit, because there was no need to - no Tablegen backend seems to autogenerate default fields in an MCInst. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60696 llvm-svn: 362064
2019-05-30 07:30:37 +00:00
Error importDefaultOperandRenderers(action_iterator InsertPt, RuleMatcher &M,
BuildMIAction &DstMIBuilder,
[GISel][TableGen] Enhance default ops support (#75689) - Instead of checking the default ops directly, this change queries DAG default operands collected during patterns reading. It does not only simplify the code but also handle few cases where integer values are converted from convertible types, such as 'bits'. - A test case is added GlobalISelEmitter.td as the regression test of default 'bits' values.
2023-12-17 15:02:10 -05:00
const DAGDefaultOperand &DefaultOp) const;
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
Error importImplicitDefRenderers(BuildMIAction &DstMIBuilder,
ArrayRef<const Record *> ImplicitDefs) const;
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
/// Analyze pattern \p P, returning a matcher for it if possible.
/// Otherwise, return an Error explaining why we don't support it.
Expected<RuleMatcher> runOnPattern(const PatternToMatch &P);
[globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule. Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300993
2017-04-21 15:59:56 +00:00
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
void declareSubtargetFeature(const Record *Predicate);
[globalisel][tablegen] Import signextload and zeroextload. Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to correct situations where SelectionDAG and GlobalISel disagree on representation. For example, it would rewrite: (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16> to: (sext:i32 (load:i16 $ptr)<<unindexedload>>) I'd have preferred to replace the fragments and have the expansion happen naturally as part of PatFrag expansion but the type inferencing system can't cope with loads of types narrower than those mentioned in register classes. This is because the SDTCisInt's on the sext constrain both the result and operand to the 'legal' integer types (where legal is defined as 'a register class can contain the type') which immediately rules the narrower types out. Several targets (those with only one legal integer type) would then go on to crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types for the result of the extend. Also, improve isObviouslySafeToFold() slightly to automatically return true for neighbouring instructions. There can't be any re-ordering problems if re-ordering isn't happenning. We'll need to improve it further to handle sign/zero-extending loads when the extend and load aren't immediate neighbours though. llvm-svn: 317971
2017-11-11 03:23:44 +00:00
[GlobalISel][RISCV][TableGen] Teach GlobalISelEmitter about HwMode. Similar to SelectionDAG, this patch treats HwMode as an additional predicate that needs to be satisfied for GIM_CheckFeatures. The existing predicate passes around Record * that point to predicate records. While HwMode expansion creates a string that needs to be checked. Each HwMode predicate string is uniqued by a new map that assigns it an index. Each Rule stores the index, or -1 if HwMode doesn't apply. The HwMode indices each create a new Predicate feature bit and the check string from the HwMode is used to set the feature bit. GIM_CheckFeatures is emitted when the rule has Predicates or the HwModeIdx is not -1. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D158660
2023-08-23 21:04:28 -07:00
unsigned declareHwModeCheck(StringRef HwModeFeatures);
Reapply r332907 "[GlobalISel] Improving InstructionSelect's performance by reducing MatchTable..." Apparently the compile time problem was caused by the fact that not all compilers / STL implementations can automatically convert std::unique_ptr<Derived> to std::unique_ptr<Base>. Fixed (hopefully) by making sure it's std::unique_ptr<Derived>&& (rvalue ref) to std::unique_ptr<Base> conversion instead. llvm-svn: 332917
2018-05-21 23:28:51 +00:00
MatchTable buildMatchTable(MutableArrayRef<RuleMatcher> Rules, bool Optimize,
bool WithCoverage);
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
/// Infer a CodeGenRegisterClass for the type of \p SuperRegNode. The returned
/// CodeGenRegisterClass will support the CodeGenRegisterClass of
/// \p SubRegNode, and the subregister index defined by \p SubRegIdxNode.
[llvm] Use std::nullopt instead of None in comments (NFC) This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-04 17:12:44 -08:00
/// If no register class is found, return std::nullopt.
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<const CodeGenRegisterClass *>
[GlobalISel] Import patterns containing SUBREG_TO_REG Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns. - Split `inferSuperRegisterClass` into two functions, one which tries to use an existing TreePatternNode (`inferSuperRegisterClassForNode`), and one that doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause for the split. - Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and update it. - Update impacted tests in the AArch64 and X86 backends. This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness. Differential Revision: https://reviews.llvm.org/D66769 llvm-svn: 370254
2019-08-28 20:12:31 +00:00
inferSuperRegisterClassForNode(const TypeSetByHwMode &Ty,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &SuperRegNode,
const TreePatternNode &SubRegIdxNode);
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<CodeGenSubRegIndex *>
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
inferSubRegIndexForNode(const TreePatternNode &SubRegIdxNode);
[GlobalISel] Import patterns containing SUBREG_TO_REG Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns. - Split `inferSuperRegisterClass` into two functions, one which tries to use an existing TreePatternNode (`inferSuperRegisterClassForNode`), and one that doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause for the split. - Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and update it. - Update impacted tests in the AArch64 and X86 backends. This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness. Differential Revision: https://reviews.llvm.org/D66769 llvm-svn: 370254
2019-08-28 20:12:31 +00:00
/// Infer a CodeGenRegisterClass which suppoorts \p Ty and \p SubRegIdxNode.
[llvm] Use std::nullopt instead of None in comments (NFC) This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-04 17:31:16 -08:00
/// Return std::nullopt if no such class exists.
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<const CodeGenRegisterClass *>
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
inferSuperRegisterClass(const TypeSetByHwMode &Ty,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &SubRegIdxNode);
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
/// Return the CodeGenRegisterClass associated with \p Leaf if it has one.
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<const CodeGenRegisterClass *>
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
getRegClassFromLeaf(const TreePatternNode &Leaf);
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
[llvm] Use std::nullopt instead of None in comments (NFC) This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-04 17:31:16 -08:00
/// Return a CodeGenRegisterClass for \p N if one can be found. Return
/// std::nullopt otherwise.
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<const CodeGenRegisterClass *>
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
inferRegClassFromPattern(const TreePatternNode &N);
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
[TableGen][GISel] Extract helper function for constraining operands (#115148) As a side effect, this fixes COPY_TO_REGCLASS not being constrained if it is not top-level (the reason for changes in tests).
2024-11-07 07:16:54 +03:00
Error constrainOperands(action_iterator InsertPt, RuleMatcher &M,
unsigned InsnID, const TreePatternNode &Dst);
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. This needs some tablegen changes so that we can actually import the patterns properly. Differential Revision: https://reviews.llvm.org/D102204
2021-01-24 00:35:15 -08:00
/// Return the size of the MemoryVT in this predicate, if possible.
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<unsigned>
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. This needs some tablegen changes so that we can actually import the patterns properly. Differential Revision: https://reviews.llvm.org/D102204
2021-01-24 00:35:15 -08:00
getMemSizeBitsFromPredicate(const TreePredicateFn &Predicate);
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
// Add builtin predicates.
Expected<InstructionMatcher &>
addBuiltinPredicates(const Record *SrcGIEquivOrNull,
const TreePredicateFn &Predicate,
InstructionMatcher &InsnMatcher, bool &HasAddedMatcher);
Revert r332907 "[GlobalISel] Improving InstructionSelect's performance by reducing MatchTable..." There is a compile time error I didn't see locally, investigating now. llvm-svn: 332912
2018-05-21 22:21:24 +00:00
};
[GlobalISel] Improving InstructionSelect's performance by reducing MatchTable, mostly NFC, perf patch 1 This patch starts a series of patches that decrease time spent by GlobalISel in its InstructionSelect pass by roughly 60% for -O0 builds for large inputs as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64. The performance improvements are achieved solely by reducing the number of matching GIM_* opcodes executed by the MatchTable's interpreter during the selection by approx. a factor of 30, which also brings contribution of this particular part of the selection process to the overall runtime of InstructionSelect pass down from approx. 60-70% to 5-7%, thus making further improvements in this particular direction not very profitable. The improvements described above are expected for any target that doesn't have many complex patterns. The targets that do should strictly benefit from the changes, but by how much exactly is hard to estimate beforehand. It's also likely that such target WILL benefit from further improvements to MatchTable, most likely the ones that bring it closer to a perfect decision tree. This commit specifically is rather large mostly NFC commit that does necessary preparation work and refactoring, there will be a following series of small patches introducing a specific optimization each shortly after. This commit specifically is expected to cause a small compile time regression (around 2.5% of InstructionSelect pass time), which should be fixed by the next commit of the series. Every commit planned shares the same Phabricator Review. Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 332907
2018-05-21 22:04:39 +00:00
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
StringRef getPatFragPredicateEnumName(const Record *R) { return R->getName(); }
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
Reapply r332907 "[GlobalISel] Improving InstructionSelect's performance by reducing MatchTable..." Apparently the compile time problem was caused by the fact that not all compilers / STL implementations can automatically convert std::unique_ptr<Derived> to std::unique_ptr<Base>. Fixed (hopefully) by making sure it's std::unique_ptr<Derived>&& (rvalue ref) to std::unique_ptr<Base> conversion instead. llvm-svn: 332917
2018-05-21 23:28:51 +00:00
void GlobalISelEmitter::gatherOpcodeValues() {
InstructionOpcodeMatcher::initOpcodeValuesMap(Target);
}
void GlobalISelEmitter::gatherTypeIDValues() {
LLTOperandMatcher::initTypeIDValuesMap();
}
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
void GlobalISelEmitter::gatherNodeEquivs() {
assert(NodeEquivs.empty());
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
for (const Record *Equiv : RK.getAllDerivedDefinitions("GINodeEquiv"))
[globalisel][tablegen] Map ld and st to G_LOAD and G_STORE. NFC Summary: There is an important mismatch between ISD::LOAD and G_LOAD (and likewise for ISD::STORE and G_STORE). In SelectionDAG, ISD::LOAD is a non-atomic load and atomic loads are handled by a separate node. However, this is not true of GlobalISel's G_LOAD. For G_LOAD, the MachineMemOperand indicates the atomicity of the operation. As a result, this mapping must also add a predicate that checks for non-atomic MachineMemOperands. This is NFC since these nodes always have predicates in practice and are therefore always rejected at the moment. Depends on D37443 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37445 llvm-svn: 315843
2017-10-15 02:41:12 +00:00
NodeEquivs[Equiv->getValueAsDef("Node")] = Equiv;
[globalisel][tblgen] Add support for ComplexPatterns Summary: Adds a new kind of MachineOperand: MO_Placeholder. This operand must not appear in the MIR and only exists as a way of creating an 'uninitialized' operand until a matcher function overwrites it. Depends on D30046, D29712 Reviewers: t.p.northover, ab, rovka, aditya_nandakumar, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30089 llvm-svn: 297782
2017-03-14 21:32:08 +00:00
assert(ComplexPatternEquivs.empty());
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
for (const Record *Equiv :
RK.getAllDerivedDefinitions("GIComplexPatternEquiv")) {
const Record *SelDAGEquiv = Equiv->getValueAsDef("SelDAGEquivalent");
[globalisel][tblgen] Add support for ComplexPatterns Summary: Adds a new kind of MachineOperand: MO_Placeholder. This operand must not appear in the MIR and only exists as a way of creating an 'uninitialized' operand until a matcher function overwrites it. Depends on D30046, D29712 Reviewers: t.p.northover, ab, rovka, aditya_nandakumar, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30089 llvm-svn: 297782
2017-03-14 21:32:08 +00:00
if (!SelDAGEquiv)
continue;
ComplexPatternEquivs[SelDAGEquiv] = Equiv;
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
}
assert(SDNodeXFormEquivs.empty());
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
for (const Record *Equiv :
RK.getAllDerivedDefinitions("GISDNodeXFormEquiv")) {
const Record *SelDAGEquiv = Equiv->getValueAsDef("SelDAGEquivalent");
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
if (!SelDAGEquiv)
continue;
SDNodeXFormEquivs[SelDAGEquiv] = Equiv;
}
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
}
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
const Record *GlobalISelEmitter::findNodeEquiv(const Record *N) const {
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
return NodeEquivs.lookup(N);
}
[globalisel] Update GlobalISel emitter to match new representation of extending loads Summary: Previously, a extending load was represented at (G_*EXT (G_LOAD x)). This had a few drawbacks: * G_LOAD had to be legal for all sizes you could extend from, even if registers didn't naturally hold those sizes. * All sizes you could extend from had to be allocatable just in case the extend went missing (e.g. by optimization). * At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we improve optimization of extends and truncates, this legality requirement would spread without considerable care w.r.t when certain combines were permitted. * The SelectionDAG importer required some ugly and fragile pattern rewriting to translate patterns into this style. This patch changes the representation to: * (G_[SZ]EXTLOAD x) * (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits() which resolves these issues by allowing targets to work entirely in their native register sizes, and by having a more direct translation from SelectionDAG patterns. Each extending load can be lowered by the legalizer into separate extends and loads, however a target that supports s1 will need the any-extending load to extend to at least s8 since LLVM does not represent memory accesses smaller than 8 bit. The legalizer can widenScalar G_LOAD into an any-extending load but sign/zero-extending loads need help from something else like a combiner pass. A follow-up patch that adds combiner helpers for for this will follow. The new representation requires that the MMO correctly reflect the memory access so this has been corrected in a couple tests. I've also moved the extending loads to their own tests since they are (mostly) separate opcodes now. Additionally, the re-write appears to have invalidated two tests from select-with-no-legality-check.mir since the matcher table no longer contains loads that result in s1's and they aren't legal in AArch64 anymore. Depends on D45540 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar Reviewed By: rtereshin Subscribers: javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45541 llvm-svn: 331601
2018-05-05 20:53:24 +00:00
const CodeGenInstruction *
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
GlobalISelEmitter::getEquivNode(const Record &Equiv,
const TreePatternNode &N) const {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (N.getNumChildren() >= 1) {
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 01:13:41 +00:00
// setcc operation maps to two different G_* instructions based on the type.
if (!Equiv.isValueUnset("IfFloatingPoint") &&
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
MVT(N.getChild(0).getSimpleType(0)).isFloatingPoint())
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 01:13:41 +00:00
return &Target.getInstruction(Equiv.getValueAsDef("IfFloatingPoint"));
}
[GlobalISel] convergent intrinsics Introduced the convergent equivalent of the existing G_INTRINSIC opcodes: - G_INTRINSIC_CONVERGENT - G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS Out of the targets that currently have some support for GlobalISel, the patch assumes that the convergent intrinsics only relevant to SPIRV and AMDGPU. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D154766
2023-07-31 12:14:34 +05:30
if (!Equiv.isValueUnset("IfConvergent") &&
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
N.getIntrinsicInfo(CGP)->isConvergent)
[GlobalISel] convergent intrinsics Introduced the convergent equivalent of the existing G_INTRINSIC opcodes: - G_INTRINSIC_CONVERGENT - G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS Out of the targets that currently have some support for GlobalISel, the patch assumes that the convergent intrinsics only relevant to SPIRV and AMDGPU. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D154766
2023-07-31 12:14:34 +05:30
return &Target.getInstruction(Equiv.getValueAsDef("IfConvergent"));
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
for (const TreePredicateCall &Call : N.getPredicateCalls()) {
TableGen/ISel: Allow PatFrag predicate code to access captured operands Summary: This simplifies writing predicates for pattern fragments that are automatically re-associated or commuted. For example, a followup patch adds patterns for fragments of the form (add (shl $x, $y), $z) to the AMDGPU backend. Such patterns are automatically commuted to (add $z, (shl $x, $y)), which makes it basically impossible to refer to $x, $y, and $z generically in the PredicateCode. With this change, the PredicateCode can refer to $x, $y, and $z simply as `Operands[i]`. Test confirmed that there are no changes to any of the generated files when building all (non-experimental) targets. Change-Id: I61c00ace7eed42c1d4edc4c5351174b56b77a79c Reviewers: arsenm, rampitec, RKSimon, craig.topper, hfinkel, uweigand Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D51994 llvm-svn: 347992
2018-11-30 14:15:13 +00:00
const TreePredicateFn &Predicate = Call.Fn;
GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD SelectionDAG has a target hook, getExtendForAtomicOps, which it uses in the computeKnownBits implementation for ATOMIC_LOAD. This is pretty ugly (as is having a separate load opcode for atomics), so instead allow making use of atomic zextload. Enable this for AArch64 since the DAG path defaults in to the zext behavior. The tablegen changes are pretty ugly, but partially helps migrate SelectionDAG from using ISD::ATOMIC_LOAD to regular ISD::LOAD with atomic memory operands. For now the DAG emitter will emit matchers for patterns which the DAG will not produce. I'm still a bit confused by the intent of the isLoad/isStore/isAtomic bits. The DAG implementation rejects trying to use any of these in combination. For now I've opted to make the isLoad checks also check isAtomic, although I think having isLoad and isAtomic set on these makes most sense.
2022-04-09 14:06:04 -04:00
if (!Equiv.isValueUnset("IfSignExtend") &&
(Predicate.isLoad() || Predicate.isAtomic()) &&
[globalisel] Update GlobalISel emitter to match new representation of extending loads Summary: Previously, a extending load was represented at (G_*EXT (G_LOAD x)). This had a few drawbacks: * G_LOAD had to be legal for all sizes you could extend from, even if registers didn't naturally hold those sizes. * All sizes you could extend from had to be allocatable just in case the extend went missing (e.g. by optimization). * At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we improve optimization of extends and truncates, this legality requirement would spread without considerable care w.r.t when certain combines were permitted. * The SelectionDAG importer required some ugly and fragile pattern rewriting to translate patterns into this style. This patch changes the representation to: * (G_[SZ]EXTLOAD x) * (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits() which resolves these issues by allowing targets to work entirely in their native register sizes, and by having a more direct translation from SelectionDAG patterns. Each extending load can be lowered by the legalizer into separate extends and loads, however a target that supports s1 will need the any-extending load to extend to at least s8 since LLVM does not represent memory accesses smaller than 8 bit. The legalizer can widenScalar G_LOAD into an any-extending load but sign/zero-extending loads need help from something else like a combiner pass. A follow-up patch that adds combiner helpers for for this will follow. The new representation requires that the MMO correctly reflect the memory access so this has been corrected in a couple tests. I've also moved the extending loads to their own tests since they are (mostly) separate opcodes now. Additionally, the re-write appears to have invalidated two tests from select-with-no-legality-check.mir since the matcher table no longer contains loads that result in s1's and they aren't legal in AArch64 anymore. Depends on D45540 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar Reviewed By: rtereshin Subscribers: javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45541 llvm-svn: 331601
2018-05-05 20:53:24 +00:00
Predicate.isSignExtLoad())
return &Target.getInstruction(Equiv.getValueAsDef("IfSignExtend"));
GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD SelectionDAG has a target hook, getExtendForAtomicOps, which it uses in the computeKnownBits implementation for ATOMIC_LOAD. This is pretty ugly (as is having a separate load opcode for atomics), so instead allow making use of atomic zextload. Enable this for AArch64 since the DAG path defaults in to the zext behavior. The tablegen changes are pretty ugly, but partially helps migrate SelectionDAG from using ISD::ATOMIC_LOAD to regular ISD::LOAD with atomic memory operands. For now the DAG emitter will emit matchers for patterns which the DAG will not produce. I'm still a bit confused by the intent of the isLoad/isStore/isAtomic bits. The DAG implementation rejects trying to use any of these in combination. For now I've opted to make the isLoad checks also check isAtomic, although I think having isLoad and isAtomic set on these makes most sense.
2022-04-09 14:06:04 -04:00
if (!Equiv.isValueUnset("IfZeroExtend") &&
(Predicate.isLoad() || Predicate.isAtomic()) &&
[globalisel] Update GlobalISel emitter to match new representation of extending loads Summary: Previously, a extending load was represented at (G_*EXT (G_LOAD x)). This had a few drawbacks: * G_LOAD had to be legal for all sizes you could extend from, even if registers didn't naturally hold those sizes. * All sizes you could extend from had to be allocatable just in case the extend went missing (e.g. by optimization). * At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we improve optimization of extends and truncates, this legality requirement would spread without considerable care w.r.t when certain combines were permitted. * The SelectionDAG importer required some ugly and fragile pattern rewriting to translate patterns into this style. This patch changes the representation to: * (G_[SZ]EXTLOAD x) * (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits() which resolves these issues by allowing targets to work entirely in their native register sizes, and by having a more direct translation from SelectionDAG patterns. Each extending load can be lowered by the legalizer into separate extends and loads, however a target that supports s1 will need the any-extending load to extend to at least s8 since LLVM does not represent memory accesses smaller than 8 bit. The legalizer can widenScalar G_LOAD into an any-extending load but sign/zero-extending loads need help from something else like a combiner pass. A follow-up patch that adds combiner helpers for for this will follow. The new representation requires that the MMO correctly reflect the memory access so this has been corrected in a couple tests. I've also moved the extending loads to their own tests since they are (mostly) separate opcodes now. Additionally, the re-write appears to have invalidated two tests from select-with-no-legality-check.mir since the matcher table no longer contains loads that result in s1's and they aren't legal in AArch64 anymore. Depends on D45540 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar Reviewed By: rtereshin Subscribers: javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45541 llvm-svn: 331601
2018-05-05 20:53:24 +00:00
Predicate.isZeroExtLoad())
return &Target.getInstruction(Equiv.getValueAsDef("IfZeroExtend"));
}
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 01:13:41 +00:00
[globalisel] Update GlobalISel emitter to match new representation of extending loads Summary: Previously, a extending load was represented at (G_*EXT (G_LOAD x)). This had a few drawbacks: * G_LOAD had to be legal for all sizes you could extend from, even if registers didn't naturally hold those sizes. * All sizes you could extend from had to be allocatable just in case the extend went missing (e.g. by optimization). * At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we improve optimization of extends and truncates, this legality requirement would spread without considerable care w.r.t when certain combines were permitted. * The SelectionDAG importer required some ugly and fragile pattern rewriting to translate patterns into this style. This patch changes the representation to: * (G_[SZ]EXTLOAD x) * (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits() which resolves these issues by allowing targets to work entirely in their native register sizes, and by having a more direct translation from SelectionDAG patterns. Each extending load can be lowered by the legalizer into separate extends and loads, however a target that supports s1 will need the any-extending load to extend to at least s8 since LLVM does not represent memory accesses smaller than 8 bit. The legalizer can widenScalar G_LOAD into an any-extending load but sign/zero-extending loads need help from something else like a combiner pass. A follow-up patch that adds combiner helpers for for this will follow. The new representation requires that the MMO correctly reflect the memory access so this has been corrected in a couple tests. I've also moved the extending loads to their own tests since they are (mostly) separate opcodes now. Additionally, the re-write appears to have invalidated two tests from select-with-no-legality-check.mir since the matcher table no longer contains loads that result in s1's and they aren't legal in AArch64 anymore. Depends on D45540 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar Reviewed By: rtereshin Subscribers: javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45541 llvm-svn: 331601
2018-05-05 20:53:24 +00:00
return &Target.getInstruction(Equiv.getValueAsDef("I"));
}
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
GlobalISelEmitter::GlobalISelEmitter(const RecordKeeper &RK)
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
: GlobalISelMatchTableExecutorEmitter(), RK(RK), CGP(RK),
Target(CGP.getTargetInfo()), CGRegs(Target.getRegBank()) {
ClassName = Target.getName().str() + "InstructionSelector";
}
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
//===- Emitter ------------------------------------------------------------===//
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
Error GlobalISelEmitter::importRulePredicates(
RuleMatcher &M, ArrayRef<const Record *> Predicates) {
for (const Record *Pred : Predicates) {
[TableGen] Store predicates in PatternToMatch as ListInit *. Add string for HwModeFeatures This uses to be how predicates were handled prior to HwMode being added. When the Predicates were converted to a std::vector it significantly increased the cost of a compare in GenerateVariants. Since ListInit's are uniquified by tablegen, we can use a simple pointer comparison to check for identical lists. In order to store the HwMode, we now add a separate string to PatternToMatch. This will be appended separately to the predicate string in getPredicateCheck. A new getPredicateRecords is added to allow GlobalISel and getPredicateCheck to both get the sorted list of Records. GlobalISel was ignoring any HwMode predicates before and still is. There is one slight change here, ListInits with different predicate orders aren't sorted so the filtering in GenerateVariants might fail to detect two isomorphic patterns with different predicate orders. This doesn't seem to be happening in tree today. My hope is this will allow us to remove all the BitVector tracking in GenerateVariants that was making up for predicates beeing expensive to compare. There's a decent amount of heap allocations there on large targets like X86, AMDGPU, and RISCV. Differential Revision: https://reviews.llvm.org/D100691
2021-04-28 11:13:10 -07:00
if (Pred->getValueAsString("CondString").empty())
TableGen support for parameterized register class information This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
2017-09-14 16:56:21 +00:00
continue;
[TableGen] Store predicates in PatternToMatch as ListInit *. Add string for HwModeFeatures This uses to be how predicates were handled prior to HwMode being added. When the Predicates were converted to a std::vector it significantly increased the cost of a compare in GenerateVariants. Since ListInit's are uniquified by tablegen, we can use a simple pointer comparison to check for identical lists. In order to store the HwMode, we now add a separate string to PatternToMatch. This will be appended separately to the predicate string in getPredicateCheck. A new getPredicateRecords is added to allow GlobalISel and getPredicateCheck to both get the sorted list of Records. GlobalISel was ignoring any HwMode predicates before and still is. There is one slight change here, ListInits with different predicate orders aren't sorted so the filtering in GenerateVariants might fail to detect two isomorphic patterns with different predicate orders. This doesn't seem to be happening in tree today. My hope is this will allow us to remove all the BitVector tracking in GenerateVariants that was making up for predicates beeing expensive to compare. There's a decent amount of heap allocations there on large targets like X86, AMDGPU, and RISCV. Differential Revision: https://reviews.llvm.org/D100691
2021-04-28 11:13:10 -07:00
declareSubtargetFeature(Pred);
M.addRequiredFeature(Pred);
[globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule. Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300993
2017-04-21 15:59:56 +00:00
}
[globalisel][tablegen] Change Expected<bool> to Error and rename functions. Functions that still return Expected<X> are now called createAndImport*() Changing the return type was requested in the review comments for r299001 llvm-svn: 299063
2017-03-30 09:36:33 +00:00
return Error::success();
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<unsigned> GlobalISelEmitter::getMemSizeBitsFromPredicate(
const TreePredicateFn &Predicate) {
std::optional<LLTCodeGen> MemTyOrNone =
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. This needs some tablegen changes so that we can actually import the patterns properly. Differential Revision: https://reviews.llvm.org/D102204
2021-01-24 00:35:15 -08:00
MVTToLLT(getValueType(Predicate.getMemoryVT()));
if (!MemTyOrNone)
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. This needs some tablegen changes so that we can actually import the patterns properly. Differential Revision: https://reviews.llvm.org/D102204
2021-01-24 00:35:15 -08:00
// Align so unusual types like i1 don't get rounded down.
Reland [GlobalISel] NFC: Have LLT::getSizeInBits/Bytes return a TypeSize. This patch relands https://reviews.llvm.org/D104454, but fixes some failing builds on Mac OS which apparently has a different definition for size_t, that caused 'ambiguous operator overload' for the implicit conversion of TypeSize to a scalar value. This reverts commit b732e6c9a8438e5204ac96c8ca76f9b11abf98ff.
2021-06-27 16:07:19 +01:00
return llvm::alignTo(
static_cast<unsigned>(MemTyOrNone->get().getSizeInBits()), 8);
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. This needs some tablegen changes so that we can actually import the patterns properly. Differential Revision: https://reviews.llvm.org/D102204
2021-01-24 00:35:15 -08:00
}
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
Expected<InstructionMatcher &> GlobalISelEmitter::addBuiltinPredicates(
const Record *SrcGIEquivOrNull, const TreePredicateFn &Predicate,
InstructionMatcher &InsnMatcher, bool &HasAddedMatcher) {
if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) {
if (const ListInit *AddrSpaces = Predicate.getAddressSpaces()) {
SmallVector<unsigned, 4> ParsedAddrSpaces;
[LLVM][TableGen] Change all `Init` pointers to const (#112705) This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-10-18 07:50:22 -07:00
for (const Init *Val : AddrSpaces->getValues()) {
const IntInit *IntVal = dyn_cast<IntInit>(Val);
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
if (!IntVal)
return failedImport("Address space is not an integer");
ParsedAddrSpaces.push_back(IntVal->getValue());
}
if (!ParsedAddrSpaces.empty()) {
InsnMatcher.addPredicate<MemoryAddressSpacePredicateMatcher>(
0, ParsedAddrSpaces);
TableGen/GlobalISel: Make address space/align predicates consistent The builtin predicate handling has a strange behavior where the code assumes that a PatFrag is a stack of PatFrags, and each level adds at most one predicate. I don't think this particularly makes sense, especially without a diagnostic to ensure you aren't trying to set multiple at once. This wasn't followed for address spaces and alignment, which could potentially fall through to report no builtin predicate was added. Just switch these to follow the existing convention for now.
2022-04-05 10:36:57 -04:00
return InsnMatcher;
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
}
}
int64_t MinAlign = Predicate.getMinAlignment();
TableGen/GlobalISel: Make address space/align predicates consistent The builtin predicate handling has a strange behavior where the code assumes that a PatFrag is a stack of PatFrags, and each level adds at most one predicate. I don't think this particularly makes sense, especially without a diagnostic to ensure you aren't trying to set multiple at once. This wasn't followed for address spaces and alignment, which could potentially fall through to report no builtin predicate was added. Just switch these to follow the existing convention for now.
2022-04-05 10:36:57 -04:00
if (MinAlign > 0) {
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
InsnMatcher.addPredicate<MemoryAlignmentPredicateMatcher>(0, MinAlign);
TableGen/GlobalISel: Make address space/align predicates consistent The builtin predicate handling has a strange behavior where the code assumes that a PatFrag is a stack of PatFrags, and each level adds at most one predicate. I don't think this particularly makes sense, especially without a diagnostic to ensure you aren't trying to set multiple at once. This wasn't followed for address spaces and alignment, which could potentially fall through to report no builtin predicate was added. Just switch these to follow the existing convention for now.
2022-04-05 10:36:57 -04:00
return InsnMatcher;
}
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
}
// G_LOAD is used for both non-extending and any-extending loads.
if (Predicate.isLoad() && Predicate.isNonExtLoad()) {
InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>(
0, MemoryVsLLTSizePredicateMatcher::EqualTo, 0);
return InsnMatcher;
}
if (Predicate.isLoad() && Predicate.isAnyExtLoad()) {
InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>(
0, MemoryVsLLTSizePredicateMatcher::LessThan, 0);
return InsnMatcher;
}
if (Predicate.isStore()) {
if (Predicate.isTruncStore()) {
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. This needs some tablegen changes so that we can actually import the patterns properly. Differential Revision: https://reviews.llvm.org/D102204
2021-01-24 00:35:15 -08:00
if (Predicate.getMemoryVT() != nullptr) {
// FIXME: If MemoryVT is set, we end up with 2 checks for the MMO size.
auto MemSizeInBits = getMemSizeBitsFromPredicate(Predicate);
if (!MemSizeInBits)
return failedImport("MemVT could not be converted to LLT");
InsnMatcher.addPredicate<MemorySizePredicateMatcher>(0, *MemSizeInBits /
8);
} else {
InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>(
0, MemoryVsLLTSizePredicateMatcher::LessThan, 0);
}
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
return InsnMatcher;
}
if (Predicate.isNonTruncStore()) {
// We need to check the sizes match here otherwise we could incorrectly
// match truncating stores with non-truncating ones.
InsnMatcher.addPredicate<MemoryVsLLTSizePredicateMatcher>(
0, MemoryVsLLTSizePredicateMatcher::EqualTo, 0);
}
}
Reapply [Coverity] Fix explicit null dereferences This change fixes static code analysis errors Reviewed By: skan Differential Revision: https://reviews.llvm.org/D149506
2023-05-08 21:17:51 +08:00
assert(SrcGIEquivOrNull != nullptr && "Invalid SrcGIEquivOrNull value");
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
// No check required. We already did it by swapping the opcode.
if (!SrcGIEquivOrNull->isValueUnset("IfSignExtend") &&
Predicate.isSignExtLoad())
return InsnMatcher;
// No check required. We already did it by swapping the opcode.
if (!SrcGIEquivOrNull->isValueUnset("IfZeroExtend") &&
Predicate.isZeroExtLoad())
return InsnMatcher;
// No check required. G_STORE by itself is a non-extending store.
if (Predicate.isNonTruncStore())
return InsnMatcher;
if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) {
if (Predicate.getMemoryVT() != nullptr) {
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. This needs some tablegen changes so that we can actually import the patterns properly. Differential Revision: https://reviews.llvm.org/D102204
2021-01-24 00:35:15 -08:00
auto MemSizeInBits = getMemSizeBitsFromPredicate(Predicate);
if (!MemSizeInBits)
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
return failedImport("MemVT could not be converted to LLT");
InsnMatcher.addPredicate<MemorySizePredicateMatcher>(0,
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. This needs some tablegen changes so that we can actually import the patterns properly. Differential Revision: https://reviews.llvm.org/D102204
2021-01-24 00:35:15 -08:00
*MemSizeInBits / 8);
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
return InsnMatcher;
}
}
if (Predicate.isLoad() || Predicate.isStore()) {
// No check required. A G_LOAD/G_STORE is an unindexed load.
if (Predicate.isUnindexed())
return InsnMatcher;
}
if (Predicate.isAtomic()) {
if (Predicate.isAtomicOrderingMonotonic()) {
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("Monotonic");
return InsnMatcher;
}
if (Predicate.isAtomicOrderingAcquire()) {
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("Acquire");
return InsnMatcher;
}
if (Predicate.isAtomicOrderingRelease()) {
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("Release");
return InsnMatcher;
}
if (Predicate.isAtomicOrderingAcquireRelease()) {
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
"AcquireRelease");
return InsnMatcher;
}
if (Predicate.isAtomicOrderingSequentiallyConsistent()) {
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
"SequentiallyConsistent");
return InsnMatcher;
}
}
if (Predicate.isAtomicOrderingAcquireOrStronger()) {
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
"Acquire", AtomicOrderingMMOPredicateMatcher::AO_OrStronger);
return InsnMatcher;
}
if (Predicate.isAtomicOrderingWeakerThanAcquire()) {
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
"Acquire", AtomicOrderingMMOPredicateMatcher::AO_WeakerThan);
return InsnMatcher;
}
if (Predicate.isAtomicOrderingReleaseOrStronger()) {
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
"Release", AtomicOrderingMMOPredicateMatcher::AO_OrStronger);
return InsnMatcher;
}
if (Predicate.isAtomicOrderingWeakerThanRelease()) {
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
"Release", AtomicOrderingMMOPredicateMatcher::AO_WeakerThan);
return InsnMatcher;
}
HasAddedMatcher = false;
return InsnMatcher;
}
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
2017-12-05 05:52:07 +00:00
Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
RuleMatcher &Rule, InstructionMatcher &InsnMatcher,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &Src, unsigned &TempOpIdx) {
const auto SavedFlags = Rule.setGISelFlags(Src.getGISelFlagsRecord());
[RFC][GISel] Add a way to ignore COPY instructions in InstructionSelector RFC to add a way to ignore COPY instructions when pattern-matching MIR in GISel. - Add a new "GISelFlags" class to TableGen. Both `Pattern` and `PatFrags` defs can use it to alter matching behaviour. - Flags start at zero and are scoped: the setter returns a `SaveAndRestore` object so that when the current scope ends, the flags are restored to their previous values. This allows child patterns to modify the flags without affecting the parent pattern. - Child patterns always reuse the parent's pattern, but they can override its values. For more examples, see `GlobalISelEmitterFlags.td` tests. - [AMDGPU] Use the IgnoreCopies flag in BFI patterns, which are known to be bothered by cross-regbank copies. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D136234
2023-01-25 14:06:09 +01:00
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
const Record *SrcGIEquivOrNull = nullptr;
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
2017-12-05 05:52:07 +00:00
const CodeGenInstruction *SrcGIOrNull = nullptr;
// Start with the defined operands (i.e., the results of the root operator).
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (Src.isLeaf()) {
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const Init *SrcInit = Src.getLeafValue();
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
2017-12-05 05:52:07 +00:00
if (isa<IntInit>(SrcInit)) {
InsnMatcher.addPredicate<InstructionOpcodeMatcher>(
&Target.getInstruction(RK.getDef("G_CONSTANT")));
} else
return failedImport(
"Unable to deduce gMIR opcode to handle Src (which is a leaf)");
} else {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
SrcGIEquivOrNull = findNodeEquiv(Src.getOperator());
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
2017-12-05 05:52:07 +00:00
if (!SrcGIEquivOrNull)
return failedImport("Pattern operator lacks an equivalent Instruction" +
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
explainOperator(Src.getOperator()));
[globalisel] Update GlobalISel emitter to match new representation of extending loads Summary: Previously, a extending load was represented at (G_*EXT (G_LOAD x)). This had a few drawbacks: * G_LOAD had to be legal for all sizes you could extend from, even if registers didn't naturally hold those sizes. * All sizes you could extend from had to be allocatable just in case the extend went missing (e.g. by optimization). * At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we improve optimization of extends and truncates, this legality requirement would spread without considerable care w.r.t when certain combines were permitted. * The SelectionDAG importer required some ugly and fragile pattern rewriting to translate patterns into this style. This patch changes the representation to: * (G_[SZ]EXTLOAD x) * (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits() which resolves these issues by allowing targets to work entirely in their native register sizes, and by having a more direct translation from SelectionDAG patterns. Each extending load can be lowered by the legalizer into separate extends and loads, however a target that supports s1 will need the any-extending load to extend to at least s8 since LLVM does not represent memory accesses smaller than 8 bit. The legalizer can widenScalar G_LOAD into an any-extending load but sign/zero-extending loads need help from something else like a combiner pass. A follow-up patch that adds combiner helpers for for this will follow. The new representation requires that the MMO correctly reflect the memory access so this has been corrected in a couple tests. I've also moved the extending loads to their own tests since they are (mostly) separate opcodes now. Additionally, the re-write appears to have invalidated two tests from select-with-no-legality-check.mir since the matcher table no longer contains loads that result in s1's and they aren't legal in AArch64 anymore. Depends on D45540 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar Reviewed By: rtereshin Subscribers: javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45541 llvm-svn: 331601
2018-05-05 20:53:24 +00:00
SrcGIOrNull = getEquivNode(*SrcGIEquivOrNull, Src);
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
2017-12-05 05:52:07 +00:00
// The operators look good: match the opcode
InsnMatcher.addPredicate<InstructionOpcodeMatcher>(SrcGIOrNull);
}
unsigned OpIdx = 0;
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
for (const TypeSetByHwMode &VTy : Src.getExtTypes()) {
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
2017-12-05 05:52:07 +00:00
// Results don't have a name unless they are the root node. The caller will
// set the name if appropriate.
[AMDGPU][GISel] Enable Selection of ADD3 for G_PTR_ADD Allows things like `(G_PTR_ADD (G_PTR_ADD a, b), c)` to be simplified into a single ADD3 instruction instead of two adds. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D131254
2022-08-24 12:13:04 +00:00
const bool OperandIsAPointer =
SrcGIOrNull && SrcGIOrNull->isOutOperandAPointer(OpIdx);
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
2017-12-05 05:52:07 +00:00
OperandMatcher &OM = InsnMatcher.addOperand(OpIdx++, "", TempOpIdx);
[AMDGPU][GISel] Enable Selection of ADD3 for G_PTR_ADD Allows things like `(G_PTR_ADD (G_PTR_ADD a, b), c)` to be simplified into a single ADD3 instruction instead of two adds. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D131254
2022-08-24 12:13:04 +00:00
if (auto Error = OM.addTypeCheckPredicate(VTy, OperandIsAPointer))
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
2017-12-05 05:52:07 +00:00
return failedImport(toString(std::move(Error)) +
" for result of Src pattern operator");
}
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
for (const TreePredicateCall &Call : Src.getPredicateCalls()) {
TableGen/ISel: Allow PatFrag predicate code to access captured operands Summary: This simplifies writing predicates for pattern fragments that are automatically re-associated or commuted. For example, a followup patch adds patterns for fragments of the form (add (shl $x, $y), $z) to the AMDGPU backend. Such patterns are automatically commuted to (add $z, (shl $x, $y)), which makes it basically impossible to refer to $x, $y, and $z generically in the PredicateCode. With this change, the PredicateCode can refer to $x, $y, and $z simply as `Operands[i]`. Test confirmed that there are no changes to any of the generated files when building all (non-experimental) targets. Change-Id: I61c00ace7eed42c1d4edc4c5351174b56b77a79c Reviewers: arsenm, rampitec, RKSimon, craig.topper, hfinkel, uweigand Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D51994 llvm-svn: 347992
2018-11-30 14:15:13 +00:00
const TreePredicateFn &Predicate = Call.Fn;
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
bool HasAddedBuiltinMatcher = true;
Re-commit: [globalisel][tablegen] Add support for ImmLeaf without SDNodeXForm Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 The previous commit was reverted for breaking the build but this appears to have been the recurring problem on the Windows bots with tablegen not being re-run when llvm-tblgen is changed but the .td's aren't. If it re-occurs then forcing a build with clean=True should fix it but this string should do this in advance: Requires a clean build. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311645
2017-08-24 09:11:20 +00:00
if (Predicate.isAlwaysTrue())
continue;
if (Predicate.isImmediatePattern()) {
InsnMatcher.addPredicate<InstructionImmPredicateMatcher>(Predicate);
continue;
}
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
auto InsnMatcherOrError = addBuiltinPredicates(
SrcGIEquivOrNull, Predicate, InsnMatcher, HasAddedBuiltinMatcher);
if (auto Error = InsnMatcherOrError.takeError())
return std::move(Error);
[globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). llvm-svn: 316360
2017-10-23 18:19:24 +00:00
[GlobalISel][SelectionDAG] Implement the HasNoUse builtin predicate This change introduces the HasNoUse builtin predicate in PatFrags that checks for the absence of use of the first result operand. GlobalISelEmitter will allow source PatFrags with this predicate to be matched with destination instructions with empty outs. This predicate is required for selecting the no-return variant of atomic instructions in AMDGPU. Differential Revision: https://reviews.llvm.org/D125212
2022-05-08 21:24:52 +05:30
// FIXME: This should be part of addBuiltinPredicates(). If we add this at
// the start of addBuiltinPredicates() without returning, then there might
// be cases where we hit the last return before which the
// HasAddedBuiltinMatcher will be set to false. The predicate could be
// missed if we add it in the middle or at the end due to return statements
// after the addPredicate<>() calls.
if (Predicate.hasNoUse()) {
InsnMatcher.addPredicate<NoUsePredicateMatcher>();
HasAddedBuiltinMatcher = true;
}
[TableGen] HasOneUse builtin predicate on PatFrags (#91578) This predicate tells GlobalISelEmitter and DAGISelEmitter to check that the instruction to emit has only one use of its result. This can be used on a PatFrag instead of defining custom predicates for both emitters per record that requires it.
2024-05-20 06:18:49 -08:00
if (Predicate.hasOneUse()) {
InsnMatcher.addPredicate<OneUsePredicateMatcher>();
HasAddedBuiltinMatcher = true;
}
[GlobalISel][SelectionDAG] Implement the HasNoUse builtin predicate This change introduces the HasNoUse builtin predicate in PatFrags that checks for the absence of use of the first result operand. GlobalISelEmitter will allow source PatFrags with this predicate to be matched with destination instructions with empty outs. This predicate is required for selecting the no-return variant of atomic instructions in AMDGPU. Differential Revision: https://reviews.llvm.org/D125212
2022-05-08 21:24:52 +05:30
[globalisel][tablegen] Add support for C++ predicates on PatFrags and use it to support BFC on ARM. So far, we've only handled special cases of PatFrag like ImmLeaf. This patch adds support for the remaining cases using similar mechanisms. Like most C++ code from SelectionDAG, GISel and DAGISel expect to operate on different types and representations and as such the code is not compatible between the two. It's therefore necessary to add an alternative implementation in the GISelPredicateCode field. The target test for this feature could easily be done with IntImmLeaf and this would save on a little boilerplate. The reason I've chosen to implement this using PatFrag.GISelPredicateCode and not IntImmLeaf is because I was unable to find a rule that was blocked solely by lack of support for PatFrag predicates. I found that the ones I investigated as being likely candidates for the test were further blocked by other things. llvm-svn: 334871
2018-06-15 23:13:43 +00:00
if (Predicate.hasGISelPredicateCode()) {
AMDGPU/GlobalISel/Emitter Support for predicate code that uses operands Predicates with 'let PredicateCodeUsesOperands = 1' want to examine matched operands. When we encounter predicate code that uses operands, analyze its named operand arguments and create a map between argument index and name. Later, when leaf node with name is encountered, emit GIM_RecordNamedOperand that will store that operand at its argument index in operand list. This operand list will be an argument to c++ code of the predicate. Differential Revision: https://reviews.llvm.org/D87285
2020-09-14 10:39:25 +02:00
if (Predicate.usesOperands()) {
assert(WaitingForNamedOperands == 0 &&
"previous predicate didn't find all operands or "
"nested predicate that uses operands");
TreePattern *TP = Predicate.getOrigPatFragRecord();
WaitingForNamedOperands = TP->getNumArgs();
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
for (unsigned I = 0; I < WaitingForNamedOperands; ++I)
StoreIdxForName[getScopedName(Call.Scope, TP->getArgName(I))] = I;
AMDGPU/GlobalISel/Emitter Support for predicate code that uses operands Predicates with 'let PredicateCodeUsesOperands = 1' want to examine matched operands. When we encounter predicate code that uses operands, analyze its named operand arguments and create a map between argument index and name. Later, when leaf node with name is encountered, emit GIM_RecordNamedOperand that will store that operand at its argument index in operand list. This operand list will be an argument to c++ code of the predicate. Differential Revision: https://reviews.llvm.org/D87285
2020-09-14 10:39:25 +02:00
}
[globalisel][tablegen] Add support for C++ predicates on PatFrags and use it to support BFC on ARM. So far, we've only handled special cases of PatFrag like ImmLeaf. This patch adds support for the remaining cases using similar mechanisms. Like most C++ code from SelectionDAG, GISel and DAGISel expect to operate on different types and representations and as such the code is not compatible between the two. It's therefore necessary to add an alternative implementation in the GISelPredicateCode field. The target test for this feature could easily be done with IntImmLeaf and this would save on a little boilerplate. The reason I've chosen to implement this using PatFrag.GISelPredicateCode and not IntImmLeaf is because I was unable to find a rule that was blocked solely by lack of support for PatFrag predicates. I found that the ones I investigated as being likely candidates for the test were further blocked by other things. llvm-svn: 334871
2018-06-15 23:13:43 +00:00
InsnMatcher.addPredicate<GenericInstructionPredicateMatcher>(Predicate);
continue;
}
[GlobalISel] Don't skip adding predicate matcher This patch fixes a bug which skipped adding predicate matcher for a pattern in many cases. For example, if predicate is Load and its memoryVT is non-null then the loop continues and never reaches to the end which adds the predicate matcher. This patch moves the matcher addition to the top of the loop so that it gets added regardless of contextual checks later in the loop. Other way to fix this issue is to remove all "continue" statements in checks and let the loop continue till end. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D83034
2020-07-02 09:08:06 +00:00
if (!HasAddedBuiltinMatcher) {
return failedImport("Src pattern child has predicate (" +
explainPredicates(Src) + ")");
}
Re-commit: [globalisel][tablegen] Add support for ImmLeaf without SDNodeXForm Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 The previous commit was reverted for breaking the build but this appears to have been the recurring problem on the Windows bots with tablegen not being re-run when llvm-tblgen is changed but the .td's aren't. If it re-occurs then forcing a build with clean=True should fix it but this string should do this in advance: Requires a clean build. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311645
2017-08-24 09:11:20 +00:00
}
TableGen/GlobalISel: Hack the operand order for atomic_store ISD::ATOMIC_STORE arbitrarily has the operands in the opposite order from regular ISD::STORE, which always introduced an annoying duplication of patterns to handle both cases. Since in GlobalISel there's just the one G_STORE, we need to swap the operands to correctly emit the type check for the pointer operand. Some work started in 20aafa31569b5157e792daa8860d71dd0df8a53a to migrate SelectionDAG to use ISD::STORE for atomics, but that work seems to have stalled. Since this is the pretty much the last operation which matters which isn't supported for AMDGPU, use this compatibility hack to unblock declaring it functionally complete. Not sure what's going on with the pending_phis AArch64 test. It seems it didn't always use atomics, and I'm not sure what it was originally testing matters anymore.
2020-08-02 17:23:52 -04:00
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
if (SrcGIEquivOrNull &&
SrcGIEquivOrNull->getValueAsBit("CheckMMOIsNonAtomic"))
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. Some concerns were raised with the direction. Revert while we discuss it and look into an alternative llvm-svn: 319739
2017-12-05 05:52:07 +00:00
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>("NotAtomic");
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
else if (SrcGIEquivOrNull &&
SrcGIEquivOrNull->getValueAsBit("CheckMMOIsAtomic")) {
AMDGPU/GlobalISel: Select atomic loads A new check for an explicitly atomic MMO is needed to avoid incorrectly matching pattern for non-atomic loads llvm-svn: 371418
2019-09-09 16:18:07 +00:00
InsnMatcher.addPredicate<AtomicOrderingMMOPredicateMatcher>(
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
"Unordered", AtomicOrderingMMOPredicateMatcher::AO_OrStronger);
AMDGPU/GlobalISel: Select atomic loads A new check for an explicitly atomic MMO is needed to avoid incorrectly matching pattern for non-atomic loads llvm-svn: 371418
2019-09-09 16:18:07 +00:00
}
Re-commit: [globalisel][tablegen] Add support for ImmLeaf without SDNodeXForm Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 The previous commit was reverted for breaking the build but this appears to have been the recurring problem on the Windows bots with tablegen not being re-run when llvm-tblgen is changed but the .td's aren't. If it re-occurs then forcing a build with clean=True should fix it but this string should do this in advance: Requires a clean build. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311645
2017-08-24 09:11:20 +00:00
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (Src.isLeaf()) {
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const Init *SrcInit = Src.getLeafValue();
if (const IntInit *SrcIntInit = dyn_cast<IntInit>(SrcInit)) {
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
OperandMatcher &OM =
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
InsnMatcher.addOperand(OpIdx++, Src.getName(), TempOpIdx);
[globalisel][tablegen] Add support for (set $dst, 1) and test X86's OptForSize predicate. Summary: It's rare but a small number of patterns use IntInit's at the root of the match. On X86, one such rule is enabled by the OptForSize predicate and causes the compiler to use the smaller: %0 = MOV32r1 instead of the usual: %0 = MOV32ri 1 This patch adds support for matching IntInit's at the root and uses this as a test case for the optsize attribute that was implemented in r301750 Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: qcolombet Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32791 llvm-svn: 303678
2017-05-23 19:33:16 +00:00
OM.addPredicate<LiteralIntOperandMatcher>(SrcIntInit->getValue());
} else
[globalisel][tablegen] Multiple 80-col corrections. llvm-svn: 306544
2017-06-28 13:50:04 +00:00
return failedImport(
"Unable to deduce gMIR opcode to handle Src (which is a leaf)");
[globalisel][tablegen] Add support for (set $dst, 1) and test X86's OptForSize predicate. Summary: It's rare but a small number of patterns use IntInit's at the root of the match. On X86, one such rule is enabled by the OptForSize predicate and causes the compiler to use the smaller: %0 = MOV32r1 instead of the usual: %0 = MOV32ri 1 This patch adds support for matching IntInit's at the root and uses this as a test case for the optsize attribute that was implemented in r301750 Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: qcolombet Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32791 llvm-svn: 303678
2017-05-23 19:33:16 +00:00
} else {
[globalisel][tablegen] Import rules containing intrinsic_wo_chain. Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 llvm-svn: 307240
2017-07-06 08:12:20 +00:00
assert(SrcGIOrNull &&
"Expected to have already found an equivalent Instruction");
[globalisel][tablegen] Add support for fpimm and import of APInt/APFloat based ImmLeaf. Summary: There's only a tablegen testcase for IntImmLeaf and not a CodeGen one because the relevant rules are rejected for other reasons at the moment. On AArch64, it's because there's an SDNodeXForm attached to the operand. On X86, it's because the rule either emits multiple instructions or has another predicate using PatFrag which cannot easily be supported at the same time. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36569 llvm-svn: 315761
2017-10-13 21:28:03 +00:00
if (SrcGIOrNull->TheDef->getName() == "G_CONSTANT" ||
SrcGIOrNull->TheDef->getName() == "G_FCONSTANT") {
// imm/fpimm still have operands but we don't need to do anything with it
[globalisel][tablegen] Add support for importing 'imm' operands. Summary: This patch enables the import of rules containing 'imm' operands that do not constrain the acceptable values using predicates. Support for ImmLeaf will arrive in a later patch. Depends on D35681 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35833 llvm-svn: 310343
2017-08-08 10:44:31 +00:00
// here since we don't support ImmLeaf predicates yet. However, we still
// need to note the hidden operand to get GIM_CheckNumOperands correct.
InsnMatcher.addOperand(OpIdx++, "", TempOpIdx);
return InsnMatcher;
}
[TableGen][GISel] Handle frameindex/tframeindex (#90475) Support patterns like Pat<(p0 frameindex:$fi), (ADD tframeindex:$fi, 0)>; in the GlobalISel emitter in TableGen. Currently, using such a pattern results in an error message.
2024-04-29 12:06:26 -04:00
if (SrcGIOrNull->TheDef->getName() == "G_FRAME_INDEX") {
InsnMatcher.addOperand(OpIdx++, Src.getName(), TempOpIdx);
return InsnMatcher;
}
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 01:13:41 +00:00
// Special case because the operand order is changed from setcc. The
// predicate operand needs to be swapped from the last operand to the first
// source.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
unsigned NumChildren = Src.getNumChildren();
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 01:13:41 +00:00
bool IsFCmp = SrcGIOrNull->TheDef->getName() == "G_FCMP";
if (IsFCmp || SrcGIOrNull->TheDef->getName() == "G_ICMP") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &SrcChild = Src.getChild(NumChildren - 1);
if (SrcChild.isLeaf()) {
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const DefInit *DI = dyn_cast<DefInit>(SrcChild.getLeafValue());
const Record *CCDef = DI ? DI->getDef() : nullptr;
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 01:13:41 +00:00
if (!CCDef || !CCDef->isSubClassOf("CondCode"))
return failedImport("Unable to handle CondCode");
OperandMatcher &OM =
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
InsnMatcher.addOperand(OpIdx++, SrcChild.getName(), TempOpIdx);
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
StringRef PredType = IsFCmp ? CCDef->getValueAsString("FCmpPredicate")
: CCDef->getValueAsString("ICmpPredicate");
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 01:13:41 +00:00
if (!PredType.empty()) {
Make llvm::StringRef to std::string conversions explicit. This is how it should've been and brings it more in line with std::string_view. There should be no functional change here. This is mostly mechanical from a custom clang-tidy check, with a lot of manual fixups. It uncovers a lot of minor inefficiencies. This doesn't actually modify StringRef yet, I'll do that in a follow-up.
2020-01-28 20:23:46 +01:00
OM.addPredicate<CmpPredicateOperandMatcher>(std::string(PredType));
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 01:13:41 +00:00
// Process the other 2 operands normally.
--NumChildren;
}
}
}
[globalisel][tablegen] Add support for (set $dst, 1) and test X86's OptForSize predicate. Summary: It's rare but a small number of patterns use IntInit's at the root of the match. On X86, one such rule is enabled by the OptForSize predicate and causes the compiler to use the smaller: %0 = MOV32r1 instead of the usual: %0 = MOV32ri 1 This patch adds support for matching IntInit's at the root and uses this as a test case for the optsize attribute that was implemented in r301750 Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: qcolombet Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32791 llvm-svn: 303678
2017-05-23 19:33:16 +00:00
// Match the used operands (i.e. the children of the operator).
Teach GlobalISelEmitter to treat used iPTRAny operands as pointer operands Overloaded intrinsics can use iPTRAny in used/input operands. The GlobalISelEmitter doesn't know that these are pointers, so it treats them as scalars. As a result, these intrinsics can't be imported. This teaches the GlobalISelEmitter to recognize these as pointers rather than scalars. Differential Revision: https://reviews.llvm.org/D65756 llvm-svn: 369455
2019-08-20 22:04:10 +00:00
bool IsIntrinsic =
SrcGIOrNull->TheDef->getName() == "G_INTRINSIC" ||
[GlobalISel] convergent intrinsics Introduced the convergent equivalent of the existing G_INTRINSIC opcodes: - G_INTRINSIC_CONVERGENT - G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS Out of the targets that currently have some support for GlobalISel, the patch assumes that the convergent intrinsics only relevant to SPIRV and AMDGPU. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D154766
2023-07-31 12:14:34 +05:30
SrcGIOrNull->TheDef->getName() == "G_INTRINSIC_W_SIDE_EFFECTS" ||
SrcGIOrNull->TheDef->getName() == "G_INTRINSIC_CONVERGENT" ||
SrcGIOrNull->TheDef->getName() ==
"G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS";
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const CodeGenIntrinsic *II = Src.getIntrinsicInfo(CGP);
Teach GlobalISelEmitter to treat used iPTRAny operands as pointer operands Overloaded intrinsics can use iPTRAny in used/input operands. The GlobalISelEmitter doesn't know that these are pointers, so it treats them as scalars. As a result, these intrinsics can't be imported. This teaches the GlobalISelEmitter to recognize these as pointers rather than scalars. Differential Revision: https://reviews.llvm.org/D65756 llvm-svn: 369455
2019-08-20 22:04:10 +00:00
if (IsIntrinsic && !II)
return failedImport("Expected IntInit containing intrinsic ID)");
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
for (unsigned I = 0; I != NumChildren; ++I) {
const TreePatternNode &SrcChild = Src.getChild(I);
[globalisel][tablegen] Import rules containing intrinsic_wo_chain. Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 llvm-svn: 307240
2017-07-06 08:12:20 +00:00
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
// We need to determine the meaning of a literal integer based on the
// context. If this is a field required to be an immediate (such as an
// immarg intrinsic argument), the required predicates are different than
// a constant which may be materialized in a register. If we have an
// argument that is required to be an immediate, we should not emit an LLT
// type check, and should not be looking for a G_CONSTANT defined
// register.
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
bool OperandIsImmArg = SrcGIOrNull->isInOperandImmArg(I);
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
[globalisel][tablegen] Implement unindexed load, non-extending load, and MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 llvm-svn: 315884
2017-10-16 00:56:30 +00:00
// SelectionDAG allows pointers to be represented with iN since it doesn't
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
// distinguish between pointers and integers but they are different types
// in GlobalISel. Coerce integers to pointers to address space 0 if the
// context indicates a pointer.
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
//
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
bool OperandIsAPointer = SrcGIOrNull->isInOperandAPointer(I);
[globalisel][tablegen] Implement unindexed load, non-extending load, and MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 llvm-svn: 315884
2017-10-16 00:56:30 +00:00
Teach GlobalISelEmitter to treat used iPTRAny operands as pointer operands Overloaded intrinsics can use iPTRAny in used/input operands. The GlobalISelEmitter doesn't know that these are pointers, so it treats them as scalars. As a result, these intrinsics can't be imported. This teaches the GlobalISelEmitter to recognize these as pointers rather than scalars. Differential Revision: https://reviews.llvm.org/D65756 llvm-svn: 369455
2019-08-20 22:04:10 +00:00
if (IsIntrinsic) {
// For G_INTRINSIC/G_INTRINSIC_W_SIDE_EFFECTS, the operand immediately
// following the defs is an intrinsic ID.
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
if (I == 0) {
[globalisel][tablegen] Import rules containing intrinsic_wo_chain. Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 llvm-svn: 307240
2017-07-06 08:12:20 +00:00
OperandMatcher &OM =
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
InsnMatcher.addOperand(OpIdx++, SrcChild.getName(), TempOpIdx);
[globalisel][tablegen] Correct matching of intrinsic ID's. TreePatternNode considers them to be plain integers but MachineInstr considers them to be a distinct kind of operand. The tweak to AArch64InstrInfo.td to produce a simple test case is a NFC for everything except GlobalISelEmitter (confirmed by diffing the tablegenerated files). GlobalISelEmitter is currently unable to infer the type of operands in the Dst pattern from the operands in the Src pattern. llvm-svn: 307634
2017-07-11 08:57:29 +00:00
OM.addPredicate<IntrinsicIDOperandMatcher>(II);
[globalisel][tablegen] Import rules containing intrinsic_wo_chain. Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 llvm-svn: 307240
2017-07-06 08:12:20 +00:00
continue;
}
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
// We have to check intrinsics for llvm_anyptr_ty and immarg parameters.
Teach GlobalISelEmitter to treat used iPTRAny operands as pointer operands Overloaded intrinsics can use iPTRAny in used/input operands. The GlobalISelEmitter doesn't know that these are pointers, so it treats them as scalars. As a result, these intrinsics can't be imported. This teaches the GlobalISelEmitter to recognize these as pointers rather than scalars. Differential Revision: https://reviews.llvm.org/D65756 llvm-svn: 369455
2019-08-20 22:04:10 +00:00
//
// Note that we have to look at the i-1th parameter, because we don't
// have the intrinsic ID in the intrinsic's parameter list.
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
OperandIsAPointer |= II->isParamAPointer(I - 1);
OperandIsImmArg |= II->isParamImmArg(I - 1);
[globalisel][tablegen] Import rules containing intrinsic_wo_chain. Summary: As of this patch, 1018 out of 3938 rules are currently imported. Depends on D32275 Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar Reviewed By: qcolombet Subscribers: dberris, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32278 llvm-svn: 307240
2017-07-06 08:12:20 +00:00
}
[globalisel][tablegen] Implement unindexed load, non-extending load, and MemVT checks Summary: This includes some context-sensitivity in the MVT to LLT conversion so that pointer types are tested correctly. FIXME: I'm not happy with the way this is done since everything is a special-case. I've yet to find a reasonable way to implement it. select-load.mir fails because <1 x s64> loads in tablegen get priority over s64 loads. This is fixed in the next patch and as such they should be committed together, I've posted them separately to help with the review. Depends on D37456 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: kristof.beyls, javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37457 llvm-svn: 315884
2017-10-16 00:56:30 +00:00
if (auto Error =
importChildMatcher(Rule, InsnMatcher, SrcChild, OperandIsAPointer,
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
OperandIsImmArg, OpIdx++, TempOpIdx))
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
[globalisel][tablegen] Add support for (set $dst, 1) and test X86's OptForSize predicate. Summary: It's rare but a small number of patterns use IntInit's at the root of the match. On X86, one such rule is enabled by the OptForSize predicate and causes the compiler to use the smaller: %0 = MOV32r1 instead of the usual: %0 = MOV32ri 1 This patch adds support for matching IntInit's at the root and uses this as a test case for the optsize attribute that was implemented in r301750 Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: qcolombet Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32791 llvm-svn: 303678
2017-05-23 19:33:16 +00:00
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
return InsnMatcher;
}
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
Error GlobalISelEmitter::importComplexPatternOperandMatcher(
[TableGen] Change CodeGenInstruction record members to const (#107921) Change CodeGenInstruction::{TheDef, InfereredFrom} to const pointers. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-11 08:52:26 -07:00
OperandMatcher &OM, const Record *R, unsigned &TempOpIdx) const {
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
const auto &ComplexPattern = ComplexPatternEquivs.find(R);
if (ComplexPattern == ComplexPatternEquivs.end())
return failedImport("SelectionDAG ComplexPattern (" + R->getName() +
") not mapped to GlobalISel");
OM.addPredicate<ComplexPatternOperandMatcher>(OM, *ComplexPattern->second);
TempOpIdx++;
return Error::success();
}
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
// Get the name to use for a pattern operand. For an anonymous physical register
// input, this should use the register name.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
static StringRef getSrcChildName(const TreePatternNode &SrcChild,
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
const Record *&PhysReg) {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
StringRef SrcChildName = SrcChild.getName();
if (SrcChildName.empty() && SrcChild.isLeaf()) {
if (auto *ChildDefInit = dyn_cast<DefInit>(SrcChild.getLeafValue())) {
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
auto *ChildRec = ChildDefInit->getDef();
if (ChildRec->isSubClassOf("Register")) {
SrcChildName = ChildRec->getName();
PhysReg = ChildRec;
}
}
}
return SrcChildName;
}
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
Error GlobalISelEmitter::importChildMatcher(
RuleMatcher &Rule, InstructionMatcher &InsnMatcher,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &SrcChild, bool OperandIsAPointer,
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
bool OperandIsImmArg, unsigned OpIdx, unsigned &TempOpIdx) {
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
const Record *PhysReg = nullptr;
AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks' The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is "MY_PAT:op1:op2" and the ones with same "name" represent same operand. Add 'same operand check' for this case. Differential Revision: https://reviews.llvm.org/D87351
2020-09-14 11:37:14 +02:00
std::string SrcChildName = std::string(getSrcChildName(SrcChild, PhysReg));
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (!SrcChild.isLeaf() &&
SrcChild.getOperator()->isSubClassOf("ComplexPattern")) {
AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks' The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is "MY_PAT:op1:op2" and the ones with same "name" represent same operand. Add 'same operand check' for this case. Differential Revision: https://reviews.llvm.org/D87351
2020-09-14 11:37:14 +02:00
// The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is
// "MY_PAT:op1:op2" and the ones with same "name" represent same operand.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
std::string PatternName = std::string(SrcChild.getOperator()->getName());
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
for (unsigned I = 0; I < SrcChild.getNumChildren(); ++I) {
AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks' The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is "MY_PAT:op1:op2" and the ones with same "name" represent same operand. Add 'same operand check' for this case. Differential Revision: https://reviews.llvm.org/D87351
2020-09-14 11:37:14 +02:00
PatternName += ":";
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
PatternName += SrcChild.getChild(I).getName();
AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks' The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is "MY_PAT:op1:op2" and the ones with same "name" represent same operand. Add 'same operand check' for this case. Differential Revision: https://reviews.llvm.org/D87351
2020-09-14 11:37:14 +02:00
}
SrcChildName = PatternName;
}
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
Make llvm::StringRef to std::string conversions explicit. This is how it should've been and brings it more in line with std::string_view. There should be no functional change here. This is mostly mechanical from a custom clang-tidy check, with a lot of manual fixups. It uncovers a lot of minor inefficiencies. This doesn't actually modify StringRef yet, I'll do that in a follow-up.
2020-01-28 20:23:46 +01:00
OperandMatcher &OM =
AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks' The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is "MY_PAT:op1:op2" and the ones with same "name" represent same operand. Add 'same operand check' for this case. Differential Revision: https://reviews.llvm.org/D87351
2020-09-14 11:37:14 +02:00
PhysReg ? InsnMatcher.addPhysRegInput(PhysReg, OpIdx, TempOpIdx)
: InsnMatcher.addOperand(OpIdx, SrcChildName, TempOpIdx);
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
if (OM.isSameAsAnotherOperand())
return Error::success();
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
ArrayRef<TypeSetByHwMode> ChildTypes = SrcChild.getExtTypes();
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
if (ChildTypes.size() != 1)
return failedImport("Src pattern child has multiple results");
// Check MBB's before the type check since they are not a known type.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (!SrcChild.isLeaf()) {
if (SrcChild.getOperator()->isSubClassOf("SDNode")) {
auto &ChildSDNI = CGP.getSDNodeInfo(SrcChild.getOperator());
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
if (ChildSDNI.getSDClassName() == "BasicBlockSDNode") {
OM.addPredicate<MBBOperandMatcher>();
[globalisel][tablegen] Change Expected<bool> to Error and rename functions. Functions that still return Expected<X> are now called createAndImport*() Changing the return type was requested in the review comments for r299001 llvm-svn: 299063
2017-03-30 09:36:33 +00:00
return Error::success();
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (SrcChild.getOperator()->getName() == "timm") {
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics" This reverts r372314, reapplying r372285 and the commits which depend on it (r372286-r372293, and r372296-r372297) This was missing one switch to getTargetConstant in an untested case. llvm-svn: 372338
2019-09-19 16:26:14 +00:00
OM.addPredicate<ImmOperandMatcher>();
[GISel] Teach TableGen to check predicates of immediate operands in patterns Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D91703
2021-03-29 15:21:46 +02:00
// Add predicates, if any
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
for (const TreePredicateCall &Call : SrcChild.getPredicateCalls()) {
[GISel] Teach TableGen to check predicates of immediate operands in patterns Reviewed By: dsanders Differential Revision: https://reviews.llvm.org/D91703
2021-03-29 15:21:46 +02:00
const TreePredicateFn &Predicate = Call.Fn;
// Only handle immediate patterns for now
if (Predicate.isImmediatePattern()) {
OM.addPredicate<OperandImmPredicateMatcher>(Predicate);
}
}
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics" This reverts r372314, reapplying r372285 and the commits which depend on it (r372286-r372293, and r372296-r372297) This was missing one switch to getTargetConstant in an untested case. llvm-svn: 372338
2019-09-19 16:26:14 +00:00
return Error::success();
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
[GISel][AArch64][RISCV] Allow G_SEXT_INREG patterns to be imported. (#115576) SelectionDAG uses VTSDNode to store the extension type. GlobalISel uses a literal constant operand. For vectors, SelectionDAG uses a type with the same number of elements as other operand of the sext_inreg. I assume for GISel we would just use the scalar size.
2024-11-08 22:26:56 -08:00
} else if (auto *ChildDefInit = dyn_cast<DefInit>(SrcChild.getLeafValue())) {
auto *ChildRec = ChildDefInit->getDef();
if (ChildRec->isSubClassOf("ValueType") && !SrcChild.hasName()) {
// An unnamed ValueType as in (sext_inreg GPR:$foo, i8). GISel represents
// this as a literal constant with the scalar size.
MVT::SimpleValueType VT = llvm::getValueType(ChildRec);
OM.addPredicate<LiteralIntOperandMatcher>(MVT(VT).getScalarSizeInBits());
return Error::success();
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
// Immediate arguments have no meaningful type to check as they don't have
// registers.
if (!OperandIsImmArg) {
if (auto Error =
OM.addTypeCheckPredicate(ChildTypes.front(), OperandIsAPointer))
return failedImport(toString(std::move(Error)) + " for Src operand (" +
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
to_string(SrcChild) + ")");
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
[TableGen][GISel] Fix incorrect binding of predicate operands upon `PredicateUsesOperands = 1` (#68125) When `PredicateUsesOperands` is set to true, GlobalISelEmitter preserves the original index of predicate operands and uses that information on each predicate usage. However, previously it only looked up the original index for "actual" operands (i.e. operands of a predicate usage) that are leaf nodes, which is an incorrect assumption. This patch fix it by generalizing the acceptable kinds of actual operands for predicate as well as checking the existance of bound predicate operands.
2023-10-05 08:57:15 -07:00
// Try look up SrcChild for a (named) predicate operand if there is any.
if (WaitingForNamedOperands) {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
auto &ScopedNames = SrcChild.getNamesAsPredicateArg();
[TableGen][GISel] Fix incorrect binding of predicate operands upon `PredicateUsesOperands = 1` (#68125) When `PredicateUsesOperands` is set to true, GlobalISelEmitter preserves the original index of predicate operands and uses that information on each predicate usage. However, previously it only looked up the original index for "actual" operands (i.e. operands of a predicate usage) that are leaf nodes, which is an incorrect assumption. This patch fix it by generalizing the acceptable kinds of actual operands for predicate as well as checking the existance of bound predicate operands.
2023-10-05 08:57:15 -07:00
if (!ScopedNames.empty()) {
auto PA = ScopedNames.begin();
std::string Name = getScopedName(PA->getScope(), PA->getIdentifier());
OM.addPredicate<RecordNamedOperandMatcher>(StoreIdxForName[Name], Name);
--WaitingForNamedOperands;
}
}
[tablegen][globalisel] Add support for nested instruction matching. Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
2017-04-04 13:25:23 +00:00
// Check for nested instructions.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (!SrcChild.isLeaf()) {
if (SrcChild.getOperator()->isSubClassOf("ComplexPattern")) {
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
// When a ComplexPattern is used as an operator, it should do the same
// thing as when used as a leaf. However, the children of the operator
// name the sub-operands that make up the complex operand and we must
// prepare to reference them in the renderer too.
unsigned RendererID = TempOpIdx;
if (auto Error = importComplexPatternOperandMatcher(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
OM, SrcChild.getOperator(), TempOpIdx))
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
return Error;
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
for (unsigned I = 0, E = SrcChild.getNumChildren(); I != E; ++I) {
auto &SubOperand = SrcChild.getChild(I);
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (!SubOperand.getName().empty()) {
AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks' The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is "MY_PAT:op1:op2" and the ones with same "name" represent same operand. Add 'same operand check' for this case. Differential Revision: https://reviews.llvm.org/D87351
2020-09-14 11:37:14 +02:00
if (auto Error = Rule.defineComplexSubOperand(
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
SubOperand.getName(), SrcChild.getOperator(), RendererID, I,
AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks' The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is "MY_PAT:op1:op2" and the ones with same "name" represent same operand. Add 'same operand check' for this case. Differential Revision: https://reviews.llvm.org/D87351
2020-09-14 11:37:14 +02:00
SrcChildName))
[GlobalISel] Skip patterns that define complex suboperands twice instead of dying If we run into a pattern that looks like this: add (complex $x, $y) (complex $x, $z) We should skip the pattern instead of asserting/doing something unpredictable. This makes us return an Error in that case, and adds a testcase for skipped patterns. Differential Revision: https://reviews.llvm.org/D57980 llvm-svn: 353586
2019-02-09 00:29:13 +00:00
return Error;
}
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
}
return Error::success();
}
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
auto MaybeInsnOperand = OM.addPredicate<InstructionOperandMatcher>(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
InsnMatcher.getRuleMatcher(), SrcChild.getName());
[llvm] Don't use Optional::hasValue (NFC)
2022-06-20 10:38:12 -07:00
if (!MaybeInsnOperand) {
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
// This isn't strictly true. If the user were to provide exactly the same
// matchers as the original operand then we could allow it. However, it's
// simpler to not permit the redundant specification.
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
return failedImport(
"Nested instruction cannot be the same as another operand");
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
}
[tablegen][globalisel] Add support for nested instruction matching. Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
2017-04-04 13:25:23 +00:00
// Map the node to a gMIR instruction.
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
InstructionOperandMatcher &InsnOperand = **MaybeInsnOperand;
[globalisel][tablegen] Fix an multi-insn match bug where ComplexPattern is used on multiple insns. In each rule, each use of ComplexPattern is assigned an element in the Renderers array. The matcher then collects renderer functions in this array and they are used to render instructions. This works well for a single instruction but a bug in the allocation mechanism causes the elements to be assigned on a per-instruction basis rather than a per-rule basis. So in the case of: (set GPR32:$dst, (Op complex:$src1, complex:$src2)) tablegen currently assigns elements 0 and 1 to $src1 and $src2 respectively, but for: (set GPR32:$dst, (Op complex:$src1, (Op complex:$src2))) it currently assigned both $src1 and $src2 the same element (0). This results in one complex operand being rendered twice and the other being forgotten. This patch corrects the allocation such that $src1 and $src2 are still allocated different elements in this case. llvm-svn: 307646
2017-07-11 10:40:18 +00:00
auto InsnMatcherOrError = createAndImportSelDAGMatcher(
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
Rule, InsnOperand.getInsnMatcher(), SrcChild, TempOpIdx);
[tablegen][globalisel] Add support for nested instruction matching. Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
2017-04-04 13:25:23 +00:00
if (auto Error = InsnMatcherOrError.takeError())
return Error;
return Error::success();
}
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (SrcChild.hasAnyPredicate())
[globalisel][tablegen] Skip src child predicates The GlobalISel TableGen backend didn't check for predicates on the source children. This caused it to generate code for ARM patterns such as SMLABB or similar, but without properly checking for the sext_16_node part of the operands. This in turn meant that we would select SMLABB instead of MLA for simple sequences such as s32 + s32 * s32, which is wrong (we want a MLA on the full operands, not just their bottom 16 bits). This patch forces TableGen to skip patterns with predicates on the src children, so it doesn't generate code for SMLABB and other similar ARM instructions at all anymore. AArch64 and X86 are not affected. Differential Revision: https://reviews.llvm.org/D39554 llvm-svn: 317313
2017-11-03 10:30:19 +00:00
return failedImport("Src pattern child has unsupported predicate");
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
// Check for constant immediates.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (auto *ChildInt = dyn_cast<IntInit>(SrcChild.getLeafValue())) {
TableGen/GlobalISel: Fix pattern matching of immarg literals For arguments that are not expected to be materialized with G_CONSTANT, this was emitting predicates which could never match. It was first adding a meaningless LLT check, which would always fail due to the operand not being a register. Infer the cases where a literal should check for an immediate operand, instead of a register This avoids needing to invent a special way of representing timm literal values. Also handle immediate arguments in GIM_CheckLiteralInt. The comments stated it handled isImm() and isCImm(), but that wasn't really true. This unblocks work on the selection of all of the complicated AMDGPU intrinsics in future commits.
2020-01-08 15:40:37 -05:00
if (OperandIsImmArg) {
// Checks for argument directly in operand list
OM.addPredicate<LiteralIntOperandMatcher>(ChildInt->getValue());
} else {
// Checks for materialized constant
OM.addPredicate<ConstantIntOperandMatcher>(ChildInt->getValue());
}
[globalisel][tablegen] Change Expected<bool> to Error and rename functions. Functions that still return Expected<X> are now called createAndImport*() Changing the return type was requested in the review comments for r299001 llvm-svn: 299063
2017-03-30 09:36:33 +00:00
return Error::success();
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
// Check for def's like register classes or ComplexPattern's.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (auto *ChildDefInit = dyn_cast<DefInit>(SrcChild.getLeafValue())) {
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
auto *ChildRec = ChildDefInit->getDef();
// Check for register classes.
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
if (ChildRec->isSubClassOf("RegisterClass") ||
ChildRec->isSubClassOf("RegisterOperand")) {
[globalisel][tablegen] Add support for RegisterOperand. Summary: It functions just like RegisterClass except that the class is obtained from a field. Depends on D31761. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: dberris, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D32229 llvm-svn: 301080
2017-04-22 15:53:21 +00:00
OM.addPredicate<RegisterBankOperandMatcher>(
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
Target.getRegisterClass(getInitValueAsRegClass(ChildDefInit)));
[globalisel][tablegen] Add support for RegisterOperand. Summary: It functions just like RegisterClass except that the class is obtained from a field. Depends on D31761. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: dberris, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D32229 llvm-svn: 301080
2017-04-22 15:53:21 +00:00
return Error::success();
}
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
if (ChildRec->isSubClassOf("Register")) {
// This just be emitted as a copy to the specific register.
ValueTypeByHwMode VT = ChildTypes.front().getValueTypeByHwMode();
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
const CodeGenRegisterClass *RC =
CGRegs.getMinimalPhysRegClass(ChildRec, &VT);
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
if (!RC) {
return failedImport(
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
"Could not determine physical register class of pattern source");
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
}
OM.addPredicate<RegisterBankOperandMatcher>(*RC);
return Error::success();
}
[globalisel] Add support for ValueType operands in patterns. It's rare but there are a small number of patterns like this: (set i64:$dst, (add i64:$src1, i64:$src2)) These should be equivalent to register classes except they shouldn't check for a specific register bank. This doesn't occur in AArch64/ARM/X86 but does occasionally come up in other in-tree targets such as BPF. llvm-svn: 315226
2017-10-09 18:14:53 +00:00
// Check for ValueType.
if (ChildRec->isSubClassOf("ValueType")) {
// We already added a type check as standard practice so this doesn't need
// to do anything.
return Error::success();
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
// Check for ComplexPattern's.
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
if (ChildRec->isSubClassOf("ComplexPattern"))
return importComplexPatternOperandMatcher(OM, ChildRec, TempOpIdx);
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
[globalisel][tablegen] Report more detail in some SelectionDAG import failures. NFC Reviewers: ab, t.p.northover, qcolombet, aditya_nandakumar, rovka Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31325 llvm-svn: 300186
2017-04-13 09:45:37 +00:00
if (ChildRec->isSubClassOf("ImmLeaf")) {
return failedImport(
"Src pattern child def is an unsupported tablegen class (ImmLeaf)");
}
TableGen/GlobalISel: Fix srcvalue inputs Allow using srcvalue for discarding pattern inputs.
2020-01-16 10:47:13 -05:00
// Place holder for SRCVALUE nodes. Nothing to do here.
if (ChildRec->getName() == "srcvalue")
return Error::success();
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 10:39:21 -04:00
const bool ImmAllOnesV = ChildRec->getName() == "immAllOnesV";
if (ImmAllOnesV || ChildRec->getName() == "immAllZerosV") {
auto MaybeInsnOperand = OM.addPredicate<InstructionOperandMatcher>(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
InsnMatcher.getRuleMatcher(), SrcChild.getName(), false);
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 10:39:21 -04:00
InstructionOperandMatcher &InsnOperand = **MaybeInsnOperand;
ValueTypeByHwMode VTy = ChildTypes.front().getValueTypeByHwMode();
TableGen/GlobalISel: Allow inst matcher to check multiple opcodes This is to initially handleg immAllOnesV, which should match G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be used for other patterns cases that map to multiple G_* instructions, such as G_ADD and G_PTR_ADD.
2020-08-02 14:52:20 -04:00
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
const CodeGenInstruction &BuildVector =
Target.getInstruction(RK.getDef("G_BUILD_VECTOR"));
const CodeGenInstruction &BuildVectorTrunc =
Target.getInstruction(RK.getDef("G_BUILD_VECTOR_TRUNC"));
TableGen/GlobalISel: Allow inst matcher to check multiple opcodes This is to initially handleg immAllOnesV, which should match G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be used for other patterns cases that map to multiple G_* instructions, such as G_ADD and G_PTR_ADD.
2020-08-02 14:52:20 -04:00
// Treat G_BUILD_VECTOR as the canonical opcode, and G_BUILD_VECTOR_TRUNC
// as an alternative.
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 10:39:21 -04:00
InsnOperand.getInsnMatcher().addPredicate<InstructionOpcodeMatcher>(
Move from llvm::makeArrayRef to ArrayRef deduction guides - llvm/ part Use deduction guides instead of helper functions. The only non-automatic changes have been: 1. ArrayRef(some_uint8_pointer, 0) needs to be changed into ArrayRef(some_uint8_pointer, (size_t)0) to avoid an ambiguous call with ArrayRef((uint8_t*), (uint8_t*)) 2. CVSymbol sym(makeArrayRef(symStorage)); needed to be rewritten as CVSymbol sym{ArrayRef(symStorage)}; otherwise the compiler is confused and thinks we have a (bad) function prototype. There was a few similar situation across the codebase. 3. ADL doesn't seem to work the same for deduction-guides and functions, so at some point the llvm namespace must be explicitly stated. 4. The "reference mode" of makeArrayRef(ArrayRef<T> &) that acts as no-op is not supported (a constructor cannot achieve that). Per reviewers' comment, some useless makeArrayRef have been removed in the process. This is a follow-up to https://reviews.llvm.org/D140896 that introduced the deduction guides. Differential Revision: https://reviews.llvm.org/D140955
2023-01-04 08:28:45 +01:00
ArrayRef({&BuildVector, &BuildVectorTrunc}));
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 10:39:21 -04:00
// TODO: Handle both G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC We could
// theoretically not emit any opcode check, but getOpcodeMatcher currently
// has to succeed.
OperandMatcher &OM =
InsnOperand.getInsnMatcher().addOperand(0, "", TempOpIdx);
if (auto Error =
[TableGen] Add an explicit cast to allow one TypeSetByHwMode constructor to be removed. NFC This constructor was taking a ValueTypeByMode by value to create an ArrayRef. By adding an explicit cast from ValueTypeByHwMode to TypeSetByHwMode we allow the ArrayRef to be implicitly converted from a single element.
2024-07-31 14:50:25 -07:00
OM.addTypeCheckPredicate(TypeSetByHwMode(VTy), false /* OperandIsAPointer */))
TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV These should really match either G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing mechanism for matching alternative opcodes. There is GIM_SwitchOpcode, but it seems to assume it's oly only used for matcher optimization. I could also omit any opcode check and rely on the matcher directly checking the opcode, but the table optimizer currently assumes there has to be an opcode check. Also doesn't try to handle undef elements like the DAG version.
2020-08-01 10:39:21 -04:00
return failedImport(toString(std::move(Error)) +
" for result of Src pattern operator");
InsnOperand.getInsnMatcher().addPredicate<VectorSplatImmPredicateMatcher>(
ImmAllOnesV ? VectorSplatImmPredicateMatcher::AllOnes
: VectorSplatImmPredicateMatcher::AllZeros);
return Error::success();
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
return failedImport(
"Src pattern child def is an unsupported tablegen class");
}
return failedImport("Src pattern child is an unsupported kind");
}
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderer(
action_iterator InsertPt, RuleMatcher &Rule, BuildMIAction &DstMIBuilder,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &DstChild, const TreePatternNode &Src) {
Re-commit: [globalisel][tablegen] Add support for ImmLeaf without SDNodeXForm Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 The previous commit was reverted for breaking the build but this appears to have been the recurring problem on the Windows bots with tablegen not being re-run when llvm-tblgen is changed but the .td's aren't. If it re-occurs then forcing a build with clean=True should fix it but this string should do this in advance: Requires a clean build. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311645
2017-08-24 09:11:20 +00:00
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const auto &SubOperand = Rule.getComplexSubOperand(DstChild.getName());
[llvm] Don't use Optional::hasValue (NFC)
2022-06-20 10:38:12 -07:00
if (SubOperand) {
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
DstMIBuilder.addRenderer<RenderComplexPatternOperand>(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
*std::get<0>(*SubOperand), DstChild.getName(), std::get<1>(*SubOperand),
std::get<2>(*SubOperand));
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
return InsertPt;
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
}
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (!DstChild.isLeaf()) {
if (DstChild.getOperator()->isSubClassOf("SDNodeXForm")) {
auto &Child = DstChild.getChild(0);
auto I = SDNodeXFormEquivs.find(DstChild.getOperator());
[GlobalISel][TableGen] Add support for SDNodeXForm Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
2018-01-16 18:44:05 +00:00
if (I != SDNodeXFormEquivs.end()) {
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
const Record *XFormOpc =
DstChild.getOperator()->getValueAsDef("Opcode");
TableGen/GlobalISel: Add way for SDNodeXForm to work on timm The current implementation assumes there is an instruction associated with the transform, but this is not the case for timm/TargetConstant/immarg values. These transforms should directly operate on a specific MachineOperand in the source instruction. TableGen would assert if you attempted to define an equivalent GISDNodeXFormEquiv using timm when it failed to find the instruction matcher. Specially recognize SDNodeXForms on timm, and pass the operand index to the render function. Ideally this would be a separate render function type that looks like void renderFoo(MachineInstrBuilder, const MachineOperand&), but this proved to be somewhat mechanically painful. Add an optional operand index which will only be passed if the transform should only look at the one source operand. Theoretically it would also be possible to only ever pass the MachineOperand, and the existing renderers would check the parent. I think that would be somewhat ugly for the standard usage which may want to inspect other operands, and I also think MachineOperand should eventually not carry a pointer to the parent instruction. Use it in one sample pattern. This isn't a great example, since the transform exists to satisfy DAG type constraints. This could also be avoided by just changing the MachineInstr's arbitrary choice of operand type from i16 to i32. Other patterns have nontrivial uses, but this serves as the simplest example. One flaw this still has is if you try to use an SDNodeXForm defined for imm, but the source pattern uses timm, you still see the "Failed to lookup instruction" assert. However, there is now a way to avoid it.
2020-01-08 12:53:15 -05:00
if (XFormOpc->getName() == "timm") {
// If this is a TargetConstant, there won't be a corresponding
// instruction to transform. Instead, this will refer directly to an
// operand in an instruction's operand list.
DstMIBuilder.addRenderer<CustomOperandRenderer>(*I->second,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
Child.getName());
TableGen/GlobalISel: Add way for SDNodeXForm to work on timm The current implementation assumes there is an instruction associated with the transform, but this is not the case for timm/TargetConstant/immarg values. These transforms should directly operate on a specific MachineOperand in the source instruction. TableGen would assert if you attempted to define an equivalent GISDNodeXFormEquiv using timm when it failed to find the instruction matcher. Specially recognize SDNodeXForms on timm, and pass the operand index to the render function. Ideally this would be a separate render function type that looks like void renderFoo(MachineInstrBuilder, const MachineOperand&), but this proved to be somewhat mechanically painful. Add an optional operand index which will only be passed if the transform should only look at the one source operand. Theoretically it would also be possible to only ever pass the MachineOperand, and the existing renderers would check the parent. I think that would be somewhat ugly for the standard usage which may want to inspect other operands, and I also think MachineOperand should eventually not carry a pointer to the parent instruction. Use it in one sample pattern. This isn't a great example, since the transform exists to satisfy DAG type constraints. This could also be avoided by just changing the MachineInstr's arbitrary choice of operand type from i16 to i32. Other patterns have nontrivial uses, but this serves as the simplest example. One flaw this still has is if you try to use an SDNodeXForm defined for imm, but the source pattern uses timm, you still see the "Failed to lookup instruction" assert. However, there is now a way to avoid it.
2020-01-08 12:53:15 -05:00
} else {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
DstMIBuilder.addRenderer<CustomRenderer>(*I->second, Child.getName());
TableGen/GlobalISel: Add way for SDNodeXForm to work on timm The current implementation assumes there is an instruction associated with the transform, but this is not the case for timm/TargetConstant/immarg values. These transforms should directly operate on a specific MachineOperand in the source instruction. TableGen would assert if you attempted to define an equivalent GISDNodeXFormEquiv using timm when it failed to find the instruction matcher. Specially recognize SDNodeXForms on timm, and pass the operand index to the render function. Ideally this would be a separate render function type that looks like void renderFoo(MachineInstrBuilder, const MachineOperand&), but this proved to be somewhat mechanically painful. Add an optional operand index which will only be passed if the transform should only look at the one source operand. Theoretically it would also be possible to only ever pass the MachineOperand, and the existing renderers would check the parent. I think that would be somewhat ugly for the standard usage which may want to inspect other operands, and I also think MachineOperand should eventually not carry a pointer to the parent instruction. Use it in one sample pattern. This isn't a great example, since the transform exists to satisfy DAG type constraints. This could also be avoided by just changing the MachineInstr's arbitrary choice of operand type from i16 to i32. Other patterns have nontrivial uses, but this serves as the simplest example. One flaw this still has is if you try to use an SDNodeXForm defined for imm, but the source pattern uses timm, you still see the "Failed to lookup instruction" assert. However, there is now a way to avoid it.
2020-01-08 12:53:15 -05:00
}
[GlobalISel][TableGen] Add support for SDNodeXForm Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
2018-01-16 18:44:05 +00:00
return InsertPt;
}
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
return failedImport("SDNodeXForm " + Child.getName() +
[GlobalISel][TableGen] Add support for SDNodeXForm Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
2018-01-16 18:44:05 +00:00
" has no custom renderer");
}
[globalisel][tablegen] Add support for importing 'imm' operands. Summary: This patch enables the import of rules containing 'imm' operands that do not constrain the acceptable values using predicates. Support for ImmLeaf will arrive in a later patch. Depends on D35681 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35833 llvm-svn: 310343
2017-08-08 10:44:31 +00:00
// We accept 'bb' here. It's an operator because BasicBlockSDNode isn't
// inline, but in MI it's just another operand.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (DstChild.getOperator()->isSubClassOf("SDNode")) {
auto &ChildSDNI = CGP.getSDNodeInfo(DstChild.getOperator());
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
if (ChildSDNI.getSDClassName() == "BasicBlockSDNode") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
DstMIBuilder.addRenderer<CopyRenderer>(DstChild.getName());
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
return InsertPt;
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
}
}
[globalisel][tablegen] Add support for importing 'imm' operands. Summary: This patch enables the import of rules containing 'imm' operands that do not constrain the acceptable values using predicates. Support for ImmLeaf will arrive in a later patch. Depends on D35681 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35833 llvm-svn: 310343
2017-08-08 10:44:31 +00:00
// Similarly, imm is an operator in TreePatternNode's view but must be
// rendered as operands.
// FIXME: The target should be able to choose sign-extended when appropriate
// (e.g. on Mips).
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (DstChild.getOperator()->getName() == "timm") {
DstMIBuilder.addRenderer<CopyRenderer>(DstChild.getName());
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics" This reverts r372314, reapplying r372285 and the commits which depend on it (r372286-r372293, and r372296-r372297) This was missing one switch to getTargetConstant in an untested case. llvm-svn: 372338
2019-09-19 16:26:14 +00:00
return InsertPt;
[TableGen][GISel] Handle frameindex/tframeindex (#90475) Support patterns like Pat<(p0 frameindex:$fi), (ADD tframeindex:$fi, 0)>; in the GlobalISel emitter in TableGen. Currently, using such a pattern results in an error message.
2024-04-29 12:06:26 -04:00
}
if (DstChild.getOperator()->getName() == "tframeindex") {
DstMIBuilder.addRenderer<CopyRenderer>(DstChild.getName());
return InsertPt;
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
}
if (DstChild.getOperator()->getName() == "imm") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
DstMIBuilder.addRenderer<CopyConstantAsImmRenderer>(DstChild.getName());
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
return InsertPt;
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
}
if (DstChild.getOperator()->getName() == "fpimm") {
[globalisel][tablegen] Add support for fpimm and import of APInt/APFloat based ImmLeaf. Summary: There's only a tablegen testcase for IntImmLeaf and not a CodeGen one because the relevant rules are rejected for other reasons at the moment. On AArch64, it's because there's an SDNodeXForm attached to the operand. On X86, it's because the rule either emits multiple instructions or has another predicate using PatFrag which cannot easily be supported at the same time. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36569 llvm-svn: 315761
2017-10-13 21:28:03 +00:00
DstMIBuilder.addRenderer<CopyFConstantAsFPImmRenderer>(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
DstChild.getName());
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
return InsertPt;
[globalisel][tablegen] Add support for importing 'imm' operands. Summary: This patch enables the import of rules containing 'imm' operands that do not constrain the acceptable values using predicates. Support for ImmLeaf will arrive in a later patch. Depends on D35681 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35833 llvm-svn: 310343
2017-08-08 10:44:31 +00:00
}
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (DstChild.getOperator()->isSubClassOf("Instruction")) {
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130) Previously, tblgen would reject patterns where one of its nested instructions produced more than one result. These arise when the instruction definition contains 'outs' as well as 'Defs'. This patch fixes that by always taking the first result, which is how these situations are handled in SelectionIDAG. Original patch: https://reviews.llvm.org/D86617 Continued as: https://github.com/llvm/llvm-project/pull/81130
2023-11-03 12:44:38 +01:00
auto OpTy = getInstResultType(DstChild, Target);
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
if (!OpTy)
return OpTy.takeError();
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
unsigned TempRegID = Rule.allocateTempRegID();
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
InsertPt =
Rule.insertAction<MakeTempRegisterAction>(InsertPt, *OpTy, TempRegID);
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID);
auto InsertPtOrError = createAndImportSubInstructionRenderer(
[GlobalISelEmitter] handle operand without MVT/class There are some patterns in td files without MVT/class set for some operands in target pattern that are from the source pattern. This prevents GlobalISelEmitter from adding them as a valid rule, because the target child operand is an unsupported kind operand. For now, for a leaf child, only IntInit and DefInit are handled in GlobalISelEmitter. This issue can be workaround by adding MVT/class to the patterns in the td files, like the workarounds for patterns anyext and setcc in PPCInstrInfo.td in D140878. To avoid adding the same workarounds for other patterns in td files, this patch tries to handle the UnsetInit case in GlobalISelEmitter. Adding the new handling allows us to remove the workarounds in the td files and also generates many selection rules for PPC target. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D141247
2023-01-09 04:07:52 +00:00
++InsertPt, Rule, DstChild, Src, TempRegID);
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
if (auto Error = InsertPtOrError.takeError())
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
return InsertPtOrError.get();
}
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
return failedImport("Dst pattern child isn't a leaf node or an MBB" +
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
llvm::to_string(DstChild));
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
[globalisel][tablegen] Add support for specific immediates in the match pattern This enables a few rules such as ARM's uxtb instruction. llvm-svn: 319457
2017-11-30 18:48:35 +00:00
// It could be a specific immediate in which case we should just check for
// that immediate.
if (const IntInit *ChildIntInit =
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
dyn_cast<IntInit>(DstChild.getLeafValue())) {
[globalisel][tablegen] Add support for specific immediates in the match pattern This enables a few rules such as ARM's uxtb instruction. llvm-svn: 319457
2017-11-30 18:48:35 +00:00
DstMIBuilder.addRenderer<ImmRenderer>(ChildIntInit->getValue());
return InsertPt;
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
// Otherwise, we're looking for a bog-standard RegisterClass operand.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (auto *ChildDefInit = dyn_cast<DefInit>(DstChild.getLeafValue())) {
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
auto *ChildRec = ChildDefInit->getDef();
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
ArrayRef<TypeSetByHwMode> ChildTypes = DstChild.getExtTypes();
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
if (ChildTypes.size() != 1)
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
return failedImport("Dst pattern child has multiple results");
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<LLTCodeGen> OpTyOrNone;
TableGen support for parameterized register class information This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
2017-09-14 16:56:21 +00:00
if (ChildTypes.front().isMachineValueType())
OpTyOrNone = MVTToLLT(ChildTypes.front().getMachineValueType().SimpleTy);
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
if (!OpTyOrNone)
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
return failedImport("Dst operand has an unsupported type");
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
if (ChildRec->isSubClassOf("Register")) {
[TableGen][GlobalISel] Fix handling of zero_reg When generating matching tables for GlobalISel, TableGen would output "::zero_reg" whenever encountering the zero_reg, which in turn would result in compilation error. This patch fixes that by instead outputting NoRegister (== 0), which is the same result that TableGen produces when generating matching tables for ISelDAG. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D86215
2020-09-18 10:08:32 +02:00
DstMIBuilder.addRenderer<AddRegisterRenderer>(Target, ChildRec);
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
return InsertPt;
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
}
[globalisel][tablegen] Add support for RegisterOperand. Summary: It functions just like RegisterClass except that the class is obtained from a field. Depends on D31761. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: dberris, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D32229 llvm-svn: 301080
2017-04-22 15:53:21 +00:00
if (ChildRec->isSubClassOf("RegisterClass") ||
[globalisel] Add support for ValueType operands in patterns. It's rare but there are a small number of patterns like this: (set i64:$dst, (add i64:$src1, i64:$src2)) These should be equivalent to register classes except they shouldn't check for a specific register bank. This doesn't occur in AArch64/ARM/X86 but does occasionally come up in other in-tree targets such as BPF. llvm-svn: 315226
2017-10-09 18:14:53 +00:00
ChildRec->isSubClassOf("RegisterOperand") ||
ChildRec->isSubClassOf("ValueType")) {
[globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). llvm-svn: 316360
2017-10-23 18:19:24 +00:00
if (ChildRec->isSubClassOf("RegisterOperand") &&
!ChildRec->isValueUnset("GIZeroRegister")) {
DstMIBuilder.addRenderer<CopyOrAddZeroRegRenderer>(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
DstChild.getName(), ChildRec->getValueAsDef("GIZeroRegister"));
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
return InsertPt;
[globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero. This patch enables the import of stores. Unfortunately, doing so by itself, loses an optimization where storing 0 to memory makes use of WZR/XZR. To mitigate this, this patch also introduces a new feature that allows register operands to nominate a zero register. When this is done, GlobalISel will substitute (G_CONSTANT 0) with the nominated register automatically. This is currently configured to only apply to the stores. Applying it to GPR32/GPR64 register classes in general will be done after review see (https://reviews.llvm.org/D39150). llvm-svn: 316360
2017-10-23 18:19:24 +00:00
}
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
DstMIBuilder.addRenderer<CopyRenderer>(DstChild.getName());
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
return InsertPt;
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
if (ChildRec->isSubClassOf("SubRegIndex")) {
CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(ChildRec);
DstMIBuilder.addRenderer<ImmRenderer>(SubIdx->EnumValue);
return InsertPt;
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
if (ChildRec->isSubClassOf("ComplexPattern")) {
const auto &ComplexPattern = ComplexPatternEquivs.find(ChildRec);
if (ComplexPattern == ComplexPatternEquivs.end())
return failedImport(
"SelectionDAG ComplexPattern not mapped to GlobalISel");
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const OperandMatcher &OM = Rule.getOperandMatcher(DstChild.getName());
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
DstMIBuilder.addRenderer<RenderComplexPatternOperand>(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
*ComplexPattern->second, DstChild.getName(),
[globalisel][tablegen] Revise API for ComplexPattern operands to improve flexibility. Summary: Some targets need to be able to do more complex rendering than just adding an operand or two to an instruction. For example, it may need to insert an instruction to extract a subreg first, or it may need to perform an operation on the operand. In SelectionDAG, targets would create SDNode's to achieve the desired effect during the complex pattern predicate. This worked because SelectionDAG had a form of garbage collection that would take care of SDNode's that were created but not used due to a later predicate rejecting a match. This doesn't translate well to GlobalISel and the churn was wasteful. The API changes in this patch enable GlobalISel to accomplish the same thing without the waste. The API is now: InstructionSelector::OptionalComplexRendererFn selectArithImmed(MachineOperand &Root) const; where Root is the root of the match. The return value can be omitted to indicate that the predicate failed to match, or a function with the signature ComplexRendererFn can be returned. For example: return OptionalComplexRendererFn( [=](MachineInstrBuilder &MIB) { MIB.addImm(Immed).addImm(ShVal); }); adds two immediate operands to the rendered instruction. Immed and ShVal are captured from the predicate function. As an added bonus, this also reduces the amount of information we need to provide to GIComplexOperandMatcher. Depends on D31418 Reviewers: aditya_nandakumar, t.p.northover, qcolombet, rovka, ab, javed.absar Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31761 llvm-svn: 301079
2017-04-22 15:11:04 +00:00
OM.getAllocatedTemporariesBaseID());
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
return InsertPt;
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
return failedImport(
"Dst pattern child def is an unsupported tablegen class");
}
[GlobalISelEmitter] handle operand without MVT/class There are some patterns in td files without MVT/class set for some operands in target pattern that are from the source pattern. This prevents GlobalISelEmitter from adding them as a valid rule, because the target child operand is an unsupported kind operand. For now, for a leaf child, only IntInit and DefInit are handled in GlobalISelEmitter. This issue can be workaround by adding MVT/class to the patterns in the td files, like the workarounds for patterns anyext and setcc in PPCInstrInfo.td in D140878. To avoid adding the same workarounds for other patterns in td files, this patch tries to handle the UnsetInit case in GlobalISelEmitter. Adding the new handling allows us to remove the workarounds in the td files and also generates many selection rules for PPC target. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D141247
2023-01-09 04:07:52 +00:00
// Handle the case where the MVT/register class is omitted in the dest pattern
// but MVT exists in the source pattern.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (isa<UnsetInit>(DstChild.getLeafValue())) {
for (unsigned NumOp = 0; NumOp < Src.getNumChildren(); NumOp++)
if (Src.getChild(NumOp).getName() == DstChild.getName()) {
DstMIBuilder.addRenderer<CopyRenderer>(Src.getChild(NumOp).getName());
[GlobalISelEmitter] handle operand without MVT/class There are some patterns in td files without MVT/class set for some operands in target pattern that are from the source pattern. This prevents GlobalISelEmitter from adding them as a valid rule, because the target child operand is an unsupported kind operand. For now, for a leaf child, only IntInit and DefInit are handled in GlobalISelEmitter. This issue can be workaround by adding MVT/class to the patterns in the td files, like the workarounds for patterns anyext and setcc in PPCInstrInfo.td in D140878. To avoid adding the same workarounds for other patterns in td files, this patch tries to handle the UnsetInit case in GlobalISelEmitter. Adding the new handling allows us to remove the workarounds in the td files and also generates many selection rules for PPC target. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D141247
2023-01-09 04:07:52 +00:00
return InsertPt;
}
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
return failedImport("Dst pattern child is an unsupported kind");
}
[globalisel][tblgen] Add support for ComplexPatterns Summary: Adds a new kind of MachineOperand: MO_Placeholder. This operand must not appear in the MIR and only exists as a way of creating an 'uninitialized' operand until a matcher function overwrites it. Depends on D30046, D29712 Reviewers: t.p.northover, ab, rovka, aditya_nandakumar, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30089 llvm-svn: 297782
2017-03-14 21:32:08 +00:00
[globalisel][tablegen] Change Expected<bool> to Error and rename functions. Functions that still return Expected<X> are now called createAndImport*() Changing the return type was requested in the review comments for r299001 llvm-svn: 299063
2017-03-30 09:36:33 +00:00
Expected<BuildMIAction &> GlobalISelEmitter::createAndImportInstructionRenderer(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
RuleMatcher &M, InstructionMatcher &InsnMatcher, const TreePatternNode &Src,
const TreePatternNode &Dst) {
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
auto InsertPtOrError = createInstructionRenderer(M.actions_end(), M, Dst);
if (auto Error = InsertPtOrError.takeError())
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
action_iterator InsertPt = InsertPtOrError.get();
BuildMIAction &DstMIBuilder = *static_cast<BuildMIAction *>(InsertPt->get());
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
for (auto PhysInput : InsnMatcher.getPhysRegInputs()) {
InsertPt = M.insertAction<BuildMIAction>(
InsertPt, M.allocateOutputInsnID(),
&Target.getInstruction(RK.getDef("COPY")));
BuildMIAction &CopyToPhysRegMIBuilder =
*static_cast<BuildMIAction *>(InsertPt->get());
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
CopyToPhysRegMIBuilder.addRenderer<AddRegisterRenderer>(
Target, PhysInput.first, true);
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
CopyToPhysRegMIBuilder.addRenderer<CopyPhysRegRenderer>(PhysInput.first);
}
[GlobalISel] Enable patterns with multiple output operands for the GlobalISelEmitter This enables writing patterns with mutliple output operands in the input pattern for GlobalISel
2023-02-04 08:23:46 -04:00
if (auto Error =
importExplicitDefRenderers(InsertPt, M, DstMIBuilder, Src, Dst)
.takeError())
TableGen/GlobalISel: Allow output instructions with multiple defs The DAG behavior allows matchching input patterns with a single result to the first result of an output instruction that defines multiple results. The remaining defs are implicitly dead. This starts to fix using manual selection for AMDGPU add/sub (although it's still needed, mostly because it's also still needed for G_PTR_ADD).
2020-07-13 08:59:38 -04:00
return std::move(Error);
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
[GlobalISelEmitter] handle operand without MVT/class There are some patterns in td files without MVT/class set for some operands in target pattern that are from the source pattern. This prevents GlobalISelEmitter from adding them as a valid rule, because the target child operand is an unsupported kind operand. For now, for a leaf child, only IntInit and DefInit are handled in GlobalISelEmitter. This issue can be workaround by adding MVT/class to the patterns in the td files, like the workarounds for patterns anyext and setcc in PPCInstrInfo.td in D140878. To avoid adding the same workarounds for other patterns in td files, this patch tries to handle the UnsetInit case in GlobalISelEmitter. Adding the new handling allows us to remove the workarounds in the td files and also generates many selection rules for PPC target. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D141247
2023-01-09 04:07:52 +00:00
if (auto Error =
importExplicitUseRenderers(InsertPt, M, DstMIBuilder, Dst, Src)
.takeError())
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
return DstMIBuilder;
}
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
Expected<action_iterator>
GlobalISelEmitter::createAndImportSubInstructionRenderer(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const action_iterator InsertPt, RuleMatcher &M, const TreePatternNode &Dst,
const TreePatternNode &Src, unsigned TempRegID) {
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
auto InsertPtOrError = createInstructionRenderer(InsertPt, M, Dst);
// TODO: Assert there's exactly one result.
if (auto Error = InsertPtOrError.takeError())
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
BuildMIAction &DstMIBuilder =
*static_cast<BuildMIAction *>(InsertPtOrError.get()->get());
// Assign the result to TempReg.
DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID, true);
[GlobalISel][AMDGPU] Import patterns with multiple defs (#84171) Fixes #63216
2024-03-08 09:39:10 +01:00
// Handle additional (ignored) results.
if (DstMIBuilder.getCGI()->Operands.NumDefs > 1) {
InsertPtOrError = importExplicitDefRenderers(
std::prev(*InsertPtOrError), M, DstMIBuilder, Src, Dst, /*Start=*/1);
if (auto Error = InsertPtOrError.takeError())
return std::move(Error);
}
[GlobalISelEmitter] handle operand without MVT/class There are some patterns in td files without MVT/class set for some operands in target pattern that are from the source pattern. This prevents GlobalISelEmitter from adding them as a valid rule, because the target child operand is an unsupported kind operand. For now, for a leaf child, only IntInit and DefInit are handled in GlobalISelEmitter. This issue can be workaround by adding MVT/class to the patterns in the td files, like the workarounds for patterns anyext and setcc in PPCInstrInfo.td in D140878. To avoid adding the same workarounds for other patterns in td files, this patch tries to handle the UnsetInit case in GlobalISelEmitter. Adding the new handling allows us to remove the workarounds in the td files and also generates many selection rules for PPC target. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D141247
2023-01-09 04:07:52 +00:00
InsertPtOrError = importExplicitUseRenderers(InsertPtOrError.get(), M,
DstMIBuilder, Dst, Src);
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
if (auto Error = InsertPtOrError.takeError())
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
[TableGen][GISel] Extract helper function for constraining operands (#115148) As a side effect, this fixes COPY_TO_REGCLASS not being constrained if it is not top-level (the reason for changes in tests).
2024-11-07 07:16:54 +03:00
if (auto Error =
constrainOperands(InsertPt, M, DstMIBuilder.getInsnID(), Dst))
return std::move(Error);
TableGen/GlobalISel: Fix constraining REG_SEQUENCE operands This was hitting the default instruction constraint code which uses the register classes in the instruction def, which REG_SEQUENCE does not have. Fixes not constraining the register class for AMDGPU fneg/fabs patterns, which would fail when the use was another generic, unconstrained instruction. Another oddity I noticed is that the temporary registers are created with an unnecessary, but incorrect 16-bit LLT but this shouldn't matter. I'm also still unclear why root and sub-instructions have to be handled differently.
2020-04-07 09:32:51 -04:00
[globalisel][tablegen] Add support for multi-insn emission The importer will now accept nested instructions in the result pattern such as (ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction def's a single vreg and the parent instruction consumes a single vreg where a nested instruction is specified. The importer will automatically create a vreg to connect the two using the type information from the pattern. This vreg will be constrained to the register classes given in the instruction definitions*. * REG_SEQUENCE is explicitly rejected because of this. The definition doesn't constrain to a register class and it therefore needs special handling. llvm-svn: 317117
2017-11-01 19:57:57 +00:00
return InsertPtOrError.get();
}
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
Expected<action_iterator> GlobalISelEmitter::createInstructionRenderer(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
action_iterator InsertPt, RuleMatcher &M, const TreePatternNode &Dst) {
[TableGen] Change CodeGenInstruction record members to const (#107921) Change CodeGenInstruction::{TheDef, InfereredFrom} to const pointers. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-11 08:52:26 -07:00
const Record *DstOp = Dst.getOperator();
[globalisel][tablegen] Report more detail in some SelectionDAG import failures. NFC Reviewers: ab, t.p.northover, qcolombet, aditya_nandakumar, rovka Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31325 llvm-svn: 300186
2017-04-13 09:45:37 +00:00
if (!DstOp->isSubClassOf("Instruction")) {
if (DstOp->isSubClassOf("ValueType"))
return failedImport(
"Pattern operator isn't an instruction (it's a ValueType)");
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
return failedImport("Pattern operator isn't an instruction");
[globalisel][tablegen] Report more detail in some SelectionDAG import failures. NFC Reviewers: ab, t.p.northover, qcolombet, aditya_nandakumar, rovka Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31325 llvm-svn: 300186
2017-04-13 09:45:37 +00:00
}
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
CodeGenInstruction *DstI = &Target.getInstruction(DstOp);
// COPY_TO_REGCLASS is just a copy with a ConstrainOperandToRegClassAction
[globalisel][tablegen] Add support for EXTRACT_SUBREG. Summary: After this patch, we finally have test cases that require multiple instruction emission. Depends on D33590 Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D33596 llvm-svn: 306388
2017-06-27 10:11:39 +00:00
// attached. Similarly for EXTRACT_SUBREG except that's a subregister copy.
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
StringRef Name = DstI->TheDef->getName();
if (Name == "COPY_TO_REGCLASS" || Name == "EXTRACT_SUBREG")
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
DstI = &Target.getInstruction(RK.getDef("COPY"));
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
[globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFC The next commit will add support for multi-instruction emission so we need to start allocating instruction ID's instead of hard-coding them to 0. llvm-svn: 317057
2017-11-01 00:29:47 +00:00
return M.insertAction<BuildMIAction>(InsertPt, M.allocateOutputInsnID(),
DstI);
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
}
TableGen/GlobalISel: Allow output instructions with multiple defs The DAG behavior allows matchching input patterns with a single result to the first result of an output instruction that defines multiple results. The remaining defs are implicitly dead. This starts to fix using manual selection for AMDGPU add/sub (although it's still needed, mostly because it's also still needed for G_PTR_ADD).
2020-07-13 08:59:38 -04:00
Expected<action_iterator> GlobalISelEmitter::importExplicitDefRenderers(
action_iterator InsertPt, RuleMatcher &M, BuildMIAction &DstMIBuilder,
[GlobalISel][AMDGPU] Import patterns with multiple defs (#84171) Fixes #63216
2024-03-08 09:39:10 +01:00
const TreePatternNode &Src, const TreePatternNode &Dst, unsigned Start) {
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
const CodeGenInstruction *DstI = DstMIBuilder.getCGI();
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const unsigned SrcNumDefs = Src.getExtTypes().size();
[GlobalISel] Enable patterns with multiple output operands for the GlobalISelEmitter This enables writing patterns with mutliple output operands in the input pattern for GlobalISel
2023-02-04 08:23:46 -04:00
const unsigned DstNumDefs = DstI->Operands.NumDefs;
if (DstNumDefs == 0)
TableGen/GlobalISel: Allow output instructions with multiple defs The DAG behavior allows matchching input patterns with a single result to the first result of an output instruction that defines multiple results. The remaining defs are implicitly dead. This starts to fix using manual selection for AMDGPU add/sub (although it's still needed, mostly because it's also still needed for G_PTR_ADD).
2020-07-13 08:59:38 -04:00
return InsertPt;
[GlobalISel][AMDGPU] Import patterns with multiple defs (#84171) Fixes #63216
2024-03-08 09:39:10 +01:00
for (unsigned I = Start; I < SrcNumDefs; ++I) {
[GISel][TableGen] Fix accidental operand name clashes in patterns (#74492) When importing instruction selection patterns into GlobalISel, the operands matched in the "source" DAG are copied into corresponding operands of the "destination" DAG according to their names (such as Rd). If multiple operands in the source DAG share the same name, a GIM_CheckIsSameOperand predicate makes instruction selector check the corresponding operands for equality (at compiler run-time) as part of matching the source pattern. The Def operands of the root node of the destination DAG are handled specially. The operands of the instruction corresponding to the root node are taken and GIM_CheckRegBankForClass predicates are tablegen-erated accordingly. If by coincidence the Def operand in question has the same name as one of the named operands in the pattern, a GIM_CheckIsSameOperand predicate is automatically added that is likely to prevent matching the source of otherwise applicable selection pattern at compiler run-time. This patch mangles the Def operand names taken from the instruction corresponding to the root of the destination DAG (for example, "Rd" becomes "DstI[Rd]") preventing unexpected name clashes with pattern's named operands. The patch consists of three sets of changes: * changes to the GlobalISelEmitter.cpp file are the actual fix * a test case is added to GlobalISelEmitter.td file as a regression test * everything else is the biggest and least interesting part - updates to the existing test cases: renames of the form Rd -> DstI[Rd] inside the inline comments in tablegen-erated code
2023-12-10 13:25:11 +03:00
std::string OpName = getMangledRootDefName(DstI->Operands[I].Name);
// CopyRenderer saves a StringRef, so cannot pass OpName itself -
// let's use a string with an appropriate lifetime.
StringRef PermanentRef = M.getOperandMatcher(OpName).getSymbolicName();
DstMIBuilder.addRenderer<CopyRenderer>(PermanentRef);
}
TableGen/GlobalISel: Allow output instructions with multiple defs The DAG behavior allows matchching input patterns with a single result to the first result of an output instruction that defines multiple results. The remaining defs are implicitly dead. This starts to fix using manual selection for AMDGPU add/sub (although it's still needed, mostly because it's also still needed for G_PTR_ADD).
2020-07-13 08:59:38 -04:00
TableGen: Check if pattern outputs matches instruction defs Attempt to fix address sanitizer bots when building ARM.
2020-07-27 20:29:53 -04:00
// Some instructions have multiple defs, but are missing a type entry
// (e.g. s_cc_out operands).
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (Dst.getExtTypes().size() < DstNumDefs)
TableGen: Check if pattern outputs matches instruction defs Attempt to fix address sanitizer bots when building ARM.
2020-07-27 20:29:53 -04:00
return failedImport("unhandled discarded def");
[GlobalISel] Enable patterns with multiple output operands for the GlobalISelEmitter This enables writing patterns with mutliple output operands in the input pattern for GlobalISel
2023-02-04 08:23:46 -04:00
for (unsigned I = SrcNumDefs; I < DstNumDefs; ++I) {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TypeSetByHwMode &ExtTy = Dst.getExtType(I);
TableGen/GlobalISel: Allow output instructions with multiple defs The DAG behavior allows matchching input patterns with a single result to the first result of an output instruction that defines multiple results. The remaining defs are implicitly dead. This starts to fix using manual selection for AMDGPU add/sub (although it's still needed, mostly because it's also still needed for G_PTR_ADD).
2020-07-13 08:59:38 -04:00
if (!ExtTy.isMachineValueType())
return failedImport("unsupported typeset");
auto OpTy = MVTToLLT(ExtTy.getMachineValueType().SimpleTy);
if (!OpTy)
return failedImport("unsupported type");
unsigned TempRegID = M.allocateTempRegID();
InsertPt =
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
M.insertAction<MakeTempRegisterAction>(InsertPt, *OpTy, TempRegID);
TableGen/GlobalISel: Allow output instructions with multiple defs The DAG behavior allows matchching input patterns with a single result to the first result of an output instruction that defines multiple results. The remaining defs are implicitly dead. This starts to fix using manual selection for AMDGPU add/sub (although it's still needed, mostly because it's also still needed for G_PTR_ADD).
2020-07-13 08:59:38 -04:00
DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID, true, nullptr, true);
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
}
TableGen/GlobalISel: Allow output instructions with multiple defs The DAG behavior allows matchching input patterns with a single result to the first result of an output instruction that defines multiple results. The remaining defs are implicitly dead. This starts to fix using manual selection for AMDGPU add/sub (although it's still needed, mostly because it's also still needed for G_PTR_ADD).
2020-07-13 08:59:38 -04:00
return InsertPt;
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
}
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderers(
action_iterator InsertPt, RuleMatcher &M, BuildMIAction &DstMIBuilder,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const llvm::TreePatternNode &Dst, const llvm::TreePatternNode &Src) {
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
const CodeGenInstruction *DstI = DstMIBuilder.getCGI();
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
CodeGenInstruction *OrigDstI = &Target.getInstruction(Dst.getOperator());
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
StringRef Name = OrigDstI->TheDef->getName();
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
unsigned ExpectedDstINumUses = Dst.getNumChildren();
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
[globalisel][tablegen] Add support for EXTRACT_SUBREG. Summary: After this patch, we finally have test cases that require multiple instruction emission. Depends on D33590 Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D33596 llvm-svn: 306388
2017-06-27 10:11:39 +00:00
// EXTRACT_SUBREG needs to use a subregister COPY.
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
if (Name == "EXTRACT_SUBREG") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (!Dst.getChild(1).isLeaf())
[GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT Before this patch there was generic mapping from vector_extract to G_EXTRACT_VECTOR_ELT added in SelectionDAGCompat.td. That mapping is now replaced by a mapping from extractelt instead. The reasoning is that vector_extract is marked as deprecated, so it is assumed that a majority of targets will use extractelt and not vector_extract (and that the long term solution for all targets would be to use extractelt). Targets like AArch64 that still use vector_extract can add an additional mapping from the deprecated vector_extract as target specific tablegen definitions. Such a mapping is added for AArch64 in this patch to avoid breaking tests. When adding the extractelt => G_EXTRACT_VECTOR_ELT mapping we triggered some new code paths in GlobalISelEmitter, ending up in an assert when trying to import a pattern containing EXTRACT_SUBREG for ARM. Therefore this patch also adds a "failedImport" warning for that situation (instead of hitting the assert). Differential Revision: https://reviews.llvm.org/D93416
2021-01-11 16:19:01 +01:00
return failedImport("EXTRACT_SUBREG child #1 is not a leaf");
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const DefInit *SubRegInit =
dyn_cast<DefInit>(Dst.getChild(1).getLeafValue());
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
if (!SubRegInit)
return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");
CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &ValChild = Dst.getChild(0);
if (!ValChild.isLeaf()) {
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
// We really have to handle the source instruction, and then insert a
// copy from the subregister.
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130) Previously, tblgen would reject patterns where one of its nested instructions produced more than one result. These arise when the instruction definition contains 'outs' as well as 'Defs'. This patch fixes that by always taking the first result, which is how these situations are handled in SelectionIDAG. Original patch: https://reviews.llvm.org/D86617 Continued as: https://github.com/llvm/llvm-project/pull/81130
2023-11-03 12:44:38 +01:00
auto ExtractSrcTy = getInstResultType(ValChild, Target);
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
if (!ExtractSrcTy)
return ExtractSrcTy.takeError();
[globalisel][tablegen] Add support for EXTRACT_SUBREG. Summary: After this patch, we finally have test cases that require multiple instruction emission. Depends on D33590 Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D33596 llvm-svn: 306388
2017-06-27 10:11:39 +00:00
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
unsigned TempRegID = M.allocateTempRegID();
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
InsertPt = M.insertAction<MakeTempRegisterAction>(InsertPt, *ExtractSrcTy,
TempRegID);
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
auto InsertPtOrError = createAndImportSubInstructionRenderer(
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
++InsertPt, M, ValChild, Src, TempRegID);
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
if (auto Error = InsertPtOrError.takeError())
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID, false, SubIdx);
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
return InsertPt;
[globalisel][tablegen] Add support for EXTRACT_SUBREG. Summary: After this patch, we finally have test cases that require multiple instruction emission. Depends on D33590 Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D33596 llvm-svn: 306388
2017-06-27 10:11:39 +00:00
}
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
// If this is a source operand, this is just a subregister copy.
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const Record *RCDef = getInitValueAsRegClass(ValChild.getLeafValue());
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
if (!RCDef)
return failedImport("EXTRACT_SUBREG child #0 could not "
"be coerced to a register class");
CodeGenRegisterClass *RC = CGRegs.getRegClass(RCDef);
const auto SrcRCDstRCPair =
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
RC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx);
[llvm] Don't use Optional::hasValue (NFC)
2022-06-20 10:38:12 -07:00
if (SrcRCDstRCPair) {
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
if (SrcRCDstRCPair->first != RC)
return failedImport("EXTRACT_SUBREG requires an additional COPY");
}
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
StringRef RegOperandName = Dst.getChild(0).getName();
[TableGen][GlobalISel] Support EXTRACT_SUBREGs for ComplexPattern suboperands. This makes it possible to write GlobalISel patterns generating EXTRACT_SUBREG instructions applied to suboperands of ComplexPattern operands. Currently, TableGen complains that such operands are not declared in matcher. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D146800
2023-03-27 11:37:16 +01:00
if (const auto &SubOperand = M.getComplexSubOperand(RegOperandName)) {
DstMIBuilder.addRenderer<RenderComplexPatternOperand>(
*std::get<0>(*SubOperand), RegOperandName, std::get<1>(*SubOperand),
std::get<2>(*SubOperand), SubIdx);
return InsertPt;
}
DstMIBuilder.addRenderer<CopySubRegRenderer>(RegOperandName, SubIdx);
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
return InsertPt;
[globalisel][tablegen] Add support for EXTRACT_SUBREG. Summary: After this patch, we finally have test cases that require multiple instruction emission. Depends on D33590 Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D33596 llvm-svn: 306388
2017-06-27 10:11:39 +00:00
}
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
if (Name == "REG_SEQUENCE") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (!Dst.getChild(0).isLeaf())
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
return failedImport("REG_SEQUENCE child #0 is not a leaf");
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const Record *RCDef =
getInitValueAsRegClass(Dst.getChild(0).getLeafValue());
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
if (!RCDef)
return failedImport("REG_SEQUENCE child #0 could not "
"be coerced to a register class");
if ((ExpectedDstINumUses - 1) % 2 != 0)
return failedImport("Malformed REG_SEQUENCE");
for (unsigned I = 1; I != ExpectedDstINumUses; I += 2) {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &ValChild = Dst.getChild(I);
const TreePatternNode &SubRegChild = Dst.getChild(I + 1);
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
if (const DefInit *SubRegInit =
dyn_cast<DefInit>(SubRegChild.getLeafValue())) {
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
auto InsertPtOrError =
[GlobalISelEmitter] handle operand without MVT/class There are some patterns in td files without MVT/class set for some operands in target pattern that are from the source pattern. This prevents GlobalISelEmitter from adding them as a valid rule, because the target child operand is an unsupported kind operand. For now, for a leaf child, only IntInit and DefInit are handled in GlobalISelEmitter. This issue can be workaround by adding MVT/class to the patterns in the td files, like the workarounds for patterns anyext and setcc in PPCInstrInfo.td in D140878. To avoid adding the same workarounds for other patterns in td files, this patch tries to handle the UnsetInit case in GlobalISelEmitter. Adding the new handling allows us to remove the workarounds in the td files and also generates many selection rules for PPC target. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D141247
2023-01-09 04:07:52 +00:00
importExplicitUseRenderer(InsertPt, M, DstMIBuilder, ValChild, Src);
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
if (auto Error = InsertPtOrError.takeError())
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
InsertPt = InsertPtOrError.get();
DstMIBuilder.addRenderer<SubRegIndexRenderer>(SubIdx);
}
}
return InsertPt;
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
// Render the explicit uses.
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
unsigned DstINumUses = OrigDstI->Operands.size() - OrigDstI->Operands.NumDefs;
GlobalISel/TableGen: Handle REG_SEQUENCE patterns The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
2019-09-10 17:57:33 +00:00
if (Name == "COPY_TO_REGCLASS") {
[globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC Multi-instruction emission will require that we have separate handling for the defs between the implicitly created temporaries and the rule outputs. The former require new temporary vregs while the latter should copy existing operands. Factor out the implicit def/use renderers to minimize the code duplication when we implement that. llvm-svn: 317025
2017-10-31 19:09:29 +00:00
DstINumUses--; // Ignore the class constraint.
ExpectedDstINumUses--;
}
TableGen/GlobalISel: Handle default operands that are used Copy the logic from the existing handling in the DAG matcher emittter. This will enable some AMDGPU pattern cleanups without breaking GlobalISel tests, and eventually handle importing more patterns. The test is a bit annoying since the sections seem to randomly sort themselves if anything else is added in the future.
2019-10-21 21:39:42 -07:00
// NumResults - This is the number of results produced by the instruction in
// the "outs" list.
unsigned NumResults = OrigDstI->Operands.NumDefs;
// Number of operands we know the output instruction must have. If it is
// variadic, we could have more operands.
unsigned NumFixedOperands = DstI->Operands.size();
// Loop over all of the fixed operands of the instruction pattern, emitting
// code to fill them all in. The node 'N' usually has number children equal to
// the number of input operands of the instruction. However, in cases where
// there are predicate operands for an instruction, we need to fill in the
// 'execute always' values. Match up the node operands to the instruction
// operands to do this.
[globalisel][tablegen] Add experimental support for OperandWithDefaultOps, PredicateOperand, and OptionalDefOperand Summary: As far as instruction selection is concerned, all three appear to be same thing. Support for these operands is experimental since AArch64 doesn't make use of them and the in-tree targets that do use them (AMDGPU for OperandWithDefaultOps, AMDGPU/ARM/Hexagon/Lanai for PredicateOperand, and ARM for OperandWithDefaultOps) are not using tablegen-erated GlobalISel yet. Reviewers: rovka, aditya_nandakumar, t.p.northover, qcolombet, ab Reviewed By: rovka Subscribers: inglorion, aemerson, rengolin, mehdi_amini, dberris, kristof.beyls, igorb, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D31135 llvm-svn: 300037
2017-04-12 08:23:08 +00:00
unsigned Child = 0;
TableGen/GlobalISel: Handle default operands that are used Copy the logic from the existing handling in the DAG matcher emittter. This will enable some AMDGPU pattern cleanups without breaking GlobalISel tests, and eventually handle importing more patterns. The test is a bit annoying since the sections seem to randomly sort themselves if anything else is added in the future.
2019-10-21 21:39:42 -07:00
// Similarly to the code in TreePatternNode::ApplyTypeConstraints, count the
// number of operands at the end of the list which have default values.
// Those can come from the pattern if it provides enough arguments, or be
// filled in with the default if the pattern hasn't provided them. But any
// operand with a default value _before_ the last mandatory one will be
// filled in with their defaults unconditionally.
unsigned NonOverridableOperands = NumFixedOperands;
while (NonOverridableOperands > NumResults &&
CGP.operandHasDefault(DstI->Operands[NonOverridableOperands - 1].Rec))
--NonOverridableOperands;
[GlobalISel][TableGen] Fix handling of default operands When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
2017-05-17 08:57:28 +00:00
unsigned NumDefaultOps = 0;
[globalisel][tablegen] Add experimental support for OperandWithDefaultOps, PredicateOperand, and OptionalDefOperand Summary: As far as instruction selection is concerned, all three appear to be same thing. Support for these operands is experimental since AArch64 doesn't make use of them and the in-tree targets that do use them (AMDGPU for OperandWithDefaultOps, AMDGPU/ARM/Hexagon/Lanai for PredicateOperand, and ARM for OperandWithDefaultOps) are not using tablegen-erated GlobalISel yet. Reviewers: rovka, aditya_nandakumar, t.p.northover, qcolombet, ab Reviewed By: rovka Subscribers: inglorion, aemerson, rengolin, mehdi_amini, dberris, kristof.beyls, igorb, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D31135 llvm-svn: 300037
2017-04-12 08:23:08 +00:00
for (unsigned I = 0; I != DstINumUses; ++I) {
TableGen/GlobalISel: Handle default operands that are used Copy the logic from the existing handling in the DAG matcher emittter. This will enable some AMDGPU pattern cleanups without breaking GlobalISel tests, and eventually handle importing more patterns. The test is a bit annoying since the sections seem to randomly sort themselves if anything else is added in the future.
2019-10-21 21:39:42 -07:00
unsigned InstOpNo = DstI->Operands.NumDefs + I;
// Determine what to emit for this operand.
[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858) Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to const pointer. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-09 14:33:21 -07:00
const Record *OperandNode = DstI->Operands[InstOpNo].Rec;
[globalisel][tablegen] Add experimental support for OperandWithDefaultOps, PredicateOperand, and OptionalDefOperand Summary: As far as instruction selection is concerned, all three appear to be same thing. Support for these operands is experimental since AArch64 doesn't make use of them and the in-tree targets that do use them (AMDGPU for OperandWithDefaultOps, AMDGPU/ARM/Hexagon/Lanai for PredicateOperand, and ARM for OperandWithDefaultOps) are not using tablegen-erated GlobalISel yet. Reviewers: rovka, aditya_nandakumar, t.p.northover, qcolombet, ab Reviewed By: rovka Subscribers: inglorion, aemerson, rengolin, mehdi_amini, dberris, kristof.beyls, igorb, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D31135 llvm-svn: 300037
2017-04-12 08:23:08 +00:00
[GlobalISel][TableGen] Fix handling of default operands When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
2017-05-17 08:57:28 +00:00
// If the operand has default values, introduce them now.
TableGen/GlobalISel: Handle default operands that are used Copy the logic from the existing handling in the DAG matcher emittter. This will enable some AMDGPU pattern cleanups without breaking GlobalISel tests, and eventually handle importing more patterns. The test is a bit annoying since the sections seem to randomly sort themselves if anything else is added in the future.
2019-10-21 21:39:42 -07:00
if (CGP.operandHasDefault(OperandNode) &&
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
(InstOpNo < NonOverridableOperands || Child >= Dst.getNumChildren())) {
TableGen/GlobalISel: Handle default operands that are used Copy the logic from the existing handling in the DAG matcher emittter. This will enable some AMDGPU pattern cleanups without breaking GlobalISel tests, and eventually handle importing more patterns. The test is a bit annoying since the sections seem to randomly sort themselves if anything else is added in the future.
2019-10-21 21:39:42 -07:00
// This is a predicate or optional def operand which the pattern has not
// overridden, or which we aren't letting it override; emit the 'default
// ops' operands.
[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858) Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to const pointer. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-09 14:33:21 -07:00
const Record *OperandNode = DstI->Operands[InstOpNo].Rec;
[GISel][TableGen] Enhance default ops support (#75689) - Instead of checking the default ops directly, this change queries DAG default operands collected during patterns reading. It does not only simplify the code but also handle few cases where integer values are converted from convertible types, such as 'bits'. - A test case is added GlobalISelEmitter.td as the regression test of default 'bits' values.
2023-12-17 15:02:10 -05:00
if (auto Error = importDefaultOperandRenderers(
InsertPt, M, DstMIBuilder, CGP.getDefaultOperand(OperandNode)))
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
[GISel][TableGen] Enhance default ops support (#75689) - Instead of checking the default ops directly, this change queries DAG default operands collected during patterns reading. It does not only simplify the code but also handle few cases where integer values are converted from convertible types, such as 'bits'. - A test case is added GlobalISelEmitter.td as the regression test of default 'bits' values.
2023-12-17 15:02:10 -05:00
[GlobalISel][TableGen] Fix handling of default operands When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
2017-05-17 08:57:28 +00:00
++NumDefaultOps;
[globalisel][tablegen] Add experimental support for OperandWithDefaultOps, PredicateOperand, and OptionalDefOperand Summary: As far as instruction selection is concerned, all three appear to be same thing. Support for these operands is experimental since AArch64 doesn't make use of them and the in-tree targets that do use them (AMDGPU for OperandWithDefaultOps, AMDGPU/ARM/Hexagon/Lanai for PredicateOperand, and ARM for OperandWithDefaultOps) are not using tablegen-erated GlobalISel yet. Reviewers: rovka, aditya_nandakumar, t.p.northover, qcolombet, ab Reviewed By: rovka Subscribers: inglorion, aemerson, rengolin, mehdi_amini, dberris, kristof.beyls, igorb, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D31135 llvm-svn: 300037
2017-04-12 08:23:08 +00:00
continue;
}
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
auto InsertPtOrError = importExplicitUseRenderer(InsertPt, M, DstMIBuilder,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
Dst.getChild(Child), Src);
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
if (auto Error = InsertPtOrError.takeError())
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
InsertPt = InsertPtOrError.get();
[globalisel][tablegen] Add experimental support for OperandWithDefaultOps, PredicateOperand, and OptionalDefOperand Summary: As far as instruction selection is concerned, all three appear to be same thing. Support for these operands is experimental since AArch64 doesn't make use of them and the in-tree targets that do use them (AMDGPU for OperandWithDefaultOps, AMDGPU/ARM/Hexagon/Lanai for PredicateOperand, and ARM for OperandWithDefaultOps) are not using tablegen-erated GlobalISel yet. Reviewers: rovka, aditya_nandakumar, t.p.northover, qcolombet, ab Reviewed By: rovka Subscribers: inglorion, aemerson, rengolin, mehdi_amini, dberris, kristof.beyls, igorb, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D31135 llvm-svn: 300037
2017-04-12 08:23:08 +00:00
++Child;
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
if (NumDefaultOps + ExpectedDstINumUses != DstINumUses)
Fixup r303240: Use llvm::to_string instead of std::to_string It turns out some of the buildbots don't have std::to_string around, even in this day and age... llvm-svn: 303243
2017-05-17 09:25:08 +00:00
return failedImport("Expected " + llvm::to_string(DstINumUses) +
[GlobalISel][TableGen] Fix handling of default operands When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
2017-05-17 08:57:28 +00:00
" used operands but found " +
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
llvm::to_string(ExpectedDstINumUses) +
Fixup r303240: Use llvm::to_string instead of std::to_string It turns out some of the buildbots don't have std::to_string around, even in this day and age... llvm-svn: 303243
2017-05-17 09:25:08 +00:00
" explicit ones and " + llvm::to_string(NumDefaultOps) +
[GlobalISel][TableGen] Fix handling of default operands When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
2017-05-17 08:57:28 +00:00
" default ones");
Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC Multi-instruction emission needs to ensure the the instructions are generated a depth-first fashion. For example: (ADDWrr (SUBWrr a, b), c) needs to emit the SUBWrr before the ADDWrr. However, our walk over TreePatternNode's is highly context sensitive which makes it difficult to append BuildMIActions in the order we want. To fix this, we now keep track of the insertion point as we add actions. This will allow multi-insn emission to insert BuildMI's in the correct place. The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the const_iterator forms of insert() and emplace() that were added in C++11. As a result I've switched the const_iterators to iterators. llvm-svn: 317049
2017-10-31 23:03:18 +00:00
return InsertPt;
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
[GlobalISel][TableGen] Fix handling of default operands When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
2017-05-17 08:57:28 +00:00
Error GlobalISelEmitter::importDefaultOperandRenderers(
[TableGen] New default operand "undef_tied_input" This is a new special identifier which you can use as a default in OperandWithDefaultOps. The idea is that you use it for an input operand of an instruction that's tied to an output operand, and its semantics are that (in the default case) the input operand's value is not used at all. The detailed effect is that when instruction selection emits the instruction in the form of a pre-regalloc MachineInstr, it creates an IMPLICIT_DEF node to use as that input. If you're creating an MCInst with explicit register names, then the right handling would be to set the input operand to the same register as the output one (honouring the tie) and to add the 'undef' flag indicating that that register is deemed to acquire a new don't-care definition just before we read it. But I haven't done that in this commit, because there was no need to - no Tablegen backend seems to autogenerate default fields in an MCInst. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60696 llvm-svn: 362064
2019-05-30 07:30:37 +00:00
action_iterator InsertPt, RuleMatcher &M, BuildMIAction &DstMIBuilder,
[GISel][TableGen] Enhance default ops support (#75689) - Instead of checking the default ops directly, this change queries DAG default operands collected during patterns reading. It does not only simplify the code but also handle few cases where integer values are converted from convertible types, such as 'bits'. - A test case is added GlobalISelEmitter.td as the regression test of default 'bits' values.
2023-12-17 15:02:10 -05:00
const DAGDefaultOperand &DefaultOp) const {
for (const auto &Op : DefaultOp.DefaultOps) {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const auto &N = *Op;
if (!N.isLeaf())
[GISel][TableGen] Enhance default ops support (#75689) - Instead of checking the default ops directly, this change queries DAG default operands collected during patterns reading. It does not only simplify the code but also handle few cases where integer values are converted from convertible types, such as 'bits'. - A test case is added GlobalISelEmitter.td as the regression test of default 'bits' values.
2023-12-17 15:02:10 -05:00
return failedImport("Could not add default op");
[TableGen] New default operand "undef_tied_input" This is a new special identifier which you can use as a default in OperandWithDefaultOps. The idea is that you use it for an input operand of an instruction that's tied to an output operand, and its semantics are that (in the default case) the input operand's value is not used at all. The detailed effect is that when instruction selection emits the instruction in the form of a pre-regalloc MachineInstr, it creates an IMPLICIT_DEF node to use as that input. If you're creating an MCInst with explicit register names, then the right handling would be to set the input operand to the same register as the output one (honouring the tie) and to add the 'undef' flag indicating that that register is deemed to acquire a new don't-care definition just before we read it. But I haven't done that in this commit, because there was no need to - no Tablegen backend seems to autogenerate default fields in an MCInst. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60696 llvm-svn: 362064
2019-05-30 07:30:37 +00:00
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const auto *DefaultOp = N.getLeafValue();
[GlobalISel][TableGen] Fix handling of default operands When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
2017-05-17 08:57:28 +00:00
if (const DefInit *DefaultDefOp = dyn_cast<DefInit>(DefaultOp)) {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
std::optional<LLTCodeGen> OpTyOrNone = MVTToLLT(N.getSimpleType(0));
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
auto *Def = DefaultDefOp->getDef();
[TableGen] New default operand "undef_tied_input" This is a new special identifier which you can use as a default in OperandWithDefaultOps. The idea is that you use it for an input operand of an instruction that's tied to an output operand, and its semantics are that (in the default case) the input operand's value is not used at all. The detailed effect is that when instruction selection emits the instruction in the form of a pre-regalloc MachineInstr, it creates an IMPLICIT_DEF node to use as that input. If you're creating an MCInst with explicit register names, then the right handling would be to set the input operand to the same register as the output one (honouring the tie) and to add the 'undef' flag indicating that that register is deemed to acquire a new don't-care definition just before we read it. But I haven't done that in this commit, because there was no need to - no Tablegen backend seems to autogenerate default fields in an MCInst. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60696 llvm-svn: 362064
2019-05-30 07:30:37 +00:00
if (Def->getName() == "undef_tied_input") {
unsigned TempRegID = M.allocateTempRegID();
std::optional::value => operator*/operator-> value() has undesired exception checking semantics and calls __throw_bad_optional_access in libc++. Moreover, the API is unavailable without _LIBCPP_NO_EXCEPTIONS on older Mach-O platforms (see _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS). This commit fixes LLVMAnalysis and its dependencies.
2022-12-16 22:44:08 +00:00
M.insertAction<MakeTempRegisterAction>(InsertPt, *OpTyOrNone,
[llvm] Use value instead of getValue (NFC)
2022-07-13 23:11:56 -07:00
TempRegID);
[TableGen] New default operand "undef_tied_input" This is a new special identifier which you can use as a default in OperandWithDefaultOps. The idea is that you use it for an input operand of an instruction that's tied to an output operand, and its semantics are that (in the default case) the input operand's value is not used at all. The detailed effect is that when instruction selection emits the instruction in the form of a pre-regalloc MachineInstr, it creates an IMPLICIT_DEF node to use as that input. If you're creating an MCInst with explicit register names, then the right handling would be to set the input operand to the same register as the output one (honouring the tie) and to add the 'undef' flag indicating that that register is deemed to acquire a new don't-care definition just before we read it. But I haven't done that in this commit, because there was no need to - no Tablegen backend seems to autogenerate default fields in an MCInst. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60696 llvm-svn: 362064
2019-05-30 07:30:37 +00:00
InsertPt = M.insertAction<BuildMIAction>(
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
InsertPt, M.allocateOutputInsnID(),
&Target.getInstruction(RK.getDef("IMPLICIT_DEF")));
BuildMIAction &IDMIBuilder =
*static_cast<BuildMIAction *>(InsertPt->get());
[TableGen] New default operand "undef_tied_input" This is a new special identifier which you can use as a default in OperandWithDefaultOps. The idea is that you use it for an input operand of an instruction that's tied to an output operand, and its semantics are that (in the default case) the input operand's value is not used at all. The detailed effect is that when instruction selection emits the instruction in the form of a pre-regalloc MachineInstr, it creates an IMPLICIT_DEF node to use as that input. If you're creating an MCInst with explicit register names, then the right handling would be to set the input operand to the same register as the output one (honouring the tie) and to add the 'undef' flag indicating that that register is deemed to acquire a new don't-care definition just before we read it. But I haven't done that in this commit, because there was no need to - no Tablegen backend seems to autogenerate default fields in an MCInst. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60696 llvm-svn: 362064
2019-05-30 07:30:37 +00:00
IDMIBuilder.addRenderer<TempRegRenderer>(TempRegID);
DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID);
} else {
[TableGen][GlobalISel] Fix handling of zero_reg When generating matching tables for GlobalISel, TableGen would output "::zero_reg" whenever encountering the zero_reg, which in turn would result in compilation error. This patch fixes that by instead outputting NoRegister (== 0), which is the same result that TableGen produces when generating matching tables for ISelDAG. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D86215
2020-09-18 10:08:32 +02:00
DstMIBuilder.addRenderer<AddRegisterRenderer>(Target, Def);
[TableGen] New default operand "undef_tied_input" This is a new special identifier which you can use as a default in OperandWithDefaultOps. The idea is that you use it for an input operand of an instruction that's tied to an output operand, and its semantics are that (in the default case) the input operand's value is not used at all. The detailed effect is that when instruction selection emits the instruction in the form of a pre-regalloc MachineInstr, it creates an IMPLICIT_DEF node to use as that input. If you're creating an MCInst with explicit register names, then the right handling would be to set the input operand to the same register as the output one (honouring the tie) and to add the 'undef' flag indicating that that register is deemed to acquire a new don't-care definition just before we read it. But I haven't done that in this commit, because there was no need to - no Tablegen backend seems to autogenerate default fields in an MCInst. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60696 llvm-svn: 362064
2019-05-30 07:30:37 +00:00
}
[GlobalISel][TableGen] Fix handling of default operands When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
2017-05-17 08:57:28 +00:00
continue;
}
if (const IntInit *DefaultIntOp = dyn_cast<IntInit>(DefaultOp)) {
[globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFC The next commit will add support for multi-instruction emission so we need to start allocating instruction ID's instead of hard-coding them to 0. llvm-svn: 317057
2017-11-01 00:29:47 +00:00
DstMIBuilder.addRenderer<ImmRenderer>(DefaultIntOp->getValue());
[GlobalISel][TableGen] Fix handling of default operands When looping through a destination pattern's operands to decide how many default operands we need to introduce, we used to count the "expanded" number of operands. So if one default operand would be rendered as 2 values, we'd count it as 2 operands, when in fact it needs to count as only 1 operand regardless of how many values it expands to. This turns out to be a problem only in some very specific cases, e.g. when we have one operand with multiple default values followed by more operands with default values (see the new test). In such a situation we'd stop looping before looking at all the operands, and then error out assuming that we don't have enough default operands to make up the shortfall. At the moment this only affects ARM. The patch removes the loop counting default operands entirely and assumes that we'll have to introduce values for any default operand that we find (i.e. we're assuming it cannot be given as a child at all). It also extracts the code for adding renderers for default operands into a helper method. Differential Revision: https://reviews.llvm.org/D33031 llvm-svn: 303240
2017-05-17 08:57:28 +00:00
continue;
}
return failedImport("Could not add default op");
}
return Error::success();
}
[globalisel][tablegen] Change Expected<bool> to Error and rename functions. Functions that still return Expected<X> are now called createAndImport*() Changing the return type was requested in the review comments for r299001 llvm-svn: 299063
2017-03-30 09:36:33 +00:00
Error GlobalISelEmitter::importImplicitDefRenderers(
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
BuildMIAction &DstMIBuilder, ArrayRef<const Record *> ImplicitDefs) const {
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
if (!ImplicitDefs.empty())
return failedImport("Pattern defines a physical register");
[globalisel][tablegen] Change Expected<bool> to Error and rename functions. Functions that still return Expected<X> are now called createAndImport*() Changing the return type was requested in the review comments for r299001 llvm-svn: 299063
2017-03-30 09:36:33 +00:00
return Error::success();
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
}
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
[TableGen][GISel] Extract helper function for constraining operands (#115148) As a side effect, this fixes COPY_TO_REGCLASS not being constrained if it is not top-level (the reason for changes in tests).
2024-11-07 07:16:54 +03:00
Error GlobalISelEmitter::constrainOperands(action_iterator InsertPt,
RuleMatcher &M, unsigned InsnID,
const TreePatternNode &Dst) {
const Record *DstOp = Dst.getOperator();
const CodeGenInstruction &DstI = Target.getInstruction(DstOp);
StringRef DstIName = DstI.TheDef->getName();
if (DstIName == "COPY_TO_REGCLASS") {
// COPY_TO_REGCLASS does not provide operand constraints itself but the
// result is constrained to the class given by the second child.
const Record *DstIOpRec =
getInitValueAsRegClass(Dst.getChild(1).getLeafValue());
if (DstIOpRec == nullptr)
return failedImport("COPY_TO_REGCLASS operand #1 isn't a register class");
M.insertAction<ConstrainOperandToRegClassAction>(
InsertPt, InsnID, 0, Target.getRegisterClass(DstIOpRec));
} else if (DstIName == "EXTRACT_SUBREG") {
auto SuperClass = inferRegClassFromPattern(Dst.getChild(0));
if (!SuperClass)
return failedImport(
"Cannot infer register class from EXTRACT_SUBREG operand #0");
auto SubIdx = inferSubRegIndexForNode(Dst.getChild(1));
if (!SubIdx)
return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");
// It would be nice to leave this constraint implicit but we're required
// to pick a register class so constrain the result to a register class
// that can hold the correct MVT.
//
// FIXME: This may introduce an extra copy if the chosen class doesn't
// actually contain the subregisters.
const auto SrcRCDstRCPair =
(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
if (!SrcRCDstRCPair) {
return failedImport("subreg index is incompatible "
"with inferred reg class");
}
assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
M.insertAction<ConstrainOperandToRegClassAction>(InsertPt, InsnID, 0,
*SrcRCDstRCPair->second);
M.insertAction<ConstrainOperandToRegClassAction>(InsertPt, InsnID, 1,
*SrcRCDstRCPair->first);
} else if (DstIName == "INSERT_SUBREG") {
// We need to constrain the destination, a super regsister source, and a
// subregister source.
auto SubClass = inferRegClassFromPattern(Dst.getChild(1));
if (!SubClass)
return failedImport(
"Cannot infer register class from INSERT_SUBREG operand #1");
auto SuperClass = inferSuperRegisterClassForNode(
Dst.getExtType(0), Dst.getChild(0), Dst.getChild(2));
if (!SuperClass)
return failedImport(
"Cannot infer register class for INSERT_SUBREG operand #0");
M.insertAction<ConstrainOperandToRegClassAction>(InsertPt, InsnID, 0,
**SuperClass);
M.insertAction<ConstrainOperandToRegClassAction>(InsertPt, InsnID, 1,
**SuperClass);
M.insertAction<ConstrainOperandToRegClassAction>(InsertPt, InsnID, 2,
**SubClass);
} else if (DstIName == "SUBREG_TO_REG") {
// We need to constrain the destination and subregister source.
// Attempt to infer the subregister source from the first child. If it has
// an explicitly given register class, we'll use that. Otherwise, we will
// fail.
auto SubClass = inferRegClassFromPattern(Dst.getChild(1));
if (!SubClass)
return failedImport(
"Cannot infer register class from SUBREG_TO_REG child #1");
// We don't have a child to look at that might have a super register node.
auto SuperClass =
inferSuperRegisterClass(Dst.getExtType(0), Dst.getChild(2));
if (!SuperClass)
return failedImport(
"Cannot infer register class for SUBREG_TO_REG operand #0");
M.insertAction<ConstrainOperandToRegClassAction>(InsertPt, InsnID, 0,
**SuperClass);
M.insertAction<ConstrainOperandToRegClassAction>(InsertPt, InsnID, 2,
**SubClass);
} else if (DstIName == "REG_SEQUENCE") {
auto SuperClass = inferRegClassFromPattern(Dst.getChild(0));
M.insertAction<ConstrainOperandToRegClassAction>(InsertPt, InsnID, 0,
**SuperClass);
unsigned Num = Dst.getNumChildren();
for (unsigned I = 1; I != Num; I += 2) {
const TreePatternNode &SubRegChild = Dst.getChild(I + 1);
auto SubIdx = inferSubRegIndexForNode(SubRegChild);
if (!SubIdx)
return failedImport("REG_SEQUENCE child is not a subreg index");
const auto SrcRCDstRCPair =
(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
M.insertAction<ConstrainOperandToRegClassAction>(InsertPt, InsnID, I,
*SrcRCDstRCPair->second);
}
} else {
M.insertAction<ConstrainOperandsToDefinitionAction>(InsertPt, InsnID);
}
return Error::success();
}
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<const CodeGenRegisterClass *>
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
GlobalISelEmitter::getRegClassFromLeaf(const TreePatternNode &Leaf) {
assert(Leaf.isLeaf() && "Expected leaf?");
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const Record *RCRec = getInitValueAsRegClass(Leaf.getLeafValue());
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
if (!RCRec)
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const CodeGenRegisterClass *RC = CGRegs.getRegClass(RCRec);
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
if (!RC)
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
return RC;
}
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<const CodeGenRegisterClass *>
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
GlobalISelEmitter::inferRegClassFromPattern(const TreePatternNode &N) {
if (N.isLeaf())
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
return getRegClassFromLeaf(N);
// We don't have a leaf node, so we have to try and infer something. Check
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130) Previously, tblgen would reject patterns where one of its nested instructions produced more than one result. These arise when the instruction definition contains 'outs' as well as 'Defs'. This patch fixes that by always taking the first result, which is how these situations are handled in SelectionIDAG. Original patch: https://reviews.llvm.org/D86617 Continued as: https://github.com/llvm/llvm-project/pull/81130
2023-11-03 12:44:38 +01:00
// that we have an instruction that we can infer something from.
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130) Previously, tblgen would reject patterns where one of its nested instructions produced more than one result. These arise when the instruction definition contains 'outs' as well as 'Defs'. This patch fixes that by always taking the first result, which is how these situations are handled in SelectionIDAG. Original patch: https://reviews.llvm.org/D86617 Continued as: https://github.com/llvm/llvm-project/pull/81130
2023-11-03 12:44:38 +01:00
// Only handle things that produce at least one value (if multiple values,
// just take the first one).
if (N.getNumTypes() < 1)
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
[TableGen] Change CodeGenInstruction record members to const (#107921) Change CodeGenInstruction::{TheDef, InfereredFrom} to const pointers. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-11 08:52:26 -07:00
const Record *OpRec = N.getOperator();
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
// We only want instructions.
if (!OpRec->isSubClassOf("Instruction"))
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
// Don't want to try and infer things when there could potentially be more
// than one candidate register class.
auto &Inst = Target.getInstruction(OpRec);
// Handle any special-case instructions which we can safely infer register
// classes from.
StringRef InstName = Inst.TheDef->getName();
GlobalISel/TableGen: Don't skip REG_SEQUENCE based on patterns This partially adds support for patterns with REG_SEQUENCE. The source patterns are now accepted, but the pattern is still rejected due to missing support for the instruction renderer. llvm-svn: 370920
2019-09-04 16:19:34 +00:00
bool IsRegSequence = InstName == "REG_SEQUENCE";
if (IsRegSequence || InstName == "COPY_TO_REGCLASS") {
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
// If we have a COPY_TO_REGCLASS, then we need to handle it specially. It
// has the desired register class as the first child.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &RCChild = N.getChild(IsRegSequence ? 0 : 1);
if (!RCChild.isLeaf())
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
return getRegClassFromLeaf(RCChild);
}
[TableGen][GlobalISel] add handling of nested *_SUBREG When nesting INSERT_SUBREG and EXTRACT_SUBREG, GlobalISelEmitter would fail to find the register class of the nested node. This patch fixes that for registers with subregs. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D88487
2020-10-05 10:28:50 +02:00
if (InstName == "INSERT_SUBREG") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &Child0 = N.getChild(0);
assert(Child0.getNumTypes() == 1 && "Unexpected number of types!");
const TypeSetByHwMode &VTy = Child0.getExtType(0);
return inferSuperRegisterClassForNode(VTy, Child0, N.getChild(2));
[TableGen][GlobalISel] add handling of nested *_SUBREG When nesting INSERT_SUBREG and EXTRACT_SUBREG, GlobalISelEmitter would fail to find the register class of the nested node. This patch fixes that for registers with subregs. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D88487
2020-10-05 10:28:50 +02:00
}
if (InstName == "EXTRACT_SUBREG") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
assert(N.getNumTypes() == 1 && "Unexpected number of types!");
const TypeSetByHwMode &VTy = N.getExtType(0);
return inferSuperRegisterClass(VTy, N.getChild(1));
[TableGen][GlobalISel] add handling of nested *_SUBREG When nesting INSERT_SUBREG and EXTRACT_SUBREG, GlobalISelEmitter would fail to find the register class of the nested node. This patch fixes that for registers with subregs. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D88487
2020-10-05 10:28:50 +02:00
}
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
// Handle destination record types that we can safely infer a register class
// from.
const auto &DstIOperand = Inst.Operands[0];
[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858) Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to const pointer. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-09 14:33:21 -07:00
const Record *DstIOpRec = DstIOperand.Rec;
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
if (DstIOpRec->isSubClassOf("RegisterOperand")) {
DstIOpRec = DstIOpRec->getValueAsDef("RegClass");
const CodeGenRegisterClass &RC = Target.getRegisterClass(DstIOpRec);
return &RC;
}
if (DstIOpRec->isSubClassOf("RegisterClass")) {
const CodeGenRegisterClass &RC = Target.getRegisterClass(DstIOpRec);
return &RC;
}
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
}
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<const CodeGenRegisterClass *>
[TableGen] Const-correct TreePatternNode::getChild. NFC Make the const version return a const TreePatterNode* and add a non-const version to return a non-const TreePatternNode*.
2023-04-18 01:19:29 -07:00
GlobalISelEmitter::inferSuperRegisterClass(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TypeSetByHwMode &Ty, const TreePatternNode &SubRegIdxNode) {
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
// We need a ValueTypeByHwMode for getSuperRegForSubReg.
if (!Ty.isValueTypeByHwMode(false))
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (!SubRegIdxNode.isLeaf())
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const DefInit *SubRegInit = dyn_cast<DefInit>(SubRegIdxNode.getLeafValue());
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
if (!SubRegInit)
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
// Use the information we found above to find a minimal register class which
// supports the subregister and type we want.
auto RC =
[GlobalISel][TableGen] Fix ConstrainOperandRC bug TableGen would pick the largest RC for constraining the operands, which could potentially be an unallocatable RC. This patch removes selection of unallocatable RCs. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D93945
2021-01-05 09:12:58 +01:00
Target.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), CGRegs, SubIdx,
/* MustBeAllocatable */ true);
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
if (!RC)
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
return *RC;
}
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
std::optional<const CodeGenRegisterClass *>
[GlobalISel] Import patterns containing SUBREG_TO_REG Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns. - Split `inferSuperRegisterClass` into two functions, one which tries to use an existing TreePatternNode (`inferSuperRegisterClassForNode`), and one that doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause for the split. - Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and update it. - Update impacted tests in the AArch64 and X86 backends. This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness. Differential Revision: https://reviews.llvm.org/D66769 llvm-svn: 370254
2019-08-28 20:12:31 +00:00
GlobalISelEmitter::inferSuperRegisterClassForNode(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TypeSetByHwMode &Ty, const TreePatternNode &SuperRegNode,
const TreePatternNode &SubRegIdxNode) {
[GlobalISel] Import patterns containing SUBREG_TO_REG Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns. - Split `inferSuperRegisterClass` into two functions, one which tries to use an existing TreePatternNode (`inferSuperRegisterClassForNode`), and one that doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause for the split. - Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and update it. - Update impacted tests in the AArch64 and X86 backends. This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness. Differential Revision: https://reviews.llvm.org/D66769 llvm-svn: 370254
2019-08-28 20:12:31 +00:00
// Check if we already have a defined register class for the super register
// node. If we do, then we should preserve that rather than inferring anything
// from the subregister index node. We can assume that whoever wrote the
// pattern in the first place made sure that the super register and
// subregister are compatible.
[TableGen] llvm::Optional => std::optional
2022-12-06 07:21:02 +00:00
if (std::optional<const CodeGenRegisterClass *> SuperRegisterClass =
[GlobalISel] Import patterns containing SUBREG_TO_REG Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns. - Split `inferSuperRegisterClass` into two functions, one which tries to use an existing TreePatternNode (`inferSuperRegisterClassForNode`), and one that doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause for the split. - Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and update it. - Update impacted tests in the AArch64 and X86 backends. This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness. Differential Revision: https://reviews.llvm.org/D66769 llvm-svn: 370254
2019-08-28 20:12:31 +00:00
inferRegClassFromPattern(SuperRegNode))
return *SuperRegisterClass;
return inferSuperRegisterClass(Ty, SubRegIdxNode);
}
[TableGen] Const-correct TreePatternNode::getChild. NFC Make the const version return a const TreePatterNode* and add a non-const version to return a non-const TreePatternNode*.
2023-04-18 01:19:29 -07:00
std::optional<CodeGenSubRegIndex *> GlobalISelEmitter::inferSubRegIndexForNode(
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TreePatternNode &SubRegIdxNode) {
if (!SubRegIdxNode.isLeaf())
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
GlobalISel/TableGen: Fix handling of EXTRACT_SUBREG constraints This was only using the correct register constraints if this was the final result instruction. If the extract was a sub instruction of the result, it would attempt to use GIR_ConstrainSelectedInstOperands on a COPY, which won't work. Move the handling to createAndImportSubInstructionRenderer so it works correctly. I don't fully understand why runOnPattern and createAndImportSubInstructionRenderer both need to handle these special cases, and constrain them with slightly different methods. If I remove the runOnPattern handling, it does break the constraint when the final result instruction is EXTRACT_SUBREG. llvm-svn: 371150
2019-09-06 00:05:58 +00:00
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
const DefInit *SubRegInit = dyn_cast<DefInit>(SubRegIdxNode.getLeafValue());
GlobalISel/TableGen: Fix handling of EXTRACT_SUBREG constraints This was only using the correct register constraints if this was the final result instruction. If the extract was a sub instruction of the result, it would attempt to use GIR_ConstrainSelectedInstOperands on a COPY, which won't work. Move the handling to createAndImportSubInstructionRenderer so it works correctly. I don't fully understand why runOnPattern and createAndImportSubInstructionRenderer both need to handle these special cases, and constrain them with slightly different methods. If I remove the runOnPattern handling, it does break the constraint when the final result instruction is EXTRACT_SUBREG. llvm-svn: 371150
2019-09-06 00:05:58 +00:00
if (!SubRegInit)
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
return std::nullopt;
GlobalISel/TableGen: Fix handling of EXTRACT_SUBREG constraints This was only using the correct register constraints if this was the final result instruction. If the extract was a sub instruction of the result, it would attempt to use GIR_ConstrainSelectedInstOperands on a COPY, which won't work. Move the handling to createAndImportSubInstructionRenderer so it works correctly. I don't fully understand why runOnPattern and createAndImportSubInstructionRenderer both need to handle these special cases, and constrain them with slightly different methods. If I remove the runOnPattern handling, it does break the constraint when the final result instruction is EXTRACT_SUBREG. llvm-svn: 371150
2019-09-06 00:05:58 +00:00
return CGRegs.getSubRegIdx(SubRegInit->getDef());
}
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
// Keep track of the matchers and actions to emit.
[GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAG This patch changes GlobalISelEmitter to rank patterns similar to how the DAG does it (ie it computes a score for a pattern and adds the added complexity to it). This is so that the decision tree for GISelSelector remains compatible with that of SelectionDAG. https://reviews.llvm.org/D43270 llvm-svn: 325401
2018-02-16 22:37:15 +00:00
int Score = P.getPatternComplexity(CGP);
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
RuleMatcher M(P.getSrcRecord()->getLoc());
[GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAG This patch changes GlobalISelEmitter to rank patterns similar to how the DAG does it (ie it computes a score for a pattern and adds the added complexity to it). This is so that the decision tree for GISelSelector remains compatible with that of SelectionDAG. https://reviews.llvm.org/D43270 llvm-svn: 325401
2018-02-16 22:37:15 +00:00
RuleMatcherScores[M.getRuleID()] = Score;
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
M.addAction<DebugCommentAction>(llvm::to_string(P.getSrcPattern()) +
[globalisel][tablegen] Allow any comment in DebugCommentAction. NFC llvm-svn: 317017
2017-10-31 18:07:03 +00:00
" => " +
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
llvm::to_string(P.getDstPattern()));
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
SmallVector<const Record *, 4> Predicates;
[TableGen] Store predicates in PatternToMatch as ListInit *. Add string for HwModeFeatures This uses to be how predicates were handled prior to HwMode being added. When the Predicates were converted to a std::vector it significantly increased the cost of a compare in GenerateVariants. Since ListInit's are uniquified by tablegen, we can use a simple pointer comparison to check for identical lists. In order to store the HwMode, we now add a separate string to PatternToMatch. This will be appended separately to the predicate string in getPredicateCheck. A new getPredicateRecords is added to allow GlobalISel and getPredicateCheck to both get the sorted list of Records. GlobalISel was ignoring any HwMode predicates before and still is. There is one slight change here, ListInits with different predicate orders aren't sorted so the filtering in GenerateVariants might fail to detect two isomorphic patterns with different predicate orders. This doesn't seem to be happening in tree today. My hope is this will allow us to remove all the BitVector tracking in GenerateVariants that was making up for predicates beeing expensive to compare. There's a decent amount of heap allocations there on large targets like X86, AMDGPU, and RISCV. Differential Revision: https://reviews.llvm.org/D100691
2021-04-28 11:13:10 -07:00
P.getPredicateRecords(Predicates);
if (auto Error = importRulePredicates(M, Predicates))
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
[GlobalISel][RISCV][TableGen] Teach GlobalISelEmitter about HwMode. Similar to SelectionDAG, this patch treats HwMode as an additional predicate that needs to be satisfied for GIM_CheckFeatures. The existing predicate passes around Record * that point to predicate records. While HwMode expansion creates a string that needs to be checked. Each HwMode predicate string is uniqued by a new map that assigns it an index. Each Rule stores the index, or -1 if HwMode doesn't apply. The HwMode indices each create a new Predicate feature bit and the check string from the HwMode is used to set the feature bit. GIM_CheckFeatures is emitted when the rule has Predicates or the HwModeIdx is not -1. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D158660
2023-08-23 21:04:28 -07:00
if (!P.getHwModeFeatures().empty())
M.addHwModeIdx(declareHwModeCheck(P.getHwModeFeatures()));
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
// Next, analyze the pattern operators.
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
TreePatternNode &Src = P.getSrcPattern();
TreePatternNode &Dst = P.getDstPattern();
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
// If the root of either pattern isn't a simple operator, ignore it.
[globalisel][tablegen] Report more detail in some SelectionDAG import failures. NFC Reviewers: ab, t.p.northover, qcolombet, aditya_nandakumar, rovka Reviewed By: ab Subscribers: dberris, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31325 llvm-svn: 300186
2017-04-13 09:45:37 +00:00
if (auto Err = isTrivialOperatorNode(Dst))
return failedImport("Dst pattern root isn't a trivial operator (" +
toString(std::move(Err)) + ")");
if (auto Err = isTrivialOperatorNode(Src))
return failedImport("Src pattern root isn't a trivial operator (" +
toString(std::move(Err)) + ")");
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
[TableGen][GlobalISel] Have the predicate directly know which data they are dealing with Prior to this patch, a predicate wouldn't make sense outside of its rule. Indeed, it was only during emitting a rule that a predicate would be made aware of the IDs of the data it is checking. Because of that, predicates could not be moved around or compared between each other. NFC. llvm-svn: 320887
2017-12-15 23:07:42 +00:00
// The different predicates and matchers created during
// addInstructionMatcher use the RuleMatcher M to set up their
// instruction ID (InsnVarID) that are going to be used when
// M is going to be emitted.
// However, the code doing the emission still relies on the IDs
// returned during that process by the RuleMatcher when issuing
// the recordInsn opcodes.
// Because of that:
// 1. The order in which we created the predicates
// and such must be the same as the order in which we emit them,
// and
// 2. We need to reset the generation of the IDs in M somewhere between
// addInstructionMatcher and emit
//
// FIXME: Long term, we don't want to have to rely on this implicit
// naming being the same. One possible solution would be to have
// explicit operator for operation capture and reference those.
// The plus side is that it would expose opportunities to share
// the capture accross rules. The downside is that it would
// introduce a dependency between predicates (captures must happen
// before their first use.)
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
InstructionMatcher &InsnMatcherTemp = M.addInstructionMatcher(Src.getName());
Re-commit: [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
2017-08-17 09:26:14 +00:00
unsigned TempOpIdx = 0;
[RFC][GISel] Add a way to ignore COPY instructions in InstructionSelector RFC to add a way to ignore COPY instructions when pattern-matching MIR in GISel. - Add a new "GISelFlags" class to TableGen. Both `Pattern` and `PatFrags` defs can use it to alter matching behaviour. - Flags start at zero and are scoped: the setter returns a `SaveAndRestore` object so that when the current scope ends, the flags are restored to their previous values. This allows child patterns to modify the flags without affecting the parent pattern. - Child patterns always reuse the parent's pattern, but they can override its values. For more examples, see `GlobalISelEmitterFlags.td` tests. - [AMDGPU] Use the IgnoreCopies flag in BFI patterns, which are known to be bothered by cross-regbank copies. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D136234
2023-01-25 14:06:09 +01:00
const auto SavedFlags = M.setGISelFlags(P.getSrcRecord());
Re-commit: [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
2017-08-17 09:26:14 +00:00
auto InsnMatcherOrError =
Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as an operator Summary: It's possible for a ComplexPattern to be used as an operator in a match pattern. This is used by the load/store patterns in AArch64 to name the suboperands returned by ComplexPattern predicate so that they can be broken apart and referenced independently in the result pattern. This patch adds support for this in order to enable the import of load/store patterns. Depends on D37445 Hopefully fixed the ambiguous constructor that a large number of bots reported. Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37456 llvm-svn: 315869
2017-10-15 18:22:54 +00:00
createAndImportSelDAGMatcher(M, InsnMatcherTemp, Src, TempOpIdx);
Re-commit: [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
2017-08-17 09:26:14 +00:00
if (auto Error = InsnMatcherOrError.takeError())
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
Re-commit: [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
2017-08-17 09:26:14 +00:00
InstructionMatcher &InsnMatcher = InsnMatcherOrError.get();
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
if (Dst.isLeaf()) {
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
if (const Record *RCDef = getInitValueAsRegClass(Dst.getLeafValue())) {
[GlobalISel][TableGen] Fix seg fault for zero instruction Tablegen seg faulted when parsing a Pat where the destination part has no output (zero instruction), due to a register class lookup using nullptr. Reviewed By: Paul-C-Anagnostopoulos Differential Revision: https://reviews.llvm.org/D90829
2020-11-24 07:12:54 +01:00
const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
Re-commit: [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
2017-08-17 09:26:14 +00:00
// We need to replace the def and all its uses with the specified
// operand. However, we must also insert COPY's wherever needed.
// For now, emit a copy and let the register allocator clean up.
auto &DstI = Target.getInstruction(RK.getDef("COPY"));
const auto &DstIOperand = DstI.Operands[0];
OperandMatcher &OM0 = InsnMatcher.getOperand(0);
OM0.setSymbolicName(DstIOperand.Name);
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
M.defineOperand(OM0.getSymbolicName(), OM0);
Re-commit: [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
2017-08-17 09:26:14 +00:00
OM0.addPredicate<RegisterBankOperandMatcher>(RC);
[globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFC The next commit will add support for multi-instruction emission so we need to start allocating instruction ID's instead of hard-coding them to 0. llvm-svn: 317057
2017-11-01 00:29:47 +00:00
auto &DstMIBuilder =
M.addAction<BuildMIAction>(M.allocateOutputInsnID(), &DstI);
DstMIBuilder.addRenderer<CopyRenderer>(DstIOperand.Name);
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
DstMIBuilder.addRenderer<CopyRenderer>(Dst.getName());
Re-commit: [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
2017-08-17 09:26:14 +00:00
M.addAction<ConstrainOperandToRegClassAction>(0, 0, RC);
[GISel] Erase the root instruction after emitting all its potential uses (#77494) This tries to fix a bug by resolving a few FIXMEs. The bug is that `EraseInstAction` is emitted after emitting the _first_ `BuildMIAction`, which is too early because the erased instruction may still be used by subsequent `BuildMIAction`s (in particular, by `CopyRenderer`). An example of the bug (from `match-table-operand-types.td`): ``` def InstTest0 : GICombineRule< (defs root:$a), (match (G_MUL i32:$x, i32:$b, i32:$c), (G_MUL $a, i32:$b, i32:$x)), (apply (G_ADD i64:$tmp, $b, i32:$c), (G_ADD i8:$a, $b, i64:$tmp))>; GIR_EraseFromParent, /*InsnID*/0, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, ``` Here, the root instruction is destroyed before copying its operands ('a' and 'b') to the new instruction. The solution is to emit `EraseInstAction` for the root instruction as the last action in the emission pipeline.
2024-01-13 11:17:41 +03:00
// Erase the root.
unsigned RootInsnID = M.getInsnVarID(InsnMatcher);
M.addAction<EraseInstAction>(RootInsnID);
Re-commit: [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
2017-08-17 09:26:14 +00:00
// We're done with this pattern! It's eligible for GISel emission; return
// it.
++NumPatternImported;
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(M);
Re-commit: [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
2017-08-17 09:26:14 +00:00
}
[globalisel][tablegen] Add support for (set $dst, 1) and test X86's OptForSize predicate. Summary: It's rare but a small number of patterns use IntInit's at the root of the match. On X86, one such rule is enabled by the OptForSize predicate and causes the compiler to use the smaller: %0 = MOV32r1 instead of the usual: %0 = MOV32ri 1 This patch adds support for matching IntInit's at the root and uses this as a test case for the optsize attribute that was implemented in r301750 Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: qcolombet Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32791 llvm-svn: 303678
2017-05-23 19:33:16 +00:00
return failedImport("Dst pattern root isn't a known leaf");
Re-commit: [globalisel][tablegen] Support zero-instruction emission. Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
2017-08-17 09:26:14 +00:00
}
[globalisel][tablegen] Add support for (set $dst, 1) and test X86's OptForSize predicate. Summary: It's rare but a small number of patterns use IntInit's at the root of the match. On X86, one such rule is enabled by the OptForSize predicate and causes the compiler to use the smaller: %0 = MOV32r1 instead of the usual: %0 = MOV32ri 1 This patch adds support for matching IntInit's at the root and uses this as a test case for the optsize attribute that was implemented in r301750 Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: qcolombet Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D32791 llvm-svn: 303678
2017-05-23 19:33:16 +00:00
[tablegen][globalisel] Add support for nested instruction matching. Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
2017-04-04 13:25:23 +00:00
// Start with the defined operands (i.e., the results of the root operator).
[TableGen] Change CodeGenInstruction record members to const (#107921) Change CodeGenInstruction::{TheDef, InfereredFrom} to const pointers. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-11 08:52:26 -07:00
const Record *DstOp = Dst.getOperator();
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
if (!DstOp->isSubClassOf("Instruction"))
return failedImport("Pattern operator isn't an instruction");
[globalisel][tblgen] Add support for ComplexPatterns Summary: Adds a new kind of MachineOperand: MO_Placeholder. This operand must not appear in the MIR and only exists as a way of creating an 'uninitialized' operand until a matcher function overwrites it. Depends on D30046, D29712 Reviewers: t.p.northover, ab, rovka, aditya_nandakumar, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D30089 llvm-svn: 297782
2017-03-14 21:32:08 +00:00
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
auto &DstI = Target.getInstruction(DstOp);
GlobalISel/TableGen: Don't skip REG_SEQUENCE based on patterns This partially adds support for patterns with REG_SEQUENCE. The source patterns are now accepted, but the pattern is still rejected due to missing support for the instruction renderer. llvm-svn: 370920
2019-09-04 16:19:34 +00:00
StringRef DstIName = DstI.TheDef->getName();
[llvm][TableGen] Count implicit defs as well as explicit ones in the GlobalISel TableGen emitter (#112673) `NumDefs` only counts the number of registers in `(outs)`, not any implicit defs specified with `Defs = [...]` This causes patterns with physical register defs to fail to import here instead of later where implicit defs are rendered. Add on `ImplicitDefs.size()` to count both and create `DstExpDefs` to count only explicit defs, used later on.
2024-10-18 05:50:44 -04:00
// Count both implicit and explicit defs in the dst instruction.
// This avoids errors importing patterns that have inherent implicit defs.
unsigned DstExpDefs = DstI.Operands.NumDefs,
DstNumDefs = DstI.ImplicitDefs.size() + DstExpDefs,
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
SrcNumDefs = Src.getExtTypes().size();
[GlobalISel][SelectionDAG] Implement the HasNoUse builtin predicate This change introduces the HasNoUse builtin predicate in PatFrags that checks for the absence of use of the first result operand. GlobalISelEmitter will allow source PatFrags with this predicate to be matched with destination instructions with empty outs. This predicate is required for selecting the no-return variant of atomic instructions in AMDGPU. Differential Revision: https://reviews.llvm.org/D125212
2022-05-08 21:24:52 +05:30
if (DstNumDefs < SrcNumDefs) {
if (DstNumDefs != 0)
return failedImport("Src pattern result has more defs than dst MI (" +
to_string(SrcNumDefs) + " def(s) vs " +
to_string(DstNumDefs) + " def(s))");
bool FoundNoUsePred = false;
for (const auto &Pred : InsnMatcher.predicates()) {
if ((FoundNoUsePred = isa<NoUsePredicateMatcher>(Pred.get())))
break;
}
if (!FoundNoUsePred)
return failedImport("Src pattern result has " + to_string(SrcNumDefs) +
" def(s) without the HasNoUse predicate set to true "
"but Dst MI has no def");
}
[globalisel] Decouple src pattern operands from dst pattern operands. Summary: This isn't testable for AArch64 by itself so this patch also adds support for constant immediates in the pattern and physical register uses in the result. The new IntOperandMatcher matches the constant in patterns such as '(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold immediates into an instruction so this is the first rule that will match across multiple BB's. The Renderer hierarchy is responsible for adding operands to the result instruction. Renderers can copy operands (CopyRenderer) or add physical registers (in particular %wzr and %xzr) to the result instruction in any order (OperandMatchers now import the operand names from SelectionDAG to allow renderers to access any operand). This allows us to emit the result instruction for: %1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0 %1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0 although the latter is untested since the matcher/importer has not been taught about commutativity yet. Added BuildMIAction which can build new instructions and mutate them where possible. W.r.t the mutation aspect, MatchActions are now told the name of an instruction they can recycle and BuildMIAction will emit mutation code when the renderers are appropriate. They are appropriate when all operands are rendered using CopyRenderer and the indices are the same as the matcher. This currently assumes that all operands have at least one matcher. Finally, this change also fixes a crash in AArch64InstructionSelector::select() caused by an immediate operand passing isImm() rather than isCImm(). This was uncovered by the other changes and was detected by existing tests. Depends on D29711 Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar Reviewed By: rovka Subscribers: aemerson, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29712 llvm-svn: 296131
2017-02-24 15:43:30 +00:00
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
// The root of the match also has constraints on the register bank so that it
// matches the result instruction.
unsigned OpIdx = 0;
[llvm][TableGen] Count implicit defs as well as explicit ones in the GlobalISel TableGen emitter (#112673) `NumDefs` only counts the number of registers in `(outs)`, not any implicit defs specified with `Defs = [...]` This causes patterns with physical register defs to fail to import here instead of later where implicit defs are rendered. Add on `ImplicitDefs.size()` to count both and create `DstExpDefs` to count only explicit defs, used later on.
2024-10-18 05:50:44 -04:00
unsigned N = std::min(DstExpDefs, SrcNumDefs);
[GlobalISel][SelectionDAG] Implement the HasNoUse builtin predicate This change introduces the HasNoUse builtin predicate in PatFrags that checks for the absence of use of the first result operand. GlobalISelEmitter will allow source PatFrags with this predicate to be matched with destination instructions with empty outs. This predicate is required for selecting the no-return variant of atomic instructions in AMDGPU. Differential Revision: https://reviews.llvm.org/D125212
2022-05-08 21:24:52 +05:30
for (unsigned I = 0; I < N; ++I) {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
const TypeSetByHwMode &VTy = Src.getExtType(I);
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
const auto &DstIOperand = DstI.Operands[OpIdx];
[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858) Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to const pointer. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-09 14:33:21 -07:00
PointerUnion<const Record *, const CodeGenRegisterClass *> MatchedRC =
[GISel][TableGen] Fix accidental operand name clashes in patterns (#74492) When importing instruction selection patterns into GlobalISel, the operands matched in the "source" DAG are copied into corresponding operands of the "destination" DAG according to their names (such as Rd). If multiple operands in the source DAG share the same name, a GIM_CheckIsSameOperand predicate makes instruction selector check the corresponding operands for equality (at compiler run-time) as part of matching the source pattern. The Def operands of the root node of the destination DAG are handled specially. The operands of the instruction corresponding to the root node are taken and GIM_CheckRegBankForClass predicates are tablegen-erated accordingly. If by coincidence the Def operand in question has the same name as one of the named operands in the pattern, a GIM_CheckIsSameOperand predicate is automatically added that is likely to prevent matching the source of otherwise applicable selection pattern at compiler run-time. This patch mangles the Def operand names taken from the instruction corresponding to the root of the destination DAG (for example, "Rd" becomes "DstI[Rd]") preventing unexpected name clashes with pattern's named operands. The patch consists of three sets of changes: * changes to the GlobalISelEmitter.cpp file are the actual fix * a test case is added to GlobalISelEmitter.td file as a regression test * everything else is the biggest and least interesting part - updates to the existing test cases: renames of the form Rd -> DstI[Rd] inside the inline comments in tablegen-erated code
2023-12-10 13:25:11 +03:00
DstIOperand.Rec;
GlobalISel/TableGen: Don't skip REG_SEQUENCE based on patterns This partially adds support for patterns with REG_SEQUENCE. The source patterns are now accepted, but the pattern is still rejected due to missing support for the instruction renderer. llvm-svn: 370920
2019-09-04 16:19:34 +00:00
if (DstIName == "COPY_TO_REGCLASS") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
MatchedRC = getInitValueAsRegClass(Dst.getChild(1).getLeafValue());
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
[GISel][TableGen] Fix accidental operand name clashes in patterns (#74492) When importing instruction selection patterns into GlobalISel, the operands matched in the "source" DAG are copied into corresponding operands of the "destination" DAG according to their names (such as Rd). If multiple operands in the source DAG share the same name, a GIM_CheckIsSameOperand predicate makes instruction selector check the corresponding operands for equality (at compiler run-time) as part of matching the source pattern. The Def operands of the root node of the destination DAG are handled specially. The operands of the instruction corresponding to the root node are taken and GIM_CheckRegBankForClass predicates are tablegen-erated accordingly. If by coincidence the Def operand in question has the same name as one of the named operands in the pattern, a GIM_CheckIsSameOperand predicate is automatically added that is likely to prevent matching the source of otherwise applicable selection pattern at compiler run-time. This patch mangles the Def operand names taken from the instruction corresponding to the root of the destination DAG (for example, "Rd" becomes "DstI[Rd]") preventing unexpected name clashes with pattern's named operands. The patch consists of three sets of changes: * changes to the GlobalISelEmitter.cpp file are the actual fix * a test case is added to GlobalISelEmitter.td file as a regression test * everything else is the biggest and least interesting part - updates to the existing test cases: renames of the form Rd -> DstI[Rd] inside the inline comments in tablegen-erated code
2023-12-10 13:25:11 +03:00
if (MatchedRC.isNull())
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
return failedImport(
"COPY_TO_REGCLASS operand #1 isn't a register class");
GlobalISel/TableGen: Don't skip REG_SEQUENCE based on patterns This partially adds support for patterns with REG_SEQUENCE. The source patterns are now accepted, but the pattern is still rejected due to missing support for the instruction renderer. llvm-svn: 370920
2019-09-04 16:19:34 +00:00
} else if (DstIName == "REG_SEQUENCE") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
MatchedRC = getInitValueAsRegClass(Dst.getChild(0).getLeafValue());
[GISel][TableGen] Fix accidental operand name clashes in patterns (#74492) When importing instruction selection patterns into GlobalISel, the operands matched in the "source" DAG are copied into corresponding operands of the "destination" DAG according to their names (such as Rd). If multiple operands in the source DAG share the same name, a GIM_CheckIsSameOperand predicate makes instruction selector check the corresponding operands for equality (at compiler run-time) as part of matching the source pattern. The Def operands of the root node of the destination DAG are handled specially. The operands of the instruction corresponding to the root node are taken and GIM_CheckRegBankForClass predicates are tablegen-erated accordingly. If by coincidence the Def operand in question has the same name as one of the named operands in the pattern, a GIM_CheckIsSameOperand predicate is automatically added that is likely to prevent matching the source of otherwise applicable selection pattern at compiler run-time. This patch mangles the Def operand names taken from the instruction corresponding to the root of the destination DAG (for example, "Rd" becomes "DstI[Rd]") preventing unexpected name clashes with pattern's named operands. The patch consists of three sets of changes: * changes to the GlobalISelEmitter.cpp file are the actual fix * a test case is added to GlobalISelEmitter.td file as a regression test * everything else is the biggest and least interesting part - updates to the existing test cases: renames of the form Rd -> DstI[Rd] inside the inline comments in tablegen-erated code
2023-12-10 13:25:11 +03:00
if (MatchedRC.isNull())
GlobalISel/TableGen: Don't skip REG_SEQUENCE based on patterns This partially adds support for patterns with REG_SEQUENCE. The source patterns are now accepted, but the pattern is still rejected due to missing support for the instruction renderer. llvm-svn: 370920
2019-09-04 16:19:34 +00:00
return failedImport("REG_SEQUENCE operand #0 isn't a register class");
} else if (DstIName == "EXTRACT_SUBREG") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
auto InferredClass = inferRegClassFromPattern(Dst.getChild(0));
TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG This previously only handled EXTRACT_SUBREGs from leafs, such as operands directly in the original output. Handle extracting from a result instruction.
2020-01-14 16:02:02 -05:00
if (!InferredClass)
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
return failedImport(
"Could not infer class for EXTRACT_SUBREG operand #0");
[globalisel][tablegen] Add support for EXTRACT_SUBREG. Summary: After this patch, we finally have test cases that require multiple instruction emission. Depends on D33590 Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D33596 llvm-svn: 306388
2017-06-27 10:11:39 +00:00
[globalisel][tablegen] Multiple 80-col corrections. llvm-svn: 306544
2017-06-28 13:50:04 +00:00
// We can assume that a subregister is in the same bank as it's super
// register.
[GISel][TableGen] Fix accidental operand name clashes in patterns (#74492) When importing instruction selection patterns into GlobalISel, the operands matched in the "source" DAG are copied into corresponding operands of the "destination" DAG according to their names (such as Rd). If multiple operands in the source DAG share the same name, a GIM_CheckIsSameOperand predicate makes instruction selector check the corresponding operands for equality (at compiler run-time) as part of matching the source pattern. The Def operands of the root node of the destination DAG are handled specially. The operands of the instruction corresponding to the root node are taken and GIM_CheckRegBankForClass predicates are tablegen-erated accordingly. If by coincidence the Def operand in question has the same name as one of the named operands in the pattern, a GIM_CheckIsSameOperand predicate is automatically added that is likely to prevent matching the source of otherwise applicable selection pattern at compiler run-time. This patch mangles the Def operand names taken from the instruction corresponding to the root of the destination DAG (for example, "Rd" becomes "DstI[Rd]") preventing unexpected name clashes with pattern's named operands. The patch consists of three sets of changes: * changes to the GlobalISelEmitter.cpp file are the actual fix * a test case is added to GlobalISelEmitter.td file as a regression test * everything else is the biggest and least interesting part - updates to the existing test cases: renames of the form Rd -> DstI[Rd] inside the inline comments in tablegen-erated code
2023-12-10 13:25:11 +03:00
MatchedRC = (*InferredClass)->getDef();
GlobalISel/TableGen: Don't skip REG_SEQUENCE based on patterns This partially adds support for patterns with REG_SEQUENCE. The source patterns are now accepted, but the pattern is still rejected due to missing support for the instruction renderer. llvm-svn: 370920
2019-09-04 16:19:34 +00:00
} else if (DstIName == "INSERT_SUBREG") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
auto MaybeSuperClass =
inferSuperRegisterClassForNode(VTy, Dst.getChild(0), Dst.getChild(2));
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
if (!MaybeSuperClass)
[globalisel][tablegen] Add support for EXTRACT_SUBREG. Summary: After this patch, we finally have test cases that require multiple instruction emission. Depends on D33590 Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls Subscribers: javed.absar, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D33596 llvm-svn: 306388
2017-06-27 10:11:39 +00:00
return failedImport(
Recommit "[GlobalISel] Import patterns containing INSERT_SUBREG" I thought `llvm::sort` was stable for some reason but it's not. Use `llvm::stable_sort` in `CodeGenTarget::getSuperRegForSubReg`. Original patch: https://reviews.llvm.org/D66498 llvm-svn: 370084
2019-08-27 17:47:06 +00:00
"Cannot infer register class for INSERT_SUBREG operand #0");
// Move to the next pattern here, because the register class we found
// doesn't necessarily have a record associated with it. So, we can't
// set DstIOpRec using this.
[GISel][TableGen] Fix accidental operand name clashes in patterns (#74492) When importing instruction selection patterns into GlobalISel, the operands matched in the "source" DAG are copied into corresponding operands of the "destination" DAG according to their names (such as Rd). If multiple operands in the source DAG share the same name, a GIM_CheckIsSameOperand predicate makes instruction selector check the corresponding operands for equality (at compiler run-time) as part of matching the source pattern. The Def operands of the root node of the destination DAG are handled specially. The operands of the instruction corresponding to the root node are taken and GIM_CheckRegBankForClass predicates are tablegen-erated accordingly. If by coincidence the Def operand in question has the same name as one of the named operands in the pattern, a GIM_CheckIsSameOperand predicate is automatically added that is likely to prevent matching the source of otherwise applicable selection pattern at compiler run-time. This patch mangles the Def operand names taken from the instruction corresponding to the root of the destination DAG (for example, "Rd" becomes "DstI[Rd]") preventing unexpected name clashes with pattern's named operands. The patch consists of three sets of changes: * changes to the GlobalISelEmitter.cpp file are the actual fix * a test case is added to GlobalISelEmitter.td file as a regression test * everything else is the biggest and least interesting part - updates to the existing test cases: renames of the form Rd -> DstI[Rd] inside the inline comments in tablegen-erated code
2023-12-10 13:25:11 +03:00
MatchedRC = *MaybeSuperClass;
GlobalISel/TableGen: Don't skip REG_SEQUENCE based on patterns This partially adds support for patterns with REG_SEQUENCE. The source patterns are now accepted, but the pattern is still rejected due to missing support for the instruction renderer. llvm-svn: 370920
2019-09-04 16:19:34 +00:00
} else if (DstIName == "SUBREG_TO_REG") {
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
auto MaybeRegClass = inferSuperRegisterClass(VTy, Dst.getChild(2));
[GlobalISel] Import patterns containing SUBREG_TO_REG Reuse the logic for INSERT_SUBREG to also import SUBREG_TO_REG patterns. - Split `inferSuperRegisterClass` into two functions, one which tries to use an existing TreePatternNode (`inferSuperRegisterClassForNode`), and one that doesn't. SUBREG_TO_REG doesn't have a node to leverage, which is the cause for the split. - Rename GlobalISelEmitterInsertSubreg.td to GlobalISelEmitterSubreg.td and update it. - Update impacted tests in the AArch64 and X86 backends. This is kind of a hit/miss for code size improvements/regressions. E.g. in add-ext.ll, we now get some identity copies. This isn't really anything the importer can handle, since it's caused by a later pass introducing the copy for the sake of correctness. Differential Revision: https://reviews.llvm.org/D66769 llvm-svn: 370254
2019-08-28 20:12:31 +00:00
if (!MaybeRegClass)
return failedImport(
"Cannot infer register class for SUBREG_TO_REG operand #0");
[GISel][TableGen] Fix accidental operand name clashes in patterns (#74492) When importing instruction selection patterns into GlobalISel, the operands matched in the "source" DAG are copied into corresponding operands of the "destination" DAG according to their names (such as Rd). If multiple operands in the source DAG share the same name, a GIM_CheckIsSameOperand predicate makes instruction selector check the corresponding operands for equality (at compiler run-time) as part of matching the source pattern. The Def operands of the root node of the destination DAG are handled specially. The operands of the instruction corresponding to the root node are taken and GIM_CheckRegBankForClass predicates are tablegen-erated accordingly. If by coincidence the Def operand in question has the same name as one of the named operands in the pattern, a GIM_CheckIsSameOperand predicate is automatically added that is likely to prevent matching the source of otherwise applicable selection pattern at compiler run-time. This patch mangles the Def operand names taken from the instruction corresponding to the root of the destination DAG (for example, "Rd" becomes "DstI[Rd]") preventing unexpected name clashes with pattern's named operands. The patch consists of three sets of changes: * changes to the GlobalISelEmitter.cpp file are the actual fix * a test case is added to GlobalISelEmitter.td file as a regression test * everything else is the biggest and least interesting part - updates to the existing test cases: renames of the form Rd -> DstI[Rd] inside the inline comments in tablegen-erated code
2023-12-10 13:25:11 +03:00
MatchedRC = *MaybeRegClass;
[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858) Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to const pointer. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-09 14:33:21 -07:00
} else if (MatchedRC.get<const Record *>()->isSubClassOf("RegisterOperand"))
MatchedRC = MatchedRC.get<const Record *>()->getValueAsDef("RegClass");
else if (!MatchedRC.get<const Record *>()->isSubClassOf("RegisterClass"))
[TableGen][NFC] convert TreePatternNode pointers to references (#81134) Almost all uses of `*TreePatternNode` expect it to be non-null. There was the occasional check that it wasn't, which I have removed. Making them references makes it clear that they exist. This was attempted in 2018 (1b465767d6ca69f4b7201503f5f21e6125fe049a) for `TreePatternNode::getChild()` but that was reverted.
2024-02-09 13:35:42 +00:00
return failedImport("Dst MI def isn't a register class" + to_string(Dst));
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
OperandMatcher &OM = InsnMatcher.getOperand(OpIdx);
[GISel][TableGen] Fix accidental operand name clashes in patterns (#74492) When importing instruction selection patterns into GlobalISel, the operands matched in the "source" DAG are copied into corresponding operands of the "destination" DAG according to their names (such as Rd). If multiple operands in the source DAG share the same name, a GIM_CheckIsSameOperand predicate makes instruction selector check the corresponding operands for equality (at compiler run-time) as part of matching the source pattern. The Def operands of the root node of the destination DAG are handled specially. The operands of the instruction corresponding to the root node are taken and GIM_CheckRegBankForClass predicates are tablegen-erated accordingly. If by coincidence the Def operand in question has the same name as one of the named operands in the pattern, a GIM_CheckIsSameOperand predicate is automatically added that is likely to prevent matching the source of otherwise applicable selection pattern at compiler run-time. This patch mangles the Def operand names taken from the instruction corresponding to the root of the destination DAG (for example, "Rd" becomes "DstI[Rd]") preventing unexpected name clashes with pattern's named operands. The patch consists of three sets of changes: * changes to the GlobalISelEmitter.cpp file are the actual fix * a test case is added to GlobalISelEmitter.td file as a regression test * everything else is the biggest and least interesting part - updates to the existing test cases: renames of the form Rd -> DstI[Rd] inside the inline comments in tablegen-erated code
2023-12-10 13:25:11 +03:00
// The operand names declared in the DstI instruction are unrelated to
// those used in pattern's source and destination DAGs, so mangle the
// former to prevent implicitly adding unexpected
// GIM_CheckIsSameOperand predicates by the defineOperand method.
OM.setSymbolicName(getMangledRootDefName(DstIOperand.Name));
[globalisel][tablegen] Simplify named operand/operator lookups and fix a wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
2017-10-14 00:31:58 +00:00
M.defineOperand(OM.getSymbolicName(), OM);
[TableGen] Change CGIOperandList::OperandInfo::Rec to const pointer (#107858) Change CGIOperandList::OperandInfo::Rec and CGIOperandList::TheDef to const pointer. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-09 14:33:21 -07:00
if (MatchedRC.is<const Record *>())
MatchedRC = &Target.getRegisterClass(MatchedRC.get<const Record *>());
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
OM.addPredicate<RegisterBankOperandMatcher>(
[GISel][TableGen] Fix accidental operand name clashes in patterns (#74492) When importing instruction selection patterns into GlobalISel, the operands matched in the "source" DAG are copied into corresponding operands of the "destination" DAG according to their names (such as Rd). If multiple operands in the source DAG share the same name, a GIM_CheckIsSameOperand predicate makes instruction selector check the corresponding operands for equality (at compiler run-time) as part of matching the source pattern. The Def operands of the root node of the destination DAG are handled specially. The operands of the instruction corresponding to the root node are taken and GIM_CheckRegBankForClass predicates are tablegen-erated accordingly. If by coincidence the Def operand in question has the same name as one of the named operands in the pattern, a GIM_CheckIsSameOperand predicate is automatically added that is likely to prevent matching the source of otherwise applicable selection pattern at compiler run-time. This patch mangles the Def operand names taken from the instruction corresponding to the root of the destination DAG (for example, "Rd" becomes "DstI[Rd]") preventing unexpected name clashes with pattern's named operands. The patch consists of three sets of changes: * changes to the GlobalISelEmitter.cpp file are the actual fix * a test case is added to GlobalISelEmitter.td file as a regression test * everything else is the biggest and least interesting part - updates to the existing test cases: renames of the form Rd -> DstI[Rd] inside the inline comments in tablegen-erated code
2023-12-10 13:25:11 +03:00
*MatchedRC.get<const CodeGenRegisterClass *>());
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
++OpIdx;
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
}
GlobalISel: Support physical register inputs in patterns llvm-svn: 371253
2019-09-06 20:32:37 +00:00
auto DstMIBuilderOrError =
createAndImportInstructionRenderer(M, InsnMatcher, Src, Dst);
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
if (auto Error = DstMIBuilderOrError.takeError())
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
BuildMIAction &DstMIBuilder = DstMIBuilderOrError.get();
// Render the implicit defs.
// These are only added to the root of the result.
[globalisel][tablegen] Change Expected<bool> to Error and rename functions. Functions that still return Expected<X> are now called createAndImport*() Changing the return type was requested in the review comments for r299001 llvm-svn: 299063
2017-03-30 09:36:33 +00:00
if (auto Error = importImplicitDefRenderers(DstMIBuilder, P.getDstRegs()))
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(Error);
[tablegen][globalisel] Convert the SelectionDAG importer to a tree walking approach. NFC Summary: But don't actually inspect the tree any deeper than we already do. This change is NFC but the next one will enable full traversal of the source/destination patterns. Depends on D30535 Reviewers: t.p.northover, qcolombet, aditya_nandakumar, rovka, ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30536 llvm-svn: 299001
2017-03-29 15:37:18 +00:00
[globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction to choose a mutatable instruction. NFC Prepare for multiple instruction emission by allowing BuildMIAction to search for a suitable matcher that will support mutation. This patch deliberately neglects to add matchers aside from the root to preserve NFC. That said, it should be noted that until we support mutations other than just the opcode the chances of finding a non-root instruction for which canMutate() is true, is essentially zero. Furthermore in the presence of multi-instruction emission the chances of finding any instruction for which canMutate() is true is also zero. Nevertheless, we can't continue to require that all BuildMIAction's consider the root of the match to be recyclable due to the risk of recycling it twice in the same rule. llvm-svn: 317022
2017-10-31 18:50:24 +00:00
DstMIBuilder.chooseInsnToMutate(M);
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
// Constrain the registers to classes. This is normally derived from the
// emitted instruction but a few instructions require special handling.
[TableGen][GISel] Extract helper function for constraining operands (#115148) As a side effect, this fixes COPY_TO_REGCLASS not being constrained if it is not top-level (the reason for changes in tests).
2024-11-07 07:16:54 +03:00
if (auto Error =
constrainOperands(M.actions_end(), M, DstMIBuilder.getInsnID(), Dst))
return std::move(Error);
TableGen/GlobalISel: Fix constraining REG_SEQUENCE operands This was hitting the default instruction constraint code which uses the register classes in the instruction def, which REG_SEQUENCE does not have. Fixes not constraining the register class for AMDGPU fneg/fabs patterns, which would fail when the use was another generic, unconstrained instruction. Another oddity I noticed is that the temporary registers are created with an unnecessary, but incorrect 16-bit LLT but this shouldn't matter. I'm also still unclear why root and sub-instructions have to be handled differently.
2020-04-07 09:32:51 -04:00
[GISel] Erase the root instruction after emitting all its potential uses (#77494) This tries to fix a bug by resolving a few FIXMEs. The bug is that `EraseInstAction` is emitted after emitting the _first_ `BuildMIAction`, which is too early because the erased instruction may still be used by subsequent `BuildMIAction`s (in particular, by `CopyRenderer`). An example of the bug (from `match-table-operand-types.td`): ``` def InstTest0 : GICombineRule< (defs root:$a), (match (G_MUL i32:$x, i32:$b, i32:$c), (G_MUL $a, i32:$b, i32:$x)), (apply (G_ADD i64:$tmp, $b, i32:$c), (G_ADD i8:$a, $b, i64:$tmp))>; GIR_EraseFromParent, /*InsnID*/0, GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, ``` Here, the root instruction is destroyed before copying its operands ('a' and 'b') to the new instruction. The solution is to emit `EraseInstAction` for the root instruction as the last action in the emission pipeline.
2024-01-13 11:17:41 +03:00
// Erase the root.
unsigned RootInsnID = M.getInsnVarID(InsnMatcher);
M.addAction<EraseInstAction>(RootInsnID);
[globalisel][tablegen] Add support for COPY_TO_REGCLASS. Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
2017-06-20 12:36:34 +00:00
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
// We're done with this pattern! It's eligible for GISel emission; return it.
[globalisel] Separate the SelectionDAG importer from the emitter. NFC Summary: In the near future the rules will be sorted between these two steps to ensure that more important rules are not prevented by less important ones. Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29709 llvm-svn: 295661
2017-02-20 14:31:27 +00:00
++NumPatternImported;
Revert "Remove redundant "std::move"s in return statements" The build failed with error: call to deleted constructor of 'llvm::Error' errors. This reverts commit 1c2241a7936bf85aa68aef94bd40c3ba77d8ddf2.
2020-02-10 07:06:45 -08:00
return std::move(M);
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
}
[GlobalISel][InstructionSelect] Refactoring buildMatchTable out, NFC to share it between the Instruction Selector in optimized and non-optimized modes both and the Testgen. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46097 llvm-svn: 331396
2018-05-02 20:08:14 +00:00
MatchTable
GlobalISelEmitter::buildMatchTable(MutableArrayRef<RuleMatcher> Rules,
[GlobalISel][InstructionSelect] Making Coverage Info generation optional on per-match table basis to make sure that Testgen always has access to coverage info even if the match table used by the selector itself is stripped off that information for performance reasons. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46098 llvm-svn: 331398
2018-05-02 20:15:11 +00:00
bool Optimize, bool WithCoverage) {
[GlobalISel][InstructionSelect] Refactoring buildMatchTable out, NFC to share it between the Instruction Selector in optimized and non-optimized modes both and the Testgen. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46097 llvm-svn: 331396
2018-05-02 20:08:14 +00:00
std::vector<Matcher *> InputRules;
for (Matcher &Rule : Rules)
InputRules.push_back(&Rule);
if (!Optimize)
[GlobalISel][InstructionSelect] Making Coverage Info generation optional on per-match table basis to make sure that Testgen always has access to coverage info even if the match table used by the selector itself is stripped off that information for performance reasons. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46098 llvm-svn: 331398
2018-05-02 20:15:11 +00:00
return MatchTable::buildTable(InputRules, WithCoverage);
[GlobalISel][InstructionSelect] Refactoring buildMatchTable out, NFC to share it between the Instruction Selector in optimized and non-optimized modes both and the Testgen. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46097 llvm-svn: 331396
2018-05-02 20:08:14 +00:00
[GlobalISel][InstructionSelect] Sorting MatchTable's first level by opcodes and num operands, perf patch 3 This patch continues a series of patches started by r332907 (reapplied as r332917) In this commit we start sorting the rules by the opcode first, and if the same, by the number of operands of the root instructions. This allows better grouping and safe as patterns with different opcodes are mutually exclusive. This is expected to decrease time GlobalISel spends in its InstructionSelect pass by roughly 18% for an -O0 build as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64. I'm also removing RuleMatcher::getFirstConditionAsRootType() function here and moving it to a later patch within the series as it's not used yet and was causing a warning on sanitizer-ppc64le-linux bot. Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333001
2018-05-22 16:54:27 +00:00
unsigned CurrentOrdering = 0;
StringMap<unsigned> OpcodeOrder;
for (RuleMatcher &Rule : Rules) {
const StringRef Opcode = Rule.getOpcode();
assert(!Opcode.empty() && "Didn't expect an undefined opcode");
if (OpcodeOrder.count(Opcode) == 0)
OpcodeOrder[Opcode] = CurrentOrdering++;
}
[llvm] Use llvm::stable_sort (NFC)
2021-01-13 19:14:42 -08:00
llvm::stable_sort(InputRules, [&OpcodeOrder](const Matcher *A,
const Matcher *B) {
auto *L = static_cast<const RuleMatcher *>(A);
auto *R = static_cast<const RuleMatcher *>(B);
[GlobalISel][TableGen] MIR Pattern Variadics (#100563) Allow for matching & rewriting a variable number of arguments in an instructions. Solves #87459
2024-08-01 08:30:20 +02:00
return std::tuple(OpcodeOrder[L->getOpcode()],
L->insnmatchers_front().getNumOperandMatchers()) <
std::tuple(OpcodeOrder[R->getOpcode()],
R->insnmatchers_front().getNumOperandMatchers());
[llvm] Use llvm::stable_sort (NFC)
2021-01-13 19:14:42 -08:00
});
[GlobalISel][InstructionSelect] Sorting MatchTable's first level by opcodes and num operands, perf patch 3 This patch continues a series of patches started by r332907 (reapplied as r332917) In this commit we start sorting the rules by the opcode first, and if the same, by the number of operands of the root instructions. This allows better grouping and safe as patterns with different opcodes are mutually exclusive. This is expected to decrease time GlobalISel spends in its InstructionSelect pass by roughly 18% for an -O0 build as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64. I'm also removing RuleMatcher::getFirstConditionAsRootType() function here and moving it to a later patch within the series as it's not used yet and was causing a warning on sanitizer-ppc64le-linux bot. Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333001
2018-05-22 16:54:27 +00:00
Reapply r332907 "[GlobalISel] Improving InstructionSelect's performance by reducing MatchTable..." Apparently the compile time problem was caused by the fact that not all compilers / STL implementations can automatically convert std::unique_ptr<Derived> to std::unique_ptr<Base>. Fixed (hopefully) by making sure it's std::unique_ptr<Derived>&& (rvalue ref) to std::unique_ptr<Base> conversion instead. llvm-svn: 332917
2018-05-21 23:28:51 +00:00
for (Matcher *Rule : InputRules)
Rule->optimize();
std::vector<std::unique_ptr<Matcher>> MatcherStorage;
[GlobalISel][InstructionSelect] Refactoring buildMatchTable out, NFC to share it between the Instruction Selector in optimized and non-optimized modes both and the Testgen. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46097 llvm-svn: 331396
2018-05-02 20:08:14 +00:00
std::vector<Matcher *> OptRules =
Reapply r332907 "[GlobalISel] Improving InstructionSelect's performance by reducing MatchTable..." Apparently the compile time problem was caused by the fact that not all compilers / STL implementations can automatically convert std::unique_ptr<Derived> to std::unique_ptr<Base>. Fixed (hopefully) by making sure it's std::unique_ptr<Derived>&& (rvalue ref) to std::unique_ptr<Base> conversion instead. llvm-svn: 332917
2018-05-21 23:28:51 +00:00
optimizeRules<GroupMatcher>(InputRules, MatcherStorage);
for (Matcher *Rule : OptRules)
Rule->optimize();
[GlobalISel][InstructionSelect] Refactoring buildMatchTable out, NFC to share it between the Instruction Selector in optimized and non-optimized modes both and the Testgen. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46097 llvm-svn: 331396
2018-05-02 20:08:14 +00:00
[GlobalISel][InstructionSelect] Switching MatchTable over opcodes, perf patch 4 This patch continues a series of patches started by r332907 (reapplied as r332917) In this commit we introduce a new matching opcode GIM_SwitchOpcode that implements a jump table over opcodes and start emitting them for root instructions. This is expected to decrease time GlobalISel spends in its InstructionSelect pass by roughly 20% for an -O0 build as measured on sqlite3-amalgamation (http://sqlite.org/download.html) targeting AArch64. To some degree, we assume here that the opcodes form a dense set, which is true at the moment for all upstream targets given the limitations of our rule importing mechanism. It might not be true for out of tree targets, specifically due to pseudo's. If so, we might noticeably increase the size of the MatchTable with this patch due to padding zeros. This will be addressed later. Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar Reviewed By: qcolombet Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44700 llvm-svn: 333017
2018-05-22 19:37:59 +00:00
OptRules = optimizeRules<SwitchMatcher>(OptRules, MatcherStorage);
[GlobalISel][InstructionSelect] Making Coverage Info generation optional on per-match table basis to make sure that Testgen always has access to coverage info even if the match table used by the selector itself is stripped off that information for performance reasons. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46098 llvm-svn: 331398
2018-05-02 20:15:11 +00:00
return MatchTable::buildTable(OptRules, WithCoverage);
[GlobalISel][InstructionSelect] Refactoring buildMatchTable out, NFC to share it between the Instruction Selector in optimized and non-optimized modes both and the Testgen. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46097 llvm-svn: 331396
2018-05-02 20:08:14 +00:00
}
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
void GlobalISelEmitter::emitAdditionalImpl(raw_ostream &OS) {
OS << "bool " << getClassName()
<< "::selectImpl(MachineInstr &I, CodeGenCoverage "
"&CoverageInfo) const {\n"
<< " const PredicateBitset AvailableFeatures = "
"getAvailableFeatures();\n"
[RFC][GlobalISel] Use Builders in MatchTable (#65955) The MatchTableExecutor did not use the MachineIRBuilder but instead created instructions ad-hoc. Making it use a Builder has the benefit that any observer added by a combine is now notified when instructions are created by MIR patterns. Another benefit is that it allows me to improve how constants are created in apply MIR patterns. `MachineIRBuilder::buildConstant` automatically handles splats for us, this means that we may change `addCImm` to use that and handle vector cases automatically.
2023-10-16 07:41:18 +02:00
<< " MachineIRBuilder B(I);\n"
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
<< " State.MIs.clear();\n"
<< " State.MIs.push_back(&I);\n\n"
[RFC][GlobalISel] Use Builders in MatchTable (#65955) The MatchTableExecutor did not use the MachineIRBuilder but instead created instructions ad-hoc. Making it use a Builder has the benefit that any observer added by a combine is now notified when instructions are created by MIR patterns. Another benefit is that it allows me to improve how constants are created in apply MIR patterns. `MachineIRBuilder::buildConstant` automatically handles splats for us, this means that we may change `addCImm` to use that and handle vector cases automatically.
2023-10-16 07:41:18 +02:00
<< " if (executeMatchTable(*this, State, ExecInfo, B"
[RFC][TableGen][GlobalISel] Add Combiner Match Table Backend Adds a new backend to power the GISel Combiners using the InstructionSelector's match tables. This does not depend on any of the data structures created for the current combiner and is intended to replace it entirely. See the RFC for more details: https://discourse.llvm.org/t/rfc-matchtable-based-globalisel-combiners/71457/6 Note: this would replace D141135. Reviewed By: aemerson, arsenm Differential Revision: https://reviews.llvm.org/D153757
2023-06-26 13:23:18 +02:00
<< ", getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures"
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
<< ", &CoverageInfo)) {\n"
<< " return true;\n"
<< " }\n\n"
<< " return false;\n"
<< "}\n\n";
}
void GlobalISelEmitter::emitMIPredicateFns(raw_ostream &OS) {
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
std::vector<const Record *> MatchedRecords;
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
std::copy_if(AllPatFrags.begin(), AllPatFrags.end(),
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
std::back_inserter(MatchedRecords), [](const Record *R) {
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
return !R->getValueAsString("GISelPredicateCode").empty();
});
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
emitMIPredicateFnsImpl<const Record *>(
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
OS,
" const MachineFunction &MF = *MI.getParent()->getParent();\n"
" const MachineRegisterInfo &MRI = MF.getRegInfo();\n"
" const auto &Operands = State.RecordedOperands;\n"
" (void)Operands;\n"
" (void)MRI;",
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
ArrayRef<const Record *>(MatchedRecords), &getPatFragPredicateEnumName,
[](const Record *R) { return R->getValueAsString("GISelPredicateCode"); },
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
"PatFrag predicates.");
}
void GlobalISelEmitter::emitI64ImmPredicateFns(raw_ostream &OS) {
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
std::vector<const Record *> MatchedRecords;
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
std::copy_if(AllPatFrags.begin(), AllPatFrags.end(),
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
std::back_inserter(MatchedRecords), [](const Record *R) {
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
bool Unset;
return !R->getValueAsString("ImmediateCode").empty() &&
!R->getValueAsBitOrUnset("IsAPFloat", Unset) &&
!R->getValueAsBit("IsAPInt");
});
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
emitImmPredicateFnsImpl<const Record *>(
OS, "I64", "int64_t", ArrayRef<const Record *>(MatchedRecords),
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
&getPatFragPredicateEnumName,
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
[](const Record *R) { return R->getValueAsString("ImmediateCode"); },
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
"PatFrag predicates.");
}
void GlobalISelEmitter::emitAPFloatImmPredicateFns(raw_ostream &OS) {
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
std::vector<const Record *> MatchedRecords;
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
std::copy_if(AllPatFrags.begin(), AllPatFrags.end(),
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
std::back_inserter(MatchedRecords), [](const Record *R) {
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
bool Unset;
return !R->getValueAsString("ImmediateCode").empty() &&
R->getValueAsBitOrUnset("IsAPFloat", Unset);
});
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
emitImmPredicateFnsImpl<const Record *>(
OS, "APFloat", "const APFloat &",
ArrayRef<const Record *>(MatchedRecords), &getPatFragPredicateEnumName,
[](const Record *R) { return R->getValueAsString("ImmediateCode"); },
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
"PatFrag predicates.");
}
void GlobalISelEmitter::emitAPIntImmPredicateFns(raw_ostream &OS) {
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
std::vector<const Record *> MatchedRecords;
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
std::copy_if(AllPatFrags.begin(), AllPatFrags.end(),
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
std::back_inserter(MatchedRecords), [](const Record *R) {
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
return !R->getValueAsString("ImmediateCode").empty() &&
R->getValueAsBit("IsAPInt");
});
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
emitImmPredicateFnsImpl<const Record *>(
OS, "APInt", "const APInt &", ArrayRef<const Record *>(MatchedRecords),
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
&getPatFragPredicateEnumName,
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
[](const Record *R) { return R->getValueAsString("ImmediateCode"); },
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
"PatFrag predicates.");
}
[RFC][TableGen][GlobalISel] Add Combiner Match Table Backend Adds a new backend to power the GISel Combiners using the InstructionSelector's match tables. This does not depend on any of the data structures created for the current combiner and is intended to replace it entirely. See the RFC for more details: https://discourse.llvm.org/t/rfc-matchtable-based-globalisel-combiners/71457/6 Note: this would replace D141135. Reviewed By: aemerson, arsenm Differential Revision: https://reviews.llvm.org/D153757
2023-06-26 13:23:18 +02:00
void GlobalISelEmitter::emitTestSimplePredicate(raw_ostream &OS) {
OS << "bool " << getClassName() << "::testSimplePredicate(unsigned) const {\n"
<< " llvm_unreachable(\"" + getClassName() +
" does not support simple predicates!\");\n"
<< " return false;\n"
<< "}\n";
}
void GlobalISelEmitter::emitRunCustomAction(raw_ostream &OS) {
[GlobalISel] Refactor Combiner MatchData & Apply C++ Code Handling (#92239) Combiners that use C++ code in their "apply" pattern only use that. They never mix it with MIR patterns as that has little added value. This patch restricts C++ apply code so that if C++ is used, we cannot use MIR patterns or builtins with it. Adding this restriction allows us to merge calls to match and apply C++ code together, which in turns makes it so we can just have MatchData variables on the stack. So before, we would have ``` GIM_CheckCxxInsnPredicate // match GIM_CheckCxxInsnPredicate // apply GIR_Done ``` Alongside a massive C++ struct holding the MatchData of all rules possible (which was a big space/perf issue). Now we just have ``` GIR_DoneWithCustomAction ``` And the function being ran just does ``` unsigned SomeMatchData; if (match(SomeMatchData)) apply(SomeMatchData) ``` This approach solves multiple issues in one: - MatchData handling is greatly simplified and more efficient, "don't pay for what you don't use" - We reduce the size of the match table - Calling C++ code has a certain overhead (we need a switch), and this overhead is only paid once now. Handling of C++ code inside PatFrags is unchanged though, that still emits a `GIM_CheckCxxInsnPredicate`. This is completely fine as they can't use MatchDatas.
2024-05-16 13:39:00 +02:00
OS << "bool " << getClassName()
[RFC][GlobalISel] Overhauled MIR Patterns Support for Combiners See https://discourse.llvm.org/t/rfc-overhauled-mir-patterns-for-globalisel-combiners/72264 This is a complete overrhaul of the recently-added GlobalISel Match Table backend which adds support for MIR patterns for both match and apply patterns. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D156315
2023-07-25 13:45:18 +02:00
<< "::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const "
"{\n"
[RFC][TableGen][GlobalISel] Add Combiner Match Table Backend Adds a new backend to power the GISel Combiners using the InstructionSelector's match tables. This does not depend on any of the data structures created for the current combiner and is intended to replace it entirely. See the RFC for more details: https://discourse.llvm.org/t/rfc-matchtable-based-globalisel-combiners/71457/6 Note: this would replace D141135. Reviewed By: aemerson, arsenm Differential Revision: https://reviews.llvm.org/D153757
2023-06-26 13:23:18 +02:00
<< " llvm_unreachable(\"" + getClassName() +
" does not support custom C++ actions!\");\n"
<< "}\n";
}
[GlobalISel] Add dead flags to implicit defs in ISel Checks for implicit defs that are unused within a pattern and mark them as dead. This is done directly at the TableGen level forr efficiency. The instructions are directly created with the "dead" operand and no further analysis is needed later. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D157273
2023-08-07 12:59:24 +02:00
void GlobalISelEmitter::postProcessRule(RuleMatcher &M) {
[LLVM][TableGen] Change InstrInfoEmitter to use const RecordKeeper (#109189) Change InstrInfoEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-18 22:27:26 -07:00
SmallPtrSet<const Record *, 16> UsedRegs;
[GlobalISel] Add dead flags to implicit defs in ISel Checks for implicit defs that are unused within a pattern and mark them as dead. This is done directly at the TableGen level forr efficiency. The instructions are directly created with the "dead" operand and no further analysis is needed later. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D157273
2023-08-07 12:59:24 +02:00
// TODO: deal with subregs?
for (auto &A : M.actions()) {
auto *MI = dyn_cast<BuildMIAction>(A.get());
if (!MI)
continue;
for (auto *Use : MI->getCGI()->ImplicitUses)
UsedRegs.insert(Use);
}
for (auto &A : M.actions()) {
auto *MI = dyn_cast<BuildMIAction>(A.get());
if (!MI)
continue;
for (auto *Def : MI->getCGI()->ImplicitDefs) {
if (!UsedRegs.contains(Def))
MI->setDeadImplicitDef(Def);
}
}
}
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
void GlobalISelEmitter::run(raw_ostream &OS) {
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
2017-11-16 00:46:35 +00:00
if (!UseCoverageFile.empty()) {
RuleCoverage = CodeGenCoverage();
auto RuleCoverageBufOrErr = MemoryBuffer::getFile(UseCoverageFile);
if (!RuleCoverageBufOrErr) {
PrintWarning(SMLoc(), "Missing rule coverage data");
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
RuleCoverage = std::nullopt;
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
2017-11-16 00:46:35 +00:00
} else {
if (!RuleCoverage->parse(*RuleCoverageBufOrErr.get(), Target.getName())) {
PrintWarning(SMLoc(), "Ignoring invalid or missing rule coverage data");
[utils] Use std::nullopt instead of None (NFC) This patch mechanically replaces None with std::nullopt where the compiler would warn if None were deprecated. The intent is to reduce the amount of manual work required in migrating from Optional to std::optional. This is part of an effort to migrate from llvm::Optional to std::optional: https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
2022-12-02 21:11:42 -08:00
RuleCoverage = std::nullopt;
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
2017-11-16 00:46:35 +00:00
}
}
}
Reapply r332907 "[GlobalISel] Improving InstructionSelect's performance by reducing MatchTable..." Apparently the compile time problem was caused by the fact that not all compilers / STL implementations can automatically convert std::unique_ptr<Derived> to std::unique_ptr<Base>. Fixed (hopefully) by making sure it's std::unique_ptr<Derived>&& (rvalue ref) to std::unique_ptr<Base> conversion instead. llvm-svn: 332917
2018-05-21 23:28:51 +00:00
// Track the run-time opcode values
gatherOpcodeValues();
// Track the run-time LLT ID values
gatherTypeIDValues();
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
// Track the GINodeEquiv definitions.
gatherNodeEquivs();
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
AllPatFrags = RK.getAllDerivedDefinitions("PatFrags");
[NFC] clang-format GlobalISelEmitter.cpp It was overdue for a clang-format run, and it avoids unrelated formatting changes sneaking into diffs.
2023-06-23 11:42:51 +02:00
emitSourceFileHeader(
("Global Instruction Selector for the " + Target.getName() + " target")
.str(),
OS);
[globalisel] Separate the SelectionDAG importer from the emitter. NFC Summary: In the near future the rules will be sorted between these two steps to ensure that more important rules are not prevented by less important ones. Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29709 llvm-svn: 295661
2017-02-20 14:31:27 +00:00
std::vector<RuleMatcher> Rules;
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
// Look through the SelectionDAG patterns we found, possibly emitting some.
for (const PatternToMatch &Pat : CGP.ptms()) {
++NumPatternTotal;
[globalisel][tablegen] Import signextload and zeroextload. Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to correct situations where SelectionDAG and GlobalISel disagree on representation. For example, it would rewrite: (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16> to: (sext:i32 (load:i16 $ptr)<<unindexedload>>) I'd have preferred to replace the fragments and have the expansion happen naturally as part of PatFrag expansion but the type inferencing system can't cope with loads of types narrower than those mentioned in register classes. This is because the SDTCisInt's on the sext constrain both the result and operand to the 'legal' integer types (where legal is defined as 'a register class can contain the type') which immediately rules the narrower types out. Several targets (those with only one legal integer type) would then go on to crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types for the result of the extend. Also, improve isObviouslySafeToFold() slightly to automatically return true for neighbouring instructions. There can't be any re-ordering problems if re-ordering isn't happenning. We'll need to improve it further to handle sign/zero-extending loads when the extend and load aren't immediate neighbours though. llvm-svn: 317971
2017-11-11 03:23:44 +00:00
[TableGen] ShouldIgnore Pattern bit to disable DAG pattern imports during GISel (#88382) Added GISelShouldIgnore property to class Pattern in TargetSelectionDAG.td; it's similar to FastISelShouldIgnore. This bit can be put on a record to avoid its pattern import within GlobalISelEmitter. This allows one to avoid the record's GISel .td implementation, .inc generation, and any skipped pattern warnings from -warn-on-skipped-patterns.
2024-04-25 13:42:48 -07:00
if (Pat.getGISelShouldIgnore())
continue; // skip without warning
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
auto MatcherOrErr = runOnPattern(Pat);
// The pattern analysis can fail, indicating an unsupported pattern.
// Report that if we've been asked to do so.
if (auto Err = MatcherOrErr.takeError()) {
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
if (WarnOnSkippedPatterns) {
PrintWarning(Pat.getSrcRecord()->getLoc(),
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
"Skipped pattern: " + toString(std::move(Err)));
} else {
consumeError(std::move(Err));
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
}
[globalisel] Separate the SelectionDAG importer from the emitter. NFC Summary: In the near future the rules will be sorted between these two steps to ensure that more important rules are not prevented by less important ones. Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29709 llvm-svn: 295661
2017-02-20 14:31:27 +00:00
++NumPatternImportsSkipped;
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
continue;
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
}
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
2017-11-16 00:46:35 +00:00
if (RuleCoverage) {
if (RuleCoverage->isCovered(MatcherOrErr->getRuleID()))
++NumPatternsTested;
else
PrintWarning(Pat.getSrcRecord()->getLoc(),
"Pattern is not covered by a test");
}
[globalisel] Separate the SelectionDAG importer from the emitter. NFC Summary: In the near future the rules will be sorted between these two steps to ensure that more important rules are not prevented by less important ones. Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29709 llvm-svn: 295661
2017-02-20 14:31:27 +00:00
Rules.push_back(std::move(MatcherOrErr.get()));
[GlobalISel] Add dead flags to implicit defs in ISel Checks for implicit defs that are unused within a pattern and mark them as dead. This is done directly at the TableGen level forr efficiency. The instructions are directly created with the "dead" operand and no further analysis is needed later. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D157273
2023-08-07 12:59:24 +02:00
postProcessRule(Rules.back());
[globalisel] Separate the SelectionDAG importer from the emitter. NFC Summary: In the near future the rules will be sorted between these two steps to ensure that more important rules are not prevented by less important ones. Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29709 llvm-svn: 295661
2017-02-20 14:31:27 +00:00
}
[GlobalISel][TableGen] Add support for SDNodeXForm Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
2018-01-16 18:44:05 +00:00
// Comparison function to order records by name.
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
auto OrderByName = [](const Record *A, const Record *B) {
[GlobalISel][TableGen] Add support for SDNodeXForm Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
2018-01-16 18:44:05 +00:00
return A->getName() < B->getName();
};
[LLVM][TableGen] Change GlobalISelEmitter to use const RecordKeeper (#110109) Change GlobalISelEmitter to use const RecordKeeper. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-30 06:37:36 -07:00
std::vector<const Record *> ComplexPredicates =
[globalisel][tablegen] Partially fix compile-time regressions by converting matcher to state-machine(s) Summary: Replace the matcher if-statements for each rule with a state-machine. This significantly reduces compile time, memory allocations, and cumulative memory allocation when compiling AArch64InstructionSelector.cpp.o after r303259 is recommitted. The following patches will expand on this further to fully fix the regressions. Reviewers: rovka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: vitalybuka, aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33758 llvm-svn: 307079
2017-07-04 14:35:06 +00:00
RK.getAllDerivedDefinitions("GIComplexOperandMatcher");
[TableGen][GISel][NFC] clang-tidy GlobalISelEmitter.cpp (#90492) Fixes a couple of style issues, such as: - unused includes - variable naming - `else if` after `return`
2024-04-29 14:47:46 -04:00
llvm::sort(ComplexPredicates, OrderByName);
[GlobalISel][TableGen] Add support for SDNodeXForm Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
2018-01-16 18:44:05 +00:00
[TableGen][GlobalISel] Allow duplicate RendererFns Allow different GICustomOperandRenderers to use the same RendererFn. This avoids the need for targets to define a bunch of identical C++ renderer functions with different names. Without this fix TableGen would have emitted code that tried to define the GICR enumeration with duplicate enumerators. Differential Revision: https://reviews.llvm.org/D96587
2020-08-27 16:15:33 +01:00
std::vector<StringRef> CustomRendererFns;
transform(RK.getAllDerivedDefinitions("GICustomOperandRenderer"),
std::back_inserter(CustomRendererFns), [](const auto &Record) {
return Record->getValueAsString("RendererFn");
});
// Sort and remove duplicates to get a list of unique renderer functions, in
// case some were mentioned more than once.
llvm::sort(CustomRendererFns);
[TableGen] Use llvm::unique (NFC) (#94163)
2024-06-02 11:52:12 -07:00
CustomRendererFns.erase(llvm::unique(CustomRendererFns),
CustomRendererFns.end());
[GlobalISel][TableGen] Add support for SDNodeXForm Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
2018-01-16 18:44:05 +00:00
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
// Create a table containing the LLT objects needed by the matcher and an enum
[globalisel][tablegen] Partially fix compile-time regressions by converting matcher to state-machine(s) Summary: Replace the matcher if-statements for each rule with a state-machine. This significantly reduces compile time, memory allocations, and cumulative memory allocation when compiling AArch64InstructionSelector.cpp.o after r303259 is recommitted. The following patches will expand on this further to fully fix the regressions. Reviewers: rovka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: vitalybuka, aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33758 llvm-svn: 307079
2017-07-04 14:35:06 +00:00
// for the matcher to reference them with.
[globalisel][tablegen] Generate TypeObject table. NFC Summary: Generate the type table from the types used by a target rather than hard-coding the union of types used by all targets. Depends on D36084 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36085 llvm-svn: 311084
2017-08-17 13:18:35 +00:00
std::vector<LLTCodeGen> TypeObjects;
[TableGen] Use llvm::append_range (NFC)
2021-01-25 19:23:57 -08:00
append_range(TypeObjects, KnownTypes);
llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) Summary: The convenience wrapper in STLExtras is available since rL342102. Reviewers: dblaikie, javed.absar, JDevlieghere, andreadb Subscribers: MatzeB, sanjoy, arsenm, dschuff, mehdi_amini, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, javed.absar, gbedwell, jrtc27, mgrang, atanasyan, steven_wu, george.burgess.iv, dexonsmith, kristina, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D52573 llvm-svn: 343163
2018-09-27 02:13:45 +00:00
llvm::sort(TypeObjects);
[GlobalISel][TableGen] Add support for SDNodeXForm Summary: This patch adds CustomRenderer which renders the matched operands to the specified instruction. Targets can enable the matching of SDNodeXForm by adding a definition that inherits from GICustomOperandRenderer and GISDNodeXFormEquiv as follows. def gi_imm8 : GICustomOperandRenderer<"renderImm8”>, GISDNodeXFormEquiv<imm8_xform>; Custom renderer functions should be of the form: void render(MachineInstrBuilder &MIB, const MachineInstr &I); Reviewers: dsanders, ab, rovka Reviewed By: dsanders Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet Differential Revision: https://reviews.llvm.org/D42012 llvm-svn: 322582
2018-01-16 18:44:05 +00:00
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
// Sort rules.
Use llvm::stable_sort While touching the code, simplify if feasible. llvm-svn: 358996
2019-04-23 14:51:27 +00:00
llvm::stable_sort(Rules, [&](const RuleMatcher &A, const RuleMatcher &B) {
[GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAG This patch changes GlobalISelEmitter to rank patterns similar to how the DAG does it (ie it computes a score for a pattern and adds the added complexity to it). This is so that the decision tree for GISelSelector remains compatible with that of SelectionDAG. https://reviews.llvm.org/D43270 llvm-svn: 325401
2018-02-16 22:37:15 +00:00
int ScoreA = RuleMatcherScores[A.getRuleID()];
int ScoreB = RuleMatcherScores[B.getRuleID()];
if (ScoreA > ScoreB)
return true;
if (ScoreB > ScoreA)
return false;
[TableGen][GlobalISel] Optimize MatchTable for faster instruction selection *** Context *** Prior to this patchw, the table generated for matching instruction was straight forward but highly inefficient. Basically, each pattern generates its own set of self contained checks and actions. E.g., TableGen generated: // First pattern CheckNumOperand 3 CheckOpcode G_ADD ... Build ADDrr // Second pattern CheckNumOperand 3 CheckOpcode G_ADD ... Build ADDri // Third pattern CheckNumOperand 3 CheckOpcode G_SUB ... Build SUBrr *** Problem *** Because of that generation, a *lot* of check were redundant between each pattern and were checked every single time until we reach the pattern that matches. E.g., Taking the previous table, let say we are matching a G_SUB, that means we were going to check all the rules for G_ADD before looking at the G_SUB rule. In particular we are going to do: check 3 operands; PASS check G_ADD; FAIL ; Next rule check 3 operands; PASS (but we already knew that!) check G_ADD; FAIL (well it is still not true) ; Next rule check 3 operands; PASS (really!!) check G_SUB; PASS (at last :P) *** Proposed Solution *** This patch introduces a concept of group of rules (GroupMatcher) that share some predicates and only get checked once for the whole group. This patch only creates groups with one nesting level. Conceptually there is nothing preventing us for having deeper nest level. However, the current implementation is not smart enough to share the recording (aka capturing) of values. That limits its ability to do more sharing. For the given example the current patch will generate: // First group CheckOpcode G_ADD // First pattern CheckNumOperand 3 ... Build ADDrr // Second pattern CheckNumOperand 3 ... Build ADDri // Second group CheckOpcode G_SUB // Third pattern CheckNumOperand 3 ... Build SUBrr But if we allowed several nesting level, it could create a sub group for the checknumoperand 3. (We would need to call optimizeRules on the rules within a group.) *** Result *** With only one level of nesting, the instruction selection pass is up to 4x faster. For instance, one instruction now takes 500 checks, instead of 24k! With more nesting we could get in the tens I believe. Differential Revision: https://reviews.llvm.org/D39034 rdar://problem/34670699 llvm-svn: 321017
2017-12-18 19:47:41 +00:00
if (A.isHigherPriorityThan(B)) {
assert(!B.isHigherPriorityThan(A) && "Cannot be more important "
"and less important at "
"the same time");
return true;
}
return false;
});
[GlobalISel][InstructionSelect] Refactoring out a getMatchTable virtual method + other small NFC's The main goal is to share getMatchTable between the Instruction Selector and the Testgen. The commit also contains some NFC only loosely related to refactoring out the getMatchTable, but strongly related to the initial Testgen patch (see https://reviews.llvm.org/D43962) Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46096 llvm-svn: 331395
2018-05-02 20:07:15 +00:00
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
unsigned MaxTemporaries = 0;
for (const auto &Rule : Rules)
MaxTemporaries = std::max(MaxTemporaries, Rule.countRendererFns());
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
// Build match table
[GlobalISel][InstructionSelect] Making Coverage Info generation optional on per-match table basis to make sure that Testgen always has access to coverage info even if the match table used by the selector itself is stripped off that information for performance reasons. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46098 llvm-svn: 331398
2018-05-02 20:15:11 +00:00
const MatchTable Table =
buildMatchTable(Rules, OptimizeMatchTable, GenerateCoverage);
[TableGen][GlobalISel] Add Generic MatchTableExecutor Emitter Move all of the reusable logic out of `GlobalISelEmitter.cpp` into a `GlobalISelMatchTableExecutorEmitter` class so the future combiner backend can use it as well. Depends on D153755 Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D153756
2023-06-26 11:44:18 +02:00
emitPredicateBitset(OS, "GET_GLOBALISEL_PREDICATE_BITSET");
emitTemporariesDecl(OS, "GET_GLOBALISEL_TEMPORARIES_DECL");
emitTemporariesInit(OS, MaxTemporaries, "GET_GLOBALISEL_TEMPORARIES_INIT");
emitExecutorImpl(OS, Table, TypeObjects, Rules, ComplexPredicates,
CustomRendererFns, "GET_GLOBALISEL_IMPL");
emitPredicatesDecl(OS, "GET_GLOBALISEL_PREDICATES_DECL");
emitPredicatesInit(OS, "GET_GLOBALISEL_PREDICATES_INIT");
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
}
[LLVM][TableGen] Use const record pointers in TableGen/Common files (#109467) Use const record pointers in TableGen/Common files. This is a part of effort to have better const correctness in TableGen backends: https://discourse.llvm.org/t/psa-planned-changes-to-tablegen-getallderiveddefinitions-api-potential-downstream-breakages/81089
2024-09-23 13:07:31 -07:00
void GlobalISelEmitter::declareSubtargetFeature(const Record *Predicate) {
[TableGen] Use std::map::try_emplace to simplify code in GlobalISelEmitter. NFC
2023-08-22 10:09:48 -07:00
SubtargetFeatures.try_emplace(Predicate, Predicate, SubtargetFeatures.size());
[globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule. Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300993
2017-04-21 15:59:56 +00:00
}
[GlobalISel][RISCV][TableGen] Teach GlobalISelEmitter about HwMode. Similar to SelectionDAG, this patch treats HwMode as an additional predicate that needs to be satisfied for GIM_CheckFeatures. The existing predicate passes around Record * that point to predicate records. While HwMode expansion creates a string that needs to be checked. Each HwMode predicate string is uniqued by a new map that assigns it an index. Each Rule stores the index, or -1 if HwMode doesn't apply. The HwMode indices each create a new Predicate feature bit and the check string from the HwMode is used to set the feature bit. GIM_CheckFeatures is emitted when the rule has Predicates or the HwModeIdx is not -1. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D158660
2023-08-23 21:04:28 -07:00
unsigned GlobalISelEmitter::declareHwModeCheck(StringRef HwModeFeatures) {
return HwModes.emplace(HwModeFeatures.str(), HwModes.size()).first->second;
}
[GlobalISel] Return an Expected<RuleMatcher> for each SDAG pattern. NFC. Instead of emitting the matcher code directly, return the rule matcher and the skip reason as an Expected<RuleMatcher>. This will let us record all matchers and process them before emission. It's a somewhat unconventional use of Error, but it's nicer than, say, std::pair, because of the bool conversions. Differential Revision: https://reviews.llvm.org/D29743 llvm-svn: 294706
2017-02-10 04:00:17 +00:00
} // end anonymous namespace
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-21 23:26:20 +00:00
//===----------------------------------------------------------------------===//
llvm-tblgen: Rewrite emitters to use `TableGen::Emitter` Each emitter became self-contained since it has the registration of option. Differential Revision: https://reviews.llvm.org/D144351
2023-02-19 14:30:14 +09:00
static TableGen::Emitter::OptClass<GlobalISelEmitter>
X("gen-global-isel", "Generate GlobalISel selector");
Reference in New Issue Copy Permalink