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llvm-project/llvm/docs/AMDGPU/gfx10_vdst_5ec176.rst

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[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
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[AMDGPU][GFX10][DOC][NFC] Update assembler syntax description Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900). - Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements.
2022-12-13 14:36:43 +03:00
.. _amdgpu_synid_gfx10_vdst_5ec176:
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
vdst
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 17:16:22 +03:00
====
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
[AMDGPU][GFX10][DOC][NFC] Update assembler syntax description Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900). - Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements.
2022-12-13 14:36:43 +03:00
Image data to be loaded by an *image_gather4* instruction.
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
[AMDGPU][GFX10][DOC][NFC] Update assembler syntax description Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900). - Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements.
2022-12-13 14:36:43 +03:00
*Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16<amdgpu_synid_d16>`.
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
[AMDGPU][GFX10][DOC][NFC] Update assembler syntax description Summary of changes: - Update MUBUF lds syntax (see https://reviews.llvm.org/D124485). - Add v_cvt_pkrtz_f16_f32_dpp, v_cvt_pkrtz_f16_f32_sdwa. - Update SMEM syntax (see https://reviews.llvm.org/D127314). - Enable op_sel for v_add_nc_u16, v_sub_nc_u16 (see https://reviews.llvm.org/D123594). - Minor bug fixing and improvements.
2022-06-27 19:49:44 +03:00
:ref:`d16<amdgpu_synid_d16>` affects operand size as follows:
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
[AMDGPU][GFX10][DOC][NFC] Update assembler syntax description Summary of changes: - Update MUBUF lds syntax (see https://reviews.llvm.org/D124485). - Add v_cvt_pkrtz_f16_f32_dpp, v_cvt_pkrtz_f16_f32_sdwa. - Update SMEM syntax (see https://reviews.llvm.org/D127314). - Enable op_sel for v_add_nc_u16, v_sub_nc_u16 (see https://reviews.llvm.org/D123594). - Minor bug fixing and improvements.
2022-06-27 19:49:44 +03:00
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
*Operands:* :ref:`v<amdgpu_synid_v>`
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