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llvm-project/llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll

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[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s
define i16 @SEXTParam(i16 signext %0) #0 {
; CHECK-LABEL: SEXTParam:
; CHECK: # %bb.0: # %top
; CHECK-NEXT: li 4, 0
; CHECK-NEXT: sth 4, -4(1)
; CHECK-NEXT: addi 4, 1, -4
; CHECK-NEXT: lwsync
; CHECK-NEXT: .LBB0_1: # %top
; CHECK-NEXT: #
; CHECK-NEXT: lharx 5, 0, 4
; CHECK-NEXT: extsh 5, 5
[PowerPC] Fix a number of inefficiencies and issues with atomic code gen There are a few issues with the code we generate for atomic operations and the way we generate it: - Hard coded CR0 for compares - Order of operands for compares not conducive to emitting compare-immediate or for CSE of compares - Missing MachineMemOperand for st[bhwd]cx intrinsics - Missing intrinsic properties for the same - Unnecessary blocks with store conditional instructions to clear reservation (which ends up hindering performance) - Move from CR instructions just to compare the result of a store conditional with zero (even though it is a record-form) This patch aims to resolve all of those issues. Differential revision: https://reviews.llvm.org/D134783
2022-10-03 19:55:05 -05:00
; CHECK-NEXT: cmpw 5, 3
; CHECK-NEXT: blt 0, .LBB0_3
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
; CHECK-NEXT: # %bb.2: # %top
; CHECK-NEXT: #
; CHECK-NEXT: sthcx. 3, 0, 4
; CHECK-NEXT: bne 0, .LBB0_1
; CHECK-NEXT: .LBB0_3: # %top
; CHECK-NEXT: lwsync
; CHECK-NEXT: lhz 3, -4(1)
; CHECK-NEXT: cmpd 7, 3, 3
; CHECK-NEXT: bne- 7, .+4
; CHECK-NEXT: isync
; CHECK-NEXT: blr
top:
%1 = alloca i16, align 4
[PPC] Opaque pointer migration, part 2. The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
2022-10-07 18:34:40 +00:00
store i16 0, ptr %1, align 4
%rv.i = atomicrmw min ptr %1, i16 %0 acq_rel
%rv.i2 = load atomic i16, ptr %1 acquire, align 16
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
ret i16 %rv.i2
}
define i16 @noSEXTParam(i16 %0) #0 {
; CHECK-LABEL: noSEXTParam:
; CHECK: # %bb.0: # %top
; CHECK-NEXT: li 4, 0
; CHECK-NEXT: extsh 3, 3
; CHECK-NEXT: sth 4, -4(1)
; CHECK-NEXT: addi 4, 1, -4
; CHECK-NEXT: lwsync
; CHECK-NEXT: .LBB1_1: # %top
; CHECK-NEXT: #
; CHECK-NEXT: lharx 5, 0, 4
; CHECK-NEXT: extsh 5, 5
[PowerPC] Fix a number of inefficiencies and issues with atomic code gen There are a few issues with the code we generate for atomic operations and the way we generate it: - Hard coded CR0 for compares - Order of operands for compares not conducive to emitting compare-immediate or for CSE of compares - Missing MachineMemOperand for st[bhwd]cx intrinsics - Missing intrinsic properties for the same - Unnecessary blocks with store conditional instructions to clear reservation (which ends up hindering performance) - Move from CR instructions just to compare the result of a store conditional with zero (even though it is a record-form) This patch aims to resolve all of those issues. Differential revision: https://reviews.llvm.org/D134783
2022-10-03 19:55:05 -05:00
; CHECK-NEXT: cmpw 5, 3
; CHECK-NEXT: blt 0, .LBB1_3
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
; CHECK-NEXT: # %bb.2: # %top
; CHECK-NEXT: #
; CHECK-NEXT: sthcx. 3, 0, 4
; CHECK-NEXT: bne 0, .LBB1_1
; CHECK-NEXT: .LBB1_3: # %top
; CHECK-NEXT: lwsync
; CHECK-NEXT: lhz 3, -4(1)
; CHECK-NEXT: cmpd 7, 3, 3
; CHECK-NEXT: bne- 7, .+4
; CHECK-NEXT: isync
; CHECK-NEXT: blr
top:
%1 = alloca i16, align 4
[PPC] Opaque pointer migration, part 2. The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
2022-10-07 18:34:40 +00:00
store i16 0, ptr %1, align 4
%rv.i = atomicrmw min ptr %1, i16 %0 acq_rel
%rv.i2 = load atomic i16, ptr %1 acquire, align 16
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
ret i16 %rv.i2
}
[PPC] Opaque pointer migration, part 2. The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
2022-10-07 18:34:40 +00:00
define i16 @noSEXTLoad(ptr %p) #0 {
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
; CHECK-LABEL: noSEXTLoad:
; CHECK: # %bb.0: # %top
; CHECK-NEXT: li 4, 0
[PowerPC] Define SchedModel for Power8 PowerPC subtargets prior to Power9 use the 'legacy' itinerary way to provide scheduling information. This patch re-writes the tablegen file to define the scheduling information in the new SchedModel way, which can bring improvements to some benchmarks. Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D154488
2023-09-08 15:41:23 +08:00
; CHECK-NEXT: lha 3, 0(3)
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
; CHECK-NEXT: sth 4, -4(1)
[PowerPC] Fix bugs in sign-/zero-extension elimination This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass. - Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer). - Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension). To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D40554
2022-08-16 11:08:33 -05:00
; CHECK-NEXT: addi 4, 1, -4
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
; CHECK-NEXT: lwsync
; CHECK-NEXT: .LBB2_1: # %top
; CHECK-NEXT: #
[PowerPC] Fix bugs in sign-/zero-extension elimination This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass. - Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer). - Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension). To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D40554
2022-08-16 11:08:33 -05:00
; CHECK-NEXT: lharx 5, 0, 4
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
; CHECK-NEXT: extsh 5, 5
[PowerPC] Fix a number of inefficiencies and issues with atomic code gen There are a few issues with the code we generate for atomic operations and the way we generate it: - Hard coded CR0 for compares - Order of operands for compares not conducive to emitting compare-immediate or for CSE of compares - Missing MachineMemOperand for st[bhwd]cx intrinsics - Missing intrinsic properties for the same - Unnecessary blocks with store conditional instructions to clear reservation (which ends up hindering performance) - Move from CR instructions just to compare the result of a store conditional with zero (even though it is a record-form) This patch aims to resolve all of those issues. Differential revision: https://reviews.llvm.org/D134783
2022-10-03 19:55:05 -05:00
; CHECK-NEXT: cmpw 5, 3
; CHECK-NEXT: blt 0, .LBB2_3
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
; CHECK-NEXT: # %bb.2: # %top
; CHECK-NEXT: #
[PowerPC] Fix bugs in sign-/zero-extension elimination This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass. - Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer). - Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension). To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D40554
2022-08-16 11:08:33 -05:00
; CHECK-NEXT: sthcx. 3, 0, 4
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
; CHECK-NEXT: bne 0, .LBB2_1
; CHECK-NEXT: .LBB2_3: # %top
; CHECK-NEXT: lwsync
; CHECK-NEXT: lhz 3, -4(1)
; CHECK-NEXT: cmpd 7, 3, 3
; CHECK-NEXT: bne- 7, .+4
; CHECK-NEXT: isync
; CHECK-NEXT: blr
top:
[PPC] Opaque pointer migration, part 2. The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
2022-10-07 18:34:40 +00:00
%0 = load i16, ptr %p, align 2
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
%1 = alloca i16, align 4
[PPC] Opaque pointer migration, part 2. The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
2022-10-07 18:34:40 +00:00
store i16 0, ptr %1, align 4
%rv.i = atomicrmw min ptr %1, i16 %0 acq_rel
%rv.i2 = load atomic i16, ptr %1 acquire, align 16
[PowerPC] Sign extend comparison operand for signed atomic comparisons As of 8dacca943af8a53a23b1caf3142d10fb4a77b645, we sign extend the atomic loaded operand for signed subword comparisons. However, the assumption that the other operand is correctly sign extended doesn't always hold. This patch sign extends the other operand if it needs to be sign extended. This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451 Differential revision: https://reviews.llvm.org/D94058
2021-01-18 21:19:11 -06:00
ret i16 %rv.i2
}
attributes #0 = { nounwind }
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