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llvm-project/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

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[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
//===- RISCVRVVInitUndef.cpp - Initialize undef vector value to pseudo ----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements a function pass that initializes undef vector value to
// temporary pseudo instruction and remove it in expandpseudo pass to prevent
// register allocation resulting in a constraint violated result for vector
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands In a recent series of refactorings (described here: https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295), I greatly increased the number of IMPLICIT_DEF operands to our vector instructions. This has turned out to have an unexpected negative impact because MachineCSE does not CSE IMPLICIT_DEFs, and thus does not CSE any instruction with an IMPLICIT_DEF operand. SelectionDAG *does* CSE the same case, but that only covers the same block case, not the cross block case. This lead to the performance regression reported in https://github.com/llvm/llvm-project/issues/64282. This change is a slightly ugly hack to side step the issue. Instead of fixing the root cause (lack of CSE for IMPLICIT_DEF) or undoing the operand changes, we leave the extra operand in place, and use NoReg in place of IMPLICIT_DEF. I then convert back to IMPLICIT_DEF just before register allocation so that ProcessImplicitDefs and TwoAddressInstructions can do the normal transforms to Undef tied registers. We may end up backporting this into the 17.x release branch. Given how late in the release cycle this is landing, that's much less likely now, but still a possibility. Differential Revision: https://reviews.llvm.org/D156909
2023-08-14 12:39:29 -07:00
// instruction. It also rewrites the NoReg tied operand back to an
// IMPLICIT_DEF.
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
//
// RISC-V vector instruction has register overlapping constraint for certain
// instructions, and will cause illegal instruction trap if violated, we use
// early clobber to model this constraint, but it can't prevent register
// allocator allocated same or overlapped if the input register is undef value,
// so convert IMPLICIT_DEF to temporary pseudo instruction and remove it later
// could prevent that happen, it's not best way to resolve this, and it might
// change the order of program or increase the register pressure, so ideally we
// should model the constraint right, but before we model the constraint right,
// it's the only way to prevent that happen.
//
// When we enable the subregister liveness option, it will also trigger same
// issue due to the partial of register is undef. If we pseudoinit the whole
// register, then it will generate redundant COPY instruction. Currently, it
// will generate INSERT_SUBREG to make sure the whole register is occupied
// when program encounter operation that has early-clobber constraint.
//
//
// See also: https://github.com/llvm/llvm-project/issues/50157
//
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands In a recent series of refactorings (described here: https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295), I greatly increased the number of IMPLICIT_DEF operands to our vector instructions. This has turned out to have an unexpected negative impact because MachineCSE does not CSE IMPLICIT_DEFs, and thus does not CSE any instruction with an IMPLICIT_DEF operand. SelectionDAG *does* CSE the same case, but that only covers the same block case, not the cross block case. This lead to the performance regression reported in https://github.com/llvm/llvm-project/issues/64282. This change is a slightly ugly hack to side step the issue. Instead of fixing the root cause (lack of CSE for IMPLICIT_DEF) or undoing the operand changes, we leave the extra operand in place, and use NoReg in place of IMPLICIT_DEF. I then convert back to IMPLICIT_DEF just before register allocation so that ProcessImplicitDefs and TwoAddressInstructions can do the normal transforms to Undef tied registers. We may end up backporting this into the 17.x release branch. Given how late in the release cycle this is landing, that's much less likely now, but still a possibility. Differential Revision: https://reviews.llvm.org/D156909
2023-08-14 12:39:29 -07:00
// Additionally, this pass rewrites tied operands of vector instructions
// from NoReg to IMPLICIT_DEF. (Not that this is a non-overlapping set of
// operands to the above.) We use NoReg to side step a MachineCSE
// optimization quality problem but need to convert back before
// TwoAddressInstruction. See pr64282 for context.
//
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
//===----------------------------------------------------------------------===//
#include "RISCV.h"
#include "RISCVSubtarget.h"
[llvm] Remove SmallSet from MachineInstr.h `MachineInstr.h` is a commonly included file and this includes `llvm/ADT/SmallSet.h` for one function `getUsedDebugRegs()`, which is used only in one place. According to `ClangBuildAnalyzer` (run solely on building LLVM, no other projects) the second most expensive template to instantiate is the `SmallSet::insert` method used in the `inline` implementation in `getUsedDebugRegs()`: ``` **** Templates that took longest to instantiate: 554239 ms: std::unordered_map<int, int> (2826 times, avg 196 ms) 521187 ms: llvm::SmallSet<llvm::Register, 4>::insert (930 times, avg 560 ms) ... ``` By removing this method and putting its implementation in the one call site we greatly reduce the template instantiation time and reduce the number of includes. When copying the implementation, I removed a check on `MO.getReg()` as this is checked within `MO.isVirtual()`. Differential Revision: https://reviews.llvm.org/D157720
2023-08-11 09:56:23 +01:00
#include "llvm/ADT/SmallSet.h"
[RISCV] postpone removal in initundef pass (#71661) InitUndef pass need replace the implicit def with Undef pseudo, but current remove method will make noreg2implicit borken. This patch postpone the removal until all basicblock be processed.
2023-11-20 11:44:27 +08:00
#include "llvm/ADT/SmallVector.h"
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
#include "llvm/CodeGen/DetectDeadLanes.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
using namespace llvm;
#define DEBUG_TYPE "riscv-init-undef"
[RISCV] Replace RISCV->RISC-V in strings. To be consistent with RISC-V branding guidelines https://riscv.org/about/risc-v-branding-guidelines/ Think we should be using RISC-V where possible. D146449 already updated comments. Strings may have more user impact. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D146451
2023-03-27 09:20:07 -07:00
#define RISCV_INIT_UNDEF_NAME "RISC-V init undef pass"
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
namespace {
class RISCVInitUndef : public MachineFunctionPass {
const TargetInstrInfo *TII;
MachineRegisterInfo *MRI;
const RISCVSubtarget *ST;
const TargetRegisterInfo *TRI;
[RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF (try 2) Reapplying after revert due to sanitizer failure. Includes fix to avoid querying dead lanes for vreg introduced by previous transform. The code was written with the implicit assumption that each IMPLICIT_DEF either a) the tied operand, or b) an untied source, but not both. This is true right now, but an upcoming change may allow CSE of IMPLICIT_DEFs in some cases, so let's rewrite the code to handle that possibility. I added an MIR case which demonstrates the multiple use IMPLICIT_DEF. To my knowledge, this is not a reachable configuration from IR right now. As an aside, this makes the structure a much closer match with the sub-reg liveness case, and we can probably just merge these routines. (Future work.) Differential Revision: https://reviews.llvm.org/D156477
2023-08-01 10:40:32 -07:00
// Newly added vregs, assumed to be fully rewritten
SmallSet<Register, 8> NewRegs;
[RISCV] postpone removal in initundef pass (#71661) InitUndef pass need replace the implicit def with Undef pseudo, but current remove method will make noreg2implicit borken. This patch postpone the removal until all basicblock be processed.
2023-11-20 11:44:27 +08:00
SmallVector<MachineInstr *, 8> DeadInsts;
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
public:
static char ID;
[RISCV] Cleanup pass initialization. Remove redundant initializations from pass constructors that were already being initialized by LLVMInitializeRISCVTarget().
2023-12-07 18:19:14 -08:00
RISCVInitUndef() : MachineFunctionPass(ID) {}
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU);
}
StringRef getPassName() const override { return RISCV_INIT_UNDEF_NAME; }
private:
bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
const DeadLaneDetector &DLD);
bool isVectorRegClass(const Register R);
const TargetRegisterClass *
getVRLargestSuperClass(const TargetRegisterClass *RC) const;
bool handleSubReg(MachineFunction &MF, MachineInstr &MI,
const DeadLaneDetector &DLD);
[RISCV] Make InitUndef handle undef operand (#65755) Address https://github.com/llvm/llvm-project/issues/65704. If the operand is marked as undef, the InitUndef misses this case. This patch makes InitUndef pass handle the undef operand case.
2023-12-01 01:04:42 -06:00
bool fixupIllOperand(MachineInstr *MI, MachineOperand &MO);
bool handleReg(MachineInstr *MI);
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
};
} // end anonymous namespace
char RISCVInitUndef::ID = 0;
INITIALIZE_PASS(RISCVInitUndef, DEBUG_TYPE, RISCV_INIT_UNDEF_NAME, false, false)
char &llvm::RISCVInitUndefID = RISCVInitUndef::ID;
const TargetRegisterClass *
RISCVInitUndef::getVRLargestSuperClass(const TargetRegisterClass *RC) const {
if (RISCV::VRM8RegClass.hasSubClassEq(RC))
return &RISCV::VRM8RegClass;
if (RISCV::VRM4RegClass.hasSubClassEq(RC))
return &RISCV::VRM4RegClass;
if (RISCV::VRM2RegClass.hasSubClassEq(RC))
return &RISCV::VRM2RegClass;
if (RISCV::VRRegClass.hasSubClassEq(RC))
return &RISCV::VRRegClass;
return RC;
}
bool RISCVInitUndef::isVectorRegClass(const Register R) {
const TargetRegisterClass *RC = MRI->getRegClass(R);
return RISCV::VRRegClass.hasSubClassEq(RC) ||
RISCV::VRM2RegClass.hasSubClassEq(RC) ||
RISCV::VRM4RegClass.hasSubClassEq(RC) ||
RISCV::VRM8RegClass.hasSubClassEq(RC);
}
static unsigned getUndefInitOpcode(unsigned RegClassID) {
switch (RegClassID) {
case RISCV::VRRegClassID:
return RISCV::PseudoRVVInitUndefM1;
case RISCV::VRM2RegClassID:
return RISCV::PseudoRVVInitUndefM2;
case RISCV::VRM4RegClassID:
return RISCV::PseudoRVVInitUndefM4;
case RISCV::VRM8RegClassID:
return RISCV::PseudoRVVInitUndefM8;
default:
llvm_unreachable("Unexpected register class.");
}
}
[RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF (try 2) Reapplying after revert due to sanitizer failure. Includes fix to avoid querying dead lanes for vreg introduced by previous transform. The code was written with the implicit assumption that each IMPLICIT_DEF either a) the tied operand, or b) an untied source, but not both. This is true right now, but an upcoming change may allow CSE of IMPLICIT_DEFs in some cases, so let's rewrite the code to handle that possibility. I added an MIR case which demonstrates the multiple use IMPLICIT_DEF. To my knowledge, this is not a reachable configuration from IR right now. As an aside, this makes the structure a much closer match with the sub-reg liveness case, and we can probably just merge these routines. (Future work.) Differential Revision: https://reviews.llvm.org/D156477
2023-08-01 10:40:32 -07:00
static bool isEarlyClobberMI(MachineInstr &MI) {
return llvm::any_of(MI.defs(), [](const MachineOperand &DefMO) {
return DefMO.isReg() && DefMO.isEarlyClobber();
});
}
[RISCV] Make InitUndef handle undef operand (#65755) Address https://github.com/llvm/llvm-project/issues/65704. If the operand is marked as undef, the InitUndef misses this case. This patch makes InitUndef pass handle the undef operand case.
2023-12-01 01:04:42 -06:00
static bool findImplictDefMIFromReg(Register Reg, MachineRegisterInfo *MRI) {
for (auto &DefMI : MRI->def_instructions(Reg)) {
if (DefMI.getOpcode() == TargetOpcode::IMPLICIT_DEF)
return true;
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
}
[RISCV] Make InitUndef handle undef operand (#65755) Address https://github.com/llvm/llvm-project/issues/65704. If the operand is marked as undef, the InitUndef misses this case. This patch makes InitUndef pass handle the undef operand case.
2023-12-01 01:04:42 -06:00
return false;
}
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
[RISCV] Make InitUndef handle undef operand (#65755) Address https://github.com/llvm/llvm-project/issues/65704. If the operand is marked as undef, the InitUndef misses this case. This patch makes InitUndef pass handle the undef operand case.
2023-12-01 01:04:42 -06:00
bool RISCVInitUndef::handleReg(MachineInstr *MI) {
bool Changed = false;
for (auto &UseMO : MI->uses()) {
if (!UseMO.isReg())
continue;
if (UseMO.isTied())
continue;
if (!UseMO.getReg().isVirtual())
continue;
if (!isVectorRegClass(UseMO.getReg()))
continue;
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
[RISCV] Make InitUndef handle undef operand (#65755) Address https://github.com/llvm/llvm-project/issues/65704. If the operand is marked as undef, the InitUndef misses this case. This patch makes InitUndef pass handle the undef operand case.
2023-12-01 01:04:42 -06:00
if (UseMO.isUndef() || findImplictDefMIFromReg(UseMO.getReg(), MRI))
Changed |= fixupIllOperand(MI, UseMO);
[RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF (try 2) Reapplying after revert due to sanitizer failure. Includes fix to avoid querying dead lanes for vreg introduced by previous transform. The code was written with the implicit assumption that each IMPLICIT_DEF either a) the tied operand, or b) an untied source, but not both. This is true right now, but an upcoming change may allow CSE of IMPLICIT_DEFs in some cases, so let's rewrite the code to handle that possibility. I added an MIR case which demonstrates the multiple use IMPLICIT_DEF. To my knowledge, this is not a reachable configuration from IR right now. As an aside, this makes the structure a much closer match with the sub-reg liveness case, and we can probably just merge these routines. (Future work.) Differential Revision: https://reviews.llvm.org/D156477
2023-08-01 10:40:32 -07:00
}
[RISCV] Make InitUndef handle undef operand (#65755) Address https://github.com/llvm/llvm-project/issues/65704. If the operand is marked as undef, the InitUndef misses this case. This patch makes InitUndef pass handle the undef operand case.
2023-12-01 01:04:42 -06:00
return Changed;
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
}
bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
const DeadLaneDetector &DLD) {
bool Changed = false;
for (MachineOperand &UseMO : MI.uses()) {
if (!UseMO.isReg())
continue;
if (!UseMO.getReg().isVirtual())
continue;
[RISCVRVVInitUndef] Ignore tied use for partial undef register The purpose of this code is to restrict overlap between source and destination registers. The tied input register is conceptually part of the destination. I can't see any reason why we need to prevent a partial undef tied source here, and skipping it reduces register pressure slightly. Differential Revision: https://reviews.llvm.org/D156709
2023-08-01 12:16:26 -07:00
if (UseMO.isTied())
continue;
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
Register Reg = UseMO.getReg();
[RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF (try 2) Reapplying after revert due to sanitizer failure. Includes fix to avoid querying dead lanes for vreg introduced by previous transform. The code was written with the implicit assumption that each IMPLICIT_DEF either a) the tied operand, or b) an untied source, but not both. This is true right now, but an upcoming change may allow CSE of IMPLICIT_DEFs in some cases, so let's rewrite the code to handle that possibility. I added an MIR case which demonstrates the multiple use IMPLICIT_DEF. To my knowledge, this is not a reachable configuration from IR right now. As an aside, this makes the structure a much closer match with the sub-reg liveness case, and we can probably just merge these routines. (Future work.) Differential Revision: https://reviews.llvm.org/D156477
2023-08-01 10:40:32 -07:00
if (NewRegs.count(Reg))
continue;
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
DeadLaneDetector::VRegInfo Info =
DLD.getVRegInfo(Register::virtReg2Index(Reg));
if (Info.UsedLanes == Info.DefinedLanes)
continue;
const TargetRegisterClass *TargetRegClass =
getVRLargestSuperClass(MRI->getRegClass(Reg));
LaneBitmask NeedDef = Info.UsedLanes & ~Info.DefinedLanes;
LLVM_DEBUG({
dbgs() << "Instruction has undef subregister.\n";
dbgs() << printReg(Reg, nullptr)
<< " Used: " << PrintLaneMask(Info.UsedLanes)
<< " Def: " << PrintLaneMask(Info.DefinedLanes)
<< " Need Def: " << PrintLaneMask(NeedDef) << "\n";
});
SmallVector<unsigned> SubRegIndexNeedInsert;
TRI->getCoveringSubRegIndexes(*MRI, TargetRegClass, NeedDef,
SubRegIndexNeedInsert);
Register LatestReg = Reg;
for (auto ind : SubRegIndexNeedInsert) {
Changed = true;
const TargetRegisterClass *SubRegClass =
getVRLargestSuperClass(TRI->getSubRegisterClass(TargetRegClass, ind));
Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);
BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
TII->get(getUndefInitOpcode(SubRegClass->getID())),
TmpInitSubReg);
Register NewReg = MRI->createVirtualRegister(TargetRegClass);
BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
TII->get(TargetOpcode::INSERT_SUBREG), NewReg)
.addReg(LatestReg)
.addReg(TmpInitSubReg)
.addImm(ind);
LatestReg = NewReg;
}
UseMO.setReg(LatestReg);
}
return Changed;
}
[RISCV] Make InitUndef handle undef operand (#65755) Address https://github.com/llvm/llvm-project/issues/65704. If the operand is marked as undef, the InitUndef misses this case. This patch makes InitUndef pass handle the undef operand case.
2023-12-01 01:04:42 -06:00
bool RISCVInitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
LLVM_DEBUG(
dbgs() << "Emitting PseudoRVVInitUndef for implicit vector register "
<< MO.getReg() << '\n');
const TargetRegisterClass *TargetRegClass =
getVRLargestSuperClass(MRI->getRegClass(MO.getReg()));
unsigned Opcode = getUndefInitOpcode(TargetRegClass->getID());
Register NewReg = MRI->createVirtualRegister(TargetRegClass);
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(Opcode), NewReg);
MO.setReg(NewReg);
if (MO.isUndef())
MO.setIsUndef(false);
return true;
}
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
bool RISCVInitUndef::processBasicBlock(MachineFunction &MF,
MachineBasicBlock &MBB,
const DeadLaneDetector &DLD) {
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
MachineInstr &MI = *I;
[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands In a recent series of refactorings (described here: https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295), I greatly increased the number of IMPLICIT_DEF operands to our vector instructions. This has turned out to have an unexpected negative impact because MachineCSE does not CSE IMPLICIT_DEFs, and thus does not CSE any instruction with an IMPLICIT_DEF operand. SelectionDAG *does* CSE the same case, but that only covers the same block case, not the cross block case. This lead to the performance regression reported in https://github.com/llvm/llvm-project/issues/64282. This change is a slightly ugly hack to side step the issue. Instead of fixing the root cause (lack of CSE for IMPLICIT_DEF) or undoing the operand changes, we leave the extra operand in place, and use NoReg in place of IMPLICIT_DEF. I then convert back to IMPLICIT_DEF just before register allocation so that ProcessImplicitDefs and TwoAddressInstructions can do the normal transforms to Undef tied registers. We may end up backporting this into the 17.x release branch. Given how late in the release cycle this is landing, that's much less likely now, but still a possibility. Differential Revision: https://reviews.llvm.org/D156909
2023-08-14 12:39:29 -07:00
// If we used NoReg to represent the passthru, switch this back to being
// an IMPLICIT_DEF before TwoAddressInstructions.
unsigned UseOpIdx;
if (MI.getNumDefs() != 0 && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
MachineOperand &UseMO = MI.getOperand(UseOpIdx);
if (UseMO.getReg() == RISCV::NoRegister) {
const TargetRegisterClass *RC =
TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF);
Register NewDest = MRI->createVirtualRegister(RC);
// We don't have a way to update dead lanes, so keep track of the
// new register so that we avoid querying it later.
NewRegs.insert(NewDest);
BuildMI(MBB, I, I->getDebugLoc(),
TII->get(TargetOpcode::IMPLICIT_DEF), NewDest);
UseMO.setReg(NewDest);
Changed = true;
}
}
[RISCV] Make InitUndef handle undef operand (#65755) Address https://github.com/llvm/llvm-project/issues/65704. If the operand is marked as undef, the InitUndef misses this case. This patch makes InitUndef pass handle the undef operand case.
2023-12-01 01:04:42 -06:00
if (isEarlyClobberMI(MI)) {
if (ST->enableSubRegLiveness())
Changed |= handleSubReg(MF, MI, DLD);
Changed |= handleReg(&MI);
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
}
}
return Changed;
}
bool RISCVInitUndef::runOnMachineFunction(MachineFunction &MF) {
ST = &MF.getSubtarget<RISCVSubtarget>();
if (!ST->hasVInstructions())
return false;
MRI = &MF.getRegInfo();
TII = ST->getInstrInfo();
TRI = MRI->getTargetRegisterInfo();
bool Changed = false;
DeadLaneDetector DLD(MRI, TRI);
DLD.computeSubRegisterLaneBitInfo();
for (MachineBasicBlock &BB : MF)
Changed |= processBasicBlock(MF, BB, DLD);
[RISCV] postpone removal in initundef pass (#71661) InitUndef pass need replace the implicit def with Undef pseudo, but current remove method will make noreg2implicit borken. This patch postpone the removal until all basicblock be processed.
2023-11-20 11:44:27 +08:00
for (auto *DeadMI : DeadInsts)
DeadMI->eraseFromParent();
DeadInsts.clear();
[RISCV] Add new pass to transform undef to pseudo for vector values. RISC-V vector instruction has register overlapping constraint for certain instructions, and will cause illegal instruction trap if violated, we use early clobber to model this constraint, but it can't prevent register allocator allocated same or overlapped if the input register is undef value, so convert IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way to resolve this. Ideally we should model the constraint right, but before we model the constraint right, it's the approach to prevent that happen. See also: https://github.com/llvm/llvm-project/issues/50157 Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D129735
2023-02-22 04:02:06 -08:00
return Changed;
}
FunctionPass *llvm::createRISCVInitUndefPass() { return new RISCVInitUndef(); }
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