2017-06-16 17:32:43 +00:00
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//===- AMDGPU.cpp ---------------------------------------------------------===//
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//
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2019-01-19 08:50:56 +00:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2017-06-16 17:32:43 +00:00
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//
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//===----------------------------------------------------------------------===//
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#include "InputFiles.h"
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#include "Symbols.h"
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#include "Target.h"
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[lld] unified COFF and ELF error handling on new Common/ErrorHandler
Summary:
The COFF linker and the ELF linker have long had similar but separate
Error.h and Error.cpp files to implement error handling. This change
introduces new error handling code in Common/ErrorHandler.h, changes the
COFF and ELF linkers to use it, and removes the old, separate
implementations.
Reviewers: ruiu
Reviewed By: ruiu
Subscribers: smeenai, jyknight, emaste, sdardis, nemanjai, nhaehnle, mgorny, javed.absar, kbarton, fedor.sergeev, llvm-commits
Differential Revision: https://reviews.llvm.org/D39259
llvm-svn: 316624
2017-10-25 22:28:38 +00:00
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#include "lld/Common/ErrorHandler.h"
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2017-06-16 17:32:43 +00:00
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#include "llvm/Object/ELF.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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using namespace llvm::object;
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using namespace llvm::support::endian;
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using namespace llvm::ELF;
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2019-10-07 08:31:18 +00:00
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namespace lld {
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namespace elf {
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2017-06-16 17:32:43 +00:00
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namespace {
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class AMDGPU final : public TargetInfo {
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public:
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AMDGPU();
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2017-10-24 19:05:32 +00:00
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uint32_t calcEFlags() const override;
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2017-10-11 22:49:24 +00:00
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void relocateOne(uint8_t *loc, RelType type, uint64_t val) const override;
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2017-11-03 21:21:47 +00:00
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RelExpr getRelExpr(RelType type, const Symbol &s,
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2017-06-16 17:32:43 +00:00
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const uint8_t *loc) const override;
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[ELF][ARM][AARCH64][MIPS][PPC] Simplify the logic to create R_*_RELATIVE for absolute relocation types in writable sections
Summary:
Our rule to create R_*_RELATIVE for absolute relocation types were
loose. D63121 made it stricter but it failed to create R_*_RELATIVE for
R_ARM_TARGET1 and R_PPC64_TOC. rLLD363236 worked around that by
reinstating the original behavior for ARM and PPC64.
This patch is an attempt to simplify the logic.
Note, in ld.bfd, R_ARM_TARGET2 --target2=abs also creates
R_ARM_RELATIVE. This seems a very uncommon scenario (moreover,
--target2=got-rel is the default), so I do not implement any logic
related to it.
Also, delete R_AARCH64_ABS32 from AArch64::getDynRel. We don't have
working ILP32 support yet. Allowing it would create an incorrect
R_AARCH64_RELATIVE.
For MIPS, the (if SymbolRel, then RelativeRel) code is to keep its
behavior unchanged.
Note, in ppc64-abs64-dyn.s, R_PPC64_TOC gets an incorrect addend because
computeAddend() doesn't compute the correct address. We seem to have the
wrong behavior for a long time. The important thing seems that a dynamic
relocation R_PPC64_TOC should not be created as the dynamic loader will
error R_PPC64_TOC is not supported.
Reviewers: atanasyan, grimar, peter.smith, ruiu, sfertile, espindola
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D63383
llvm-svn: 363928
2019-06-20 14:00:08 +00:00
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RelType getDynRel(RelType type) const override;
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2017-06-16 17:32:43 +00:00
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};
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} // namespace
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AMDGPU::AMDGPU() {
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2017-10-16 20:46:53 +00:00
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relativeRel = R_AMDGPU_RELATIVE64;
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2017-06-16 17:32:43 +00:00
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gotRel = R_AMDGPU_ABS64;
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2018-09-26 08:11:34 +00:00
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noneRel = R_AMDGPU_NONE;
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2019-06-11 12:59:30 +00:00
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symbolicRel = R_AMDGPU_ABS64;
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2017-06-16 17:32:43 +00:00
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}
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2017-10-24 19:40:03 +00:00
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static uint32_t getEFlags(InputFile *file) {
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return cast<ObjFile<ELF64LE>>(file)->getObj().getHeader()->e_flags;
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}
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2017-10-24 19:05:32 +00:00
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2017-10-24 19:40:03 +00:00
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uint32_t AMDGPU::calcEFlags() const {
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assert(!objectFiles.empty());
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uint32_t ret = getEFlags(objectFiles[0]);
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2017-10-24 19:05:32 +00:00
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// Verify that all input files have the same e_flags.
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2017-10-24 19:40:03 +00:00
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for (InputFile *f : makeArrayRef(objectFiles).slice(1)) {
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if (ret == getEFlags(f))
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continue;
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error("incompatible e_flags: " + toString(f));
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return 0;
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2017-10-24 19:05:32 +00:00
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}
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return ret;
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}
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2017-10-11 22:49:24 +00:00
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void AMDGPU::relocateOne(uint8_t *loc, RelType type, uint64_t val) const {
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2017-06-16 17:32:43 +00:00
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switch (type) {
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case R_AMDGPU_ABS32:
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case R_AMDGPU_GOTPCREL:
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case R_AMDGPU_GOTPCREL32_LO:
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case R_AMDGPU_REL32:
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case R_AMDGPU_REL32_LO:
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write32le(loc, val);
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break;
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case R_AMDGPU_ABS64:
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2018-06-11 21:42:53 +00:00
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case R_AMDGPU_REL64:
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2017-06-16 17:32:43 +00:00
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write64le(loc, val);
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break;
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case R_AMDGPU_GOTPCREL32_HI:
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case R_AMDGPU_REL32_HI:
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write32le(loc, val >> 32);
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break;
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default:
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2019-02-14 18:02:20 +00:00
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llvm_unreachable("unknown relocation");
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2017-06-16 17:32:43 +00:00
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}
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}
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2017-11-03 21:21:47 +00:00
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RelExpr AMDGPU::getRelExpr(RelType type, const Symbol &s,
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2017-10-12 03:14:06 +00:00
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const uint8_t *loc) const {
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2017-06-16 17:32:43 +00:00
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switch (type) {
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case R_AMDGPU_ABS32:
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case R_AMDGPU_ABS64:
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return R_ABS;
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case R_AMDGPU_REL32:
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case R_AMDGPU_REL32_LO:
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case R_AMDGPU_REL32_HI:
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2018-06-11 21:42:53 +00:00
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case R_AMDGPU_REL64:
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2017-06-16 17:32:43 +00:00
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return R_PC;
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case R_AMDGPU_GOTPCREL:
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case R_AMDGPU_GOTPCREL32_LO:
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case R_AMDGPU_GOTPCREL32_HI:
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return R_GOT_PC;
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default:
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2019-02-14 18:02:20 +00:00
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error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
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") against symbol " + toString(s));
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return R_NONE;
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2017-06-16 17:32:43 +00:00
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}
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}
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[ELF][ARM][AARCH64][MIPS][PPC] Simplify the logic to create R_*_RELATIVE for absolute relocation types in writable sections
Summary:
Our rule to create R_*_RELATIVE for absolute relocation types were
loose. D63121 made it stricter but it failed to create R_*_RELATIVE for
R_ARM_TARGET1 and R_PPC64_TOC. rLLD363236 worked around that by
reinstating the original behavior for ARM and PPC64.
This patch is an attempt to simplify the logic.
Note, in ld.bfd, R_ARM_TARGET2 --target2=abs also creates
R_ARM_RELATIVE. This seems a very uncommon scenario (moreover,
--target2=got-rel is the default), so I do not implement any logic
related to it.
Also, delete R_AARCH64_ABS32 from AArch64::getDynRel. We don't have
working ILP32 support yet. Allowing it would create an incorrect
R_AARCH64_RELATIVE.
For MIPS, the (if SymbolRel, then RelativeRel) code is to keep its
behavior unchanged.
Note, in ppc64-abs64-dyn.s, R_PPC64_TOC gets an incorrect addend because
computeAddend() doesn't compute the correct address. We seem to have the
wrong behavior for a long time. The important thing seems that a dynamic
relocation R_PPC64_TOC should not be created as the dynamic loader will
error R_PPC64_TOC is not supported.
Reviewers: atanasyan, grimar, peter.smith, ruiu, sfertile, espindola
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D63383
llvm-svn: 363928
2019-06-20 14:00:08 +00:00
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RelType AMDGPU::getDynRel(RelType type) const {
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if (type == R_AMDGPU_ABS64)
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return type;
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return R_AMDGPU_NONE;
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}
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2019-10-07 08:31:18 +00:00
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TargetInfo *getAMDGPUTargetInfo() {
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2017-06-16 20:15:03 +00:00
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static AMDGPU target;
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return ⌖
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}
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2019-10-07 08:31:18 +00:00
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} // namespace elf
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} // namespace lld
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