2009-12-19 02:59:52 +00:00
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//===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
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//
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2019-01-19 08:50:56 +00:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2009-12-19 02:59:52 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler Emitter.
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// It contains the implementation of the disassembler tables.
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// Documentation for the disassembler emitter in general can be found in
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2017-07-04 13:09:29 +00:00
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// X86DisassemblerEmitter.h.
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2009-12-19 02:59:52 +00:00
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//
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//===----------------------------------------------------------------------===//
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#include "X86DisassemblerTables.h"
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2012-12-04 10:37:14 +00:00
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#include "X86DisassemblerShared.h"
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2022-01-28 14:55:42 +01:00
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#include "X86ModRMFilters.h"
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#include "llvm/ADT/SmallVector.h"
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2009-12-19 02:59:52 +00:00
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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2022-01-28 14:55:42 +01:00
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#include "llvm/Support/raw_ostream.h"
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2012-08-01 07:39:18 +00:00
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#include <map>
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2009-12-19 02:59:52 +00:00
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using namespace llvm;
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using namespace X86Disassembler;
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2012-07-31 05:27:01 +00:00
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2014-01-01 15:12:34 +00:00
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/// stringForContext - Returns a string containing the name of a particular
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/// InstructionContext, usually for diagnostic purposes.
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///
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/// @param insnContext - The instruction class to transform to a string.
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/// @return - A statically-allocated string constant that contains the
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/// name of the instruction class.
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2023-12-07 20:58:04 +08:00
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static inline const char *stringForContext(InstructionContext insnContext) {
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2014-01-01 15:12:34 +00:00
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switch (insnContext) {
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default:
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llvm_unreachable("Unhandled instruction class");
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2023-12-07 20:58:04 +08:00
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#define ENUM_ENTRY(n, r, d) \
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case n: \
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return #n; \
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break;
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#define ENUM_ENTRY_K_B(n, r, d) \
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ENUM_ENTRY(n, r, d) \
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ENUM_ENTRY(n##_K_B, r, d) \
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ENUM_ENTRY(n##_KZ, r, d) \
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ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d)
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INSTRUCTION_CONTEXTS
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2014-01-01 15:12:34 +00:00
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#undef ENUM_ENTRY
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#undef ENUM_ENTRY_K_B
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}
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}
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/// stringForOperandType - Like stringForContext, but for OperandTypes.
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2023-12-07 20:58:04 +08:00
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static inline const char *stringForOperandType(OperandType type) {
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2014-01-01 15:12:34 +00:00
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switch (type) {
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default:
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llvm_unreachable("Unhandled type");
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2023-12-07 20:58:04 +08:00
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#define ENUM_ENTRY(i, d) \
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case i: \
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return #i;
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TYPES
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2014-01-01 15:12:34 +00:00
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#undef ENUM_ENTRY
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}
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}
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/// stringForOperandEncoding - like stringForContext, but for
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/// OperandEncodings.
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2023-12-07 20:58:04 +08:00
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static inline const char *stringForOperandEncoding(OperandEncoding encoding) {
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2014-01-01 15:12:34 +00:00
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switch (encoding) {
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default:
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llvm_unreachable("Unhandled encoding");
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2023-12-07 20:58:04 +08:00
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#define ENUM_ENTRY(i, d) \
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case i: \
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return #i;
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ENCODINGS
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2014-01-01 15:12:34 +00:00
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#undef ENUM_ENTRY
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}
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}
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2009-12-19 02:59:52 +00:00
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/// inheritsFrom - Indicates whether all instructions in one class also belong
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/// to another class.
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///
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/// @param child - The class that may be the subset
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/// @param parent - The class that may be the superset
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/// @return - True if child is a subset of parent, false otherwise.
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static inline bool inheritsFrom(InstructionContext child,
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2017-10-23 16:49:26 +00:00
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InstructionContext parent, bool noPrefix = true,
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2023-04-20 11:07:18 +08:00
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bool VEX_LIG = false, bool WIG = false,
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2017-10-22 06:18:26 +00:00
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bool AdSize64 = false) {
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2009-12-19 02:59:52 +00:00
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if (child == parent)
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return true;
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2012-07-31 05:27:01 +00:00
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2009-12-19 02:59:52 +00:00
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switch (parent) {
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case IC:
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2023-12-07 20:58:04 +08:00
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return (inheritsFrom(child, IC_64BIT, AdSize64) ||
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(noPrefix && inheritsFrom(child, IC_OPSIZE, noPrefix)) ||
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inheritsFrom(child, IC_ADSIZE) ||
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(noPrefix && inheritsFrom(child, IC_XD, noPrefix)) ||
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(noPrefix && inheritsFrom(child, IC_XS, noPrefix)));
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2009-12-19 02:59:52 +00:00
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case IC_64BIT:
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2023-12-07 20:58:04 +08:00
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return (inheritsFrom(child, IC_64BIT_REXW) ||
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(noPrefix && inheritsFrom(child, IC_64BIT_OPSIZE, noPrefix)) ||
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(!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) ||
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(noPrefix && inheritsFrom(child, IC_64BIT_XD, noPrefix)) ||
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(noPrefix && inheritsFrom(child, IC_64BIT_XS, noPrefix)));
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2009-12-19 02:59:52 +00:00
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case IC_OPSIZE:
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2014-12-31 07:07:31 +00:00
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return inheritsFrom(child, IC_64BIT_OPSIZE) ||
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inheritsFrom(child, IC_OPSIZE_ADSIZE);
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2012-02-27 01:54:29 +00:00
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case IC_ADSIZE:
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2017-10-23 16:49:26 +00:00
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return (noPrefix && inheritsFrom(child, IC_OPSIZE_ADSIZE, noPrefix));
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2014-12-31 07:07:31 +00:00
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case IC_OPSIZE_ADSIZE:
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return false;
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2012-02-27 01:54:29 +00:00
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case IC_64BIT_ADSIZE:
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2017-10-23 16:49:26 +00:00
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return (noPrefix && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE, noPrefix));
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2014-12-31 07:07:31 +00:00
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case IC_64BIT_OPSIZE_ADSIZE:
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[X86] Fix handling of maskmovdqu in x32 differently
This reverts the functional changes of D103427 but keeps its tests, and
and reimplements the functionality by reusing the existing 32-bit
MASKMOVDQU and VMASKMOVDQU instructions as suggested by skan in review.
These instructions were previously predicated on Not64BitMode. This
reimplementation restores the disassembly of a class of instructions,
which will see a test added in followup patch D122449.
These instructions are in 64-bit mode special cased in
X86MCInstLower::Lower, because we use flags with one meaning for subtly
different things: we have an AdSize32 class which indicates both that
the instruction needs a 0x67 prefix and that the text form of the
instruction implies a 0x67 prefix. These instructions are special in
needing a 0x67 prefix but having a text form that does *not* imply a
0x67 prefix, so we encode this in MCInst as an instruction that has an
explicit address size override.
Note that originally VMASKMOVDQU64 was special cased to be excluded from
disassembly, as we cannot distinguish between VMASKMOVDQU and
VMASKMOVDQU64 and rely on the fact that these are indistinguishable, or
close enough to it, at the MCInst level that it does not matter which we
use. Because VMASKMOVDQU now receives special casing, even though it
does not make a difference in the current implementation, as a
precaution VMASKMOVDQU is excluded from disassembly rather than
VMASKMOVDQU64.
Reviewed By: RKSimon, skan
Differential Revision: https://reviews.llvm.org/D122540
2022-04-12 18:32:14 +01:00
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return false;
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2009-12-19 02:59:52 +00:00
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case IC_XD:
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2011-09-02 04:17:54 +00:00
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return inheritsFrom(child, IC_64BIT_XD);
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2009-12-19 02:59:52 +00:00
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case IC_XS:
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2011-09-02 04:17:54 +00:00
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return inheritsFrom(child, IC_64BIT_XS);
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2011-10-01 19:54:56 +00:00
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case IC_XD_OPSIZE:
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return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
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2011-10-11 04:34:23 +00:00
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case IC_XS_OPSIZE:
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return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
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2018-04-05 18:20:14 +00:00
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case IC_XD_ADSIZE:
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return inheritsFrom(child, IC_64BIT_XD_ADSIZE);
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case IC_XS_ADSIZE:
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return inheritsFrom(child, IC_64BIT_XS_ADSIZE);
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2009-12-19 02:59:52 +00:00
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case IC_64BIT_REXW:
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2023-12-07 20:58:04 +08:00
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return ((noPrefix && inheritsFrom(child, IC_64BIT_REXW_XS, noPrefix)) ||
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(noPrefix && inheritsFrom(child, IC_64BIT_REXW_XD, noPrefix)) ||
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(noPrefix && inheritsFrom(child, IC_64BIT_REXW_OPSIZE, noPrefix)) ||
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(!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE)));
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2009-12-19 02:59:52 +00:00
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case IC_64BIT_OPSIZE:
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2014-12-31 07:07:31 +00:00
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return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
|
2015-01-03 00:00:20 +00:00
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|
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(!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE)) ||
|
[X86] Fix handling of maskmovdqu in x32 differently
This reverts the functional changes of D103427 but keeps its tests, and
and reimplements the functionality by reusing the existing 32-bit
MASKMOVDQU and VMASKMOVDQU instructions as suggested by skan in review.
These instructions were previously predicated on Not64BitMode. This
reimplementation restores the disassembly of a class of instructions,
which will see a test added in followup patch D122449.
These instructions are in 64-bit mode special cased in
X86MCInstLower::Lower, because we use flags with one meaning for subtly
different things: we have an AdSize32 class which indicates both that
the instruction needs a 0x67 prefix and that the text form of the
instruction implies a 0x67 prefix. These instructions are special in
needing a 0x67 prefix but having a text form that does *not* imply a
0x67 prefix, so we encode this in MCInst as an instruction that has an
explicit address size override.
Note that originally VMASKMOVDQU64 was special cased to be excluded from
disassembly, as we cannot distinguish between VMASKMOVDQU and
VMASKMOVDQU64 and rely on the fact that these are indistinguishable, or
close enough to it, at the MCInst level that it does not matter which we
use. Because VMASKMOVDQU now receives special casing, even though it
does not make a difference in the current implementation, as a
precaution VMASKMOVDQU is excluded from disassembly rather than
VMASKMOVDQU64.
Reviewed By: RKSimon, skan
Differential Revision: https://reviews.llvm.org/D122540
2022-04-12 18:32:14 +01:00
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(!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE));
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2009-12-19 02:59:52 +00:00
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case IC_64BIT_XD:
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2023-12-07 20:58:04 +08:00
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return (inheritsFrom(child, IC_64BIT_REXW_XD) ||
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(!AdSize64 && inheritsFrom(child, IC_64BIT_XD_ADSIZE)));
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2009-12-19 02:59:52 +00:00
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case IC_64BIT_XS:
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2023-12-07 20:58:04 +08:00
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return (inheritsFrom(child, IC_64BIT_REXW_XS) ||
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(!AdSize64 && inheritsFrom(child, IC_64BIT_XS_ADSIZE)));
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2011-10-01 19:54:56 +00:00
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case IC_64BIT_XD_OPSIZE:
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2011-10-11 04:34:23 +00:00
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case IC_64BIT_XS_OPSIZE:
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2011-10-01 19:54:56 +00:00
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return false;
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2018-04-05 18:20:14 +00:00
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case IC_64BIT_XD_ADSIZE:
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case IC_64BIT_XS_ADSIZE:
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return false;
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2009-12-19 02:59:52 +00:00
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case IC_64BIT_REXW_XD:
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case IC_64BIT_REXW_XS:
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case IC_64BIT_REXW_OPSIZE:
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2015-01-03 00:00:20 +00:00
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case IC_64BIT_REXW_ADSIZE:
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2023-11-22 10:26:23 +08:00
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case IC_64BIT_REX2:
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2009-12-19 02:59:52 +00:00
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return false;
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2011-03-15 01:23:15 +00:00
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case IC_VEX:
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2023-04-20 11:07:18 +08:00
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return (VEX_LIG && WIG && inheritsFrom(child, IC_VEX_L_W)) ||
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(WIG && inheritsFrom(child, IC_VEX_W)) ||
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2011-10-04 06:30:42 +00:00
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(VEX_LIG && inheritsFrom(child, IC_VEX_L));
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2011-03-15 01:23:15 +00:00
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case IC_VEX_XS:
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2023-04-20 11:07:18 +08:00
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return (VEX_LIG && WIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
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(WIG && inheritsFrom(child, IC_VEX_W_XS)) ||
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2011-10-04 06:30:42 +00:00
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(VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
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2011-03-15 01:23:15 +00:00
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case IC_VEX_XD:
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2023-04-20 11:07:18 +08:00
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return (VEX_LIG && WIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
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(WIG && inheritsFrom(child, IC_VEX_W_XD)) ||
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2011-10-04 06:30:42 +00:00
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(VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
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2011-09-02 04:17:54 +00:00
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case IC_VEX_OPSIZE:
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2023-04-20 11:07:18 +08:00
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return (VEX_LIG && WIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
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|
|
|
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(WIG && inheritsFrom(child, IC_VEX_W_OPSIZE)) ||
|
[X86] Fix handling of maskmovdqu in x32 differently
This reverts the functional changes of D103427 but keeps its tests, and
and reimplements the functionality by reusing the existing 32-bit
MASKMOVDQU and VMASKMOVDQU instructions as suggested by skan in review.
These instructions were previously predicated on Not64BitMode. This
reimplementation restores the disassembly of a class of instructions,
which will see a test added in followup patch D122449.
These instructions are in 64-bit mode special cased in
X86MCInstLower::Lower, because we use flags with one meaning for subtly
different things: we have an AdSize32 class which indicates both that
the instruction needs a 0x67 prefix and that the text form of the
instruction implies a 0x67 prefix. These instructions are special in
needing a 0x67 prefix but having a text form that does *not* imply a
0x67 prefix, so we encode this in MCInst as an instruction that has an
explicit address size override.
Note that originally VMASKMOVDQU64 was special cased to be excluded from
disassembly, as we cannot distinguish between VMASKMOVDQU and
VMASKMOVDQU64 and rely on the fact that these are indistinguishable, or
close enough to it, at the MCInst level that it does not matter which we
use. Because VMASKMOVDQU now receives special casing, even though it
does not make a difference in the current implementation, as a
precaution VMASKMOVDQU is excluded from disassembly rather than
VMASKMOVDQU64.
Reviewed By: RKSimon, skan
Differential Revision: https://reviews.llvm.org/D122540
2022-04-12 18:32:14 +01:00
|
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(VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
|
2011-09-02 04:17:54 +00:00
|
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case IC_VEX_W:
|
Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
llvm-svn: 191649
2013-09-30 02:46:36 +00:00
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return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
|
2011-09-02 04:17:54 +00:00
|
|
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case IC_VEX_W_XS:
|
Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
llvm-svn: 191649
2013-09-30 02:46:36 +00:00
|
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|
return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
|
2011-09-02 04:17:54 +00:00
|
|
|
case IC_VEX_W_XD:
|
Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
llvm-svn: 191649
2013-09-30 02:46:36 +00:00
|
|
|
return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
|
2011-09-02 04:17:54 +00:00
|
|
|
case IC_VEX_W_OPSIZE:
|
Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
llvm-svn: 191649
2013-09-30 02:46:36 +00:00
|
|
|
return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
|
2011-03-15 01:23:15 +00:00
|
|
|
case IC_VEX_L:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_VEX_L_W);
|
2011-03-15 01:23:15 +00:00
|
|
|
case IC_VEX_L_XS:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_VEX_L_W_XS);
|
2011-03-15 01:23:15 +00:00
|
|
|
case IC_VEX_L_XD:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_VEX_L_W_XD);
|
2011-09-02 04:17:54 +00:00
|
|
|
case IC_VEX_L_OPSIZE:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_VEX_L_W:
|
|
|
|
|
case IC_VEX_L_W_XS:
|
|
|
|
|
case IC_VEX_L_W_XD:
|
2011-11-06 23:04:08 +00:00
|
|
|
case IC_VEX_L_W_OPSIZE:
|
2011-03-15 01:23:15 +00:00
|
|
|
return false;
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2));
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_XS:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XS)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XS)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XS)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS));
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_XD:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XD)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XD)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XD)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD));
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_OPSIZE:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE));
|
2023-12-15 16:03:17 +08:00
|
|
|
case IC_EVEX_OPSIZE_ADSIZE:
|
2024-01-25 22:24:43 -08:00
|
|
|
case IC_EVEX_XS_ADSIZE:
|
|
|
|
|
case IC_EVEX_XD_ADSIZE:
|
2023-12-15 16:03:17 +08:00
|
|
|
return false;
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_K)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_K)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_K)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_K));
|
|
|
|
|
case IC_EVEX_XS_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XS_K)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XS_K)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS_K)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS_K));
|
|
|
|
|
case IC_EVEX_XD_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XD_K)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XD_K)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD_K)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD_K));
|
|
|
|
|
case IC_EVEX_OPSIZE_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE_K)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE_K)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_K));
|
|
|
|
|
case IC_EVEX_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_KZ)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_KZ)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_KZ)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_KZ)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_KZ));
|
|
|
|
|
case IC_EVEX_XS_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XS_KZ)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS_KZ)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS_KZ));
|
|
|
|
|
case IC_EVEX_XD_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XD_KZ)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD_KZ)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD_KZ));
|
|
|
|
|
case IC_EVEX_OPSIZE_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE_KZ)) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE_KZ)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_KZ));
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_W:
|
2017-10-22 17:22:29 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W)) ||
|
2024-08-29 18:22:26 +08:00
|
|
|
inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
|
2017-10-22 17:22:29 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W));
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_W_XS:
|
2017-10-22 17:22:29 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS));
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_W_XD:
|
2017-10-22 17:22:29 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD));
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_W_OPSIZE:
|
2017-10-22 17:22:29 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE));
|
|
|
|
|
case IC_EVEX_W_K:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_K)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_K));
|
|
|
|
|
case IC_EVEX_W_XS_K:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_K)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K));
|
|
|
|
|
case IC_EVEX_W_XD_K:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD_K)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K));
|
|
|
|
|
case IC_EVEX_W_OPSIZE_K:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K));
|
|
|
|
|
case IC_EVEX_W_KZ:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_KZ)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_KZ));
|
|
|
|
|
case IC_EVEX_W_XS_KZ:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ));
|
|
|
|
|
case IC_EVEX_W_XD_KZ:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ));
|
|
|
|
|
case IC_EVEX_W_OPSIZE_KZ:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ));
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W);
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L_XS:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XS);
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L_XD:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XD);
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L_OPSIZE:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_K);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L_XS_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XS_K);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L_XD_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XD_K);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L_OPSIZE_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_KZ);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L_XS_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L_XD_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L_OPSIZE_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ);
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L_W:
|
|
|
|
|
case IC_EVEX_L_W_XS:
|
|
|
|
|
case IC_EVEX_L_W_XD:
|
|
|
|
|
case IC_EVEX_L_W_OPSIZE:
|
|
|
|
|
return false;
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L_W_K:
|
|
|
|
|
case IC_EVEX_L_W_XS_K:
|
|
|
|
|
case IC_EVEX_L_W_XD_K:
|
|
|
|
|
case IC_EVEX_L_W_OPSIZE_K:
|
|
|
|
|
return false;
|
|
|
|
|
case IC_EVEX_L_W_KZ:
|
|
|
|
|
case IC_EVEX_L_W_XS_KZ:
|
|
|
|
|
case IC_EVEX_L_W_XD_KZ:
|
|
|
|
|
case IC_EVEX_L_W_OPSIZE_KZ:
|
|
|
|
|
return false;
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L2:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W);
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L2_XS:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XS);
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L2_XD:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XD);
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L2_OPSIZE:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L2_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_K);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L2_XS_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L2_XD_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L2_OPSIZE_K:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L2_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_KZ);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L2_XS_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L2_XD_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ);
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L2_OPSIZE_KZ:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ);
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L2_W:
|
|
|
|
|
case IC_EVEX_L2_W_XS:
|
|
|
|
|
case IC_EVEX_L2_W_XD:
|
|
|
|
|
case IC_EVEX_L2_W_OPSIZE:
|
|
|
|
|
return false;
|
2017-10-22 17:22:29 +00:00
|
|
|
case IC_EVEX_L2_W_K:
|
|
|
|
|
case IC_EVEX_L2_W_XS_K:
|
|
|
|
|
case IC_EVEX_L2_W_XD_K:
|
|
|
|
|
case IC_EVEX_L2_W_OPSIZE_K:
|
|
|
|
|
return false;
|
|
|
|
|
case IC_EVEX_L2_W_KZ:
|
|
|
|
|
case IC_EVEX_L2_W_XS_KZ:
|
|
|
|
|
case IC_EVEX_L2_W_XD_KZ:
|
|
|
|
|
case IC_EVEX_L2_W_OPSIZE_KZ:
|
|
|
|
|
return false;
|
|
|
|
|
case IC_EVEX_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_B)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_B));
|
2015-03-01 07:44:04 +00:00
|
|
|
case IC_EVEX_XS_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XS_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_B)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XS_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS_B));
|
2015-03-01 07:44:04 +00:00
|
|
|
case IC_EVEX_XD_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XD_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_B)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XD_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD_B));
|
2014-01-13 12:55:03 +00:00
|
|
|
case IC_EVEX_OPSIZE_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_B)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_B));
|
|
|
|
|
case IC_EVEX_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_K_B)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_K_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_K_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_K_B));
|
|
|
|
|
case IC_EVEX_XS_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XS_K_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K_B)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XS_K_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS_K_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS_K_B));
|
|
|
|
|
case IC_EVEX_XD_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XD_K_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K_B)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XD_K_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD_K_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD_K_B));
|
2014-08-25 14:49:34 +00:00
|
|
|
case IC_EVEX_OPSIZE_K_B:
|
2023-12-07 20:58:04 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K_B)) ||
|
2023-04-20 11:07:18 +08:00
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE_K_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE_K_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_K_B));
|
|
|
|
|
case IC_EVEX_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_KZ_B)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_KZ_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_KZ_B));
|
|
|
|
|
case IC_EVEX_XS_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ_B)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XS_KZ_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XS_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XS_KZ_B));
|
|
|
|
|
case IC_EVEX_XD_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ_B)) ||
|
|
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_XD_KZ_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_XD_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_XD_KZ_B));
|
2014-10-09 08:38:48 +00:00
|
|
|
case IC_EVEX_OPSIZE_KZ_B:
|
2023-12-07 20:58:04 +08:00
|
|
|
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ_B)) ||
|
2023-04-20 11:07:18 +08:00
|
|
|
(WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE_KZ_B)) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_KZ_B));
|
2015-07-13 13:26:20 +00:00
|
|
|
case IC_EVEX_W_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_B)) ||
|
2024-08-29 18:22:26 +08:00
|
|
|
inheritsFrom(child, IC_EVEX_W_OPSIZE_B) ||
|
2017-10-23 02:26:24 +00:00
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_B));
|
2015-03-01 07:44:04 +00:00
|
|
|
case IC_EVEX_W_XS_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS_B));
|
2015-03-01 07:44:04 +00:00
|
|
|
case IC_EVEX_W_XD_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD_B));
|
|
|
|
|
case IC_EVEX_W_OPSIZE_B:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_B));
|
|
|
|
|
case IC_EVEX_W_K_B:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_K_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_K_B));
|
2015-03-01 07:44:04 +00:00
|
|
|
case IC_EVEX_W_XS_K_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_K_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K_B));
|
2015-03-01 07:44:04 +00:00
|
|
|
case IC_EVEX_W_XD_K_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD_K_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K_B));
|
|
|
|
|
case IC_EVEX_W_OPSIZE_K_B:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K_B));
|
|
|
|
|
case IC_EVEX_W_KZ_B:
|
|
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_KZ_B));
|
2015-03-01 07:44:04 +00:00
|
|
|
case IC_EVEX_W_XS_KZ_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ_B));
|
2015-03-01 07:44:04 +00:00
|
|
|
case IC_EVEX_W_XD_KZ_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ_B));
|
2014-10-09 08:38:48 +00:00
|
|
|
case IC_EVEX_W_OPSIZE_KZ_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ_B)) ||
|
|
|
|
|
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ_B));
|
|
|
|
|
case IC_EVEX_L_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_B);
|
2015-04-21 13:13:46 +00:00
|
|
|
case IC_EVEX_L_XS_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XS_B);
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L_XD_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XD_B);
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L_OPSIZE_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_B);
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_K_B);
|
2015-04-21 13:13:46 +00:00
|
|
|
case IC_EVEX_L_XS_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XS_K_B);
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L_XD_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XD_K_B);
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L_OPSIZE_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_K_B);
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_KZ_B);
|
2015-07-13 13:26:20 +00:00
|
|
|
case IC_EVEX_L_XS_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XS_KZ_B);
|
2015-07-13 13:26:20 +00:00
|
|
|
case IC_EVEX_L_XD_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_XD_KZ_B);
|
2014-10-09 08:38:48 +00:00
|
|
|
case IC_EVEX_L_OPSIZE_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L_W_OPSIZE_KZ_B);
|
2015-07-13 13:26:20 +00:00
|
|
|
case IC_EVEX_L_W_B:
|
2015-04-21 13:13:46 +00:00
|
|
|
case IC_EVEX_L_W_XS_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L_W_XD_B:
|
2014-08-25 14:49:34 +00:00
|
|
|
case IC_EVEX_L_W_OPSIZE_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return false;
|
|
|
|
|
case IC_EVEX_L_W_K_B:
|
|
|
|
|
case IC_EVEX_L_W_XS_K_B:
|
|
|
|
|
case IC_EVEX_L_W_XD_K_B:
|
2014-08-25 14:49:34 +00:00
|
|
|
case IC_EVEX_L_W_OPSIZE_K_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return false;
|
2015-07-13 13:26:20 +00:00
|
|
|
case IC_EVEX_L_W_KZ_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L_W_XS_KZ_B:
|
2015-07-13 13:26:20 +00:00
|
|
|
case IC_EVEX_L_W_XD_KZ_B:
|
2014-10-09 08:38:48 +00:00
|
|
|
case IC_EVEX_L_W_OPSIZE_KZ_B:
|
2013-07-28 08:28:38 +00:00
|
|
|
return false;
|
|
|
|
|
case IC_EVEX_L2_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_B);
|
2014-01-01 15:12:34 +00:00
|
|
|
case IC_EVEX_L2_XS_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_B);
|
2014-01-01 15:12:34 +00:00
|
|
|
case IC_EVEX_L2_XD_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_B);
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L2_OPSIZE_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_B);
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L2_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_K_B);
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L2_XS_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_K_B);
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L2_XD_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_K_B);
|
2013-11-03 13:46:31 +00:00
|
|
|
case IC_EVEX_L2_OPSIZE_K_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_K_B);
|
2017-10-23 02:26:24 +00:00
|
|
|
case IC_EVEX_L2_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_KZ_B);
|
2015-07-13 13:26:20 +00:00
|
|
|
case IC_EVEX_L2_XS_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XS_KZ_B);
|
2015-07-13 13:26:20 +00:00
|
|
|
case IC_EVEX_L2_XD_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_XD_KZ_B);
|
2013-11-03 13:46:31 +00:00
|
|
|
case IC_EVEX_L2_OPSIZE_KZ_B:
|
2023-04-20 11:07:18 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_L2_W_OPSIZE_KZ_B);
|
2013-11-03 13:46:31 +00:00
|
|
|
case IC_EVEX_L2_W_B:
|
2015-04-21 13:13:46 +00:00
|
|
|
case IC_EVEX_L2_W_XS_B:
|
2014-01-01 15:12:34 +00:00
|
|
|
case IC_EVEX_L2_W_XD_B:
|
2013-07-28 08:28:38 +00:00
|
|
|
case IC_EVEX_L2_W_OPSIZE_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return false;
|
|
|
|
|
case IC_EVEX_L2_W_K_B:
|
|
|
|
|
case IC_EVEX_L2_W_XS_K_B:
|
|
|
|
|
case IC_EVEX_L2_W_XD_K_B:
|
2013-11-03 13:46:31 +00:00
|
|
|
case IC_EVEX_L2_W_OPSIZE_K_B:
|
2017-10-23 02:26:24 +00:00
|
|
|
return false;
|
|
|
|
|
case IC_EVEX_L2_W_KZ_B:
|
2015-07-13 13:26:20 +00:00
|
|
|
case IC_EVEX_L2_W_XS_KZ_B:
|
|
|
|
|
case IC_EVEX_L2_W_XD_KZ_B:
|
2013-11-03 13:46:31 +00:00
|
|
|
case IC_EVEX_L2_W_OPSIZE_KZ_B:
|
2013-07-28 08:28:38 +00:00
|
|
|
return false;
|
2023-12-28 21:22:03 +08:00
|
|
|
case IC_EVEX_NF:
|
2024-02-29 11:44:41 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_W_NF);
|
2023-12-28 21:22:03 +08:00
|
|
|
case IC_EVEX_B_NF:
|
2024-02-29 11:44:41 +08:00
|
|
|
return WIG && inheritsFrom(child, IC_EVEX_W_B_NF);
|
2023-12-28 21:22:03 +08:00
|
|
|
case IC_EVEX_OPSIZE_NF:
|
|
|
|
|
case IC_EVEX_OPSIZE_B_NF:
|
|
|
|
|
case IC_EVEX_W_NF:
|
|
|
|
|
case IC_EVEX_W_B_NF:
|
|
|
|
|
return false;
|
2024-08-03 09:26:07 +08:00
|
|
|
case IC_EVEX_B_U:
|
|
|
|
|
case IC_EVEX_XS_B_U:
|
|
|
|
|
case IC_EVEX_XD_B_U:
|
|
|
|
|
case IC_EVEX_OPSIZE_B_U:
|
|
|
|
|
case IC_EVEX_W_B_U:
|
|
|
|
|
case IC_EVEX_W_XS_B_U:
|
|
|
|
|
case IC_EVEX_W_XD_B_U:
|
|
|
|
|
case IC_EVEX_W_OPSIZE_B_U:
|
|
|
|
|
case IC_EVEX_K_B_U:
|
|
|
|
|
case IC_EVEX_XS_K_B_U:
|
|
|
|
|
case IC_EVEX_XD_K_B_U:
|
|
|
|
|
case IC_EVEX_OPSIZE_K_B_U:
|
|
|
|
|
case IC_EVEX_W_K_B_U:
|
|
|
|
|
case IC_EVEX_W_XS_K_B_U:
|
|
|
|
|
case IC_EVEX_W_XD_K_B_U:
|
|
|
|
|
case IC_EVEX_W_OPSIZE_K_B_U:
|
|
|
|
|
case IC_EVEX_KZ_B_U:
|
|
|
|
|
case IC_EVEX_XS_KZ_B_U:
|
|
|
|
|
case IC_EVEX_XD_KZ_B_U:
|
|
|
|
|
case IC_EVEX_OPSIZE_KZ_B_U:
|
|
|
|
|
case IC_EVEX_W_KZ_B_U:
|
|
|
|
|
case IC_EVEX_W_XS_KZ_B_U:
|
|
|
|
|
case IC_EVEX_W_XD_KZ_B_U:
|
|
|
|
|
case IC_EVEX_W_OPSIZE_KZ_B_U:
|
|
|
|
|
return false;
|
2009-12-19 02:59:52 +00:00
|
|
|
default:
|
2023-12-07 20:58:04 +08:00
|
|
|
errs() << "Unknown instruction class: "
|
|
|
|
|
<< stringForContext((InstructionContext)parent) << "\n";
|
2011-09-02 04:17:54 +00:00
|
|
|
llvm_unreachable("Unknown instruction class");
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// outranks - Indicates whether, if an instruction has two different applicable
|
|
|
|
|
/// classes, which class should be preferred when performing decode. This
|
|
|
|
|
/// imposes a total ordering (ties are resolved toward "lower")
|
|
|
|
|
///
|
|
|
|
|
/// @param upper - The class that may be preferable
|
|
|
|
|
/// @param lower - The class that may be less preferable
|
|
|
|
|
/// @return - True if upper is to be preferred, false otherwise.
|
2012-07-31 05:27:01 +00:00
|
|
|
static inline bool outranks(InstructionContext upper,
|
2009-12-19 02:59:52 +00:00
|
|
|
InstructionContext lower) {
|
|
|
|
|
assert(upper < IC_max);
|
|
|
|
|
assert(lower < IC_max);
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
#define ENUM_ENTRY(n, r, d) r,
|
2023-12-07 20:58:04 +08:00
|
|
|
#define ENUM_ENTRY_K_B(n, r, d) \
|
|
|
|
|
ENUM_ENTRY(n, r, d) \
|
|
|
|
|
ENUM_ENTRY(n##_K_B, r, d) \
|
|
|
|
|
ENUM_ENTRY(n##_KZ_B, r, d) \
|
|
|
|
|
ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
|
|
|
|
|
static int ranks[IC_max] = {INSTRUCTION_CONTEXTS};
|
2009-12-19 02:59:52 +00:00
|
|
|
#undef ENUM_ENTRY
|
2013-07-28 08:28:38 +00:00
|
|
|
#undef ENUM_ENTRY_K_B
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
return (ranks[upper] > ranks[lower]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// getDecisionType - Determines whether a ModRM decision with 255 entries can
|
|
|
|
|
/// be compacted by eliminating redundant information.
|
|
|
|
|
///
|
|
|
|
|
/// @param decision - The decision to be compacted.
|
|
|
|
|
/// @return - The compactest available representation for the decision.
|
2012-07-31 05:42:02 +00:00
|
|
|
static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
|
2009-12-19 02:59:52 +00:00
|
|
|
bool satisfiesOneEntry = true;
|
|
|
|
|
bool satisfiesSplitRM = true;
|
2012-02-09 08:58:07 +00:00
|
|
|
bool satisfiesSplitReg = true;
|
2012-09-13 05:45:42 +00:00
|
|
|
bool satisfiesSplitMisc = true;
|
2012-02-09 08:58:07 +00:00
|
|
|
|
2012-07-31 06:02:05 +00:00
|
|
|
for (unsigned index = 0; index < 256; ++index) {
|
2009-12-19 02:59:52 +00:00
|
|
|
if (decision.instructionIDs[index] != decision.instructionIDs[0])
|
|
|
|
|
satisfiesOneEntry = false;
|
2012-02-09 08:58:07 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
if (((index & 0xc0) == 0xc0) &&
|
2023-12-07 20:58:04 +08:00
|
|
|
(decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
|
2009-12-19 02:59:52 +00:00
|
|
|
satisfiesSplitRM = false;
|
2012-02-09 08:58:07 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
if (((index & 0xc0) != 0xc0) &&
|
2023-12-07 20:58:04 +08:00
|
|
|
(decision.instructionIDs[index] != decision.instructionIDs[0x00]))
|
2009-12-19 02:59:52 +00:00
|
|
|
satisfiesSplitRM = false;
|
2012-02-09 08:58:07 +00:00
|
|
|
|
2023-12-07 20:58:04 +08:00
|
|
|
if (((index & 0xc0) == 0xc0) && (decision.instructionIDs[index] !=
|
|
|
|
|
decision.instructionIDs[index & 0xf8]))
|
2012-02-09 08:58:07 +00:00
|
|
|
satisfiesSplitReg = false;
|
|
|
|
|
|
2023-12-07 20:58:04 +08:00
|
|
|
if (((index & 0xc0) != 0xc0) && (decision.instructionIDs[index] !=
|
|
|
|
|
decision.instructionIDs[index & 0x38]))
|
2012-09-13 05:45:42 +00:00
|
|
|
satisfiesSplitMisc = false;
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
2012-02-09 08:58:07 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
if (satisfiesOneEntry)
|
|
|
|
|
return MODRM_ONEENTRY;
|
2012-02-09 08:58:07 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
if (satisfiesSplitRM)
|
|
|
|
|
return MODRM_SPLITRM;
|
2012-02-09 08:58:07 +00:00
|
|
|
|
2012-09-13 05:45:42 +00:00
|
|
|
if (satisfiesSplitReg && satisfiesSplitMisc)
|
2012-02-09 08:58:07 +00:00
|
|
|
return MODRM_SPLITREG;
|
|
|
|
|
|
2012-09-13 05:45:42 +00:00
|
|
|
if (satisfiesSplitMisc)
|
|
|
|
|
return MODRM_SPLITMISC;
|
|
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
return MODRM_FULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// stringForDecisionType - Returns a statically-allocated string corresponding
|
|
|
|
|
/// to a particular decision type.
|
|
|
|
|
///
|
|
|
|
|
/// @param dt - The decision type.
|
2012-07-31 05:27:01 +00:00
|
|
|
/// @return - A pointer to the statically-allocated string (e.g.,
|
2009-12-19 02:59:52 +00:00
|
|
|
/// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
|
2023-12-07 20:58:04 +08:00
|
|
|
static const char *stringForDecisionType(ModRMDecisionType dt) {
|
|
|
|
|
#define ENUM_ENTRY(n) \
|
|
|
|
|
case n: \
|
|
|
|
|
return #n;
|
2009-12-19 02:59:52 +00:00
|
|
|
switch (dt) {
|
2023-12-07 20:58:04 +08:00
|
|
|
default:
|
|
|
|
|
llvm_unreachable("Unknown decision type");
|
2009-12-19 02:59:52 +00:00
|
|
|
MODRMTYPES
|
2012-07-31 05:27:01 +00:00
|
|
|
};
|
2009-12-19 02:59:52 +00:00
|
|
|
#undef ENUM_ENTRY
|
|
|
|
|
}
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
DisassemblerTables::DisassemblerTables() {
|
2022-09-06 18:06:58 -06:00
|
|
|
for (unsigned i = 0; i < std::size(Tables); i++)
|
2019-08-15 15:54:37 +00:00
|
|
|
Tables[i] = std::make_unique<ContextDecision>();
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
HasConflicts = false;
|
|
|
|
|
}
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2023-12-07 20:58:04 +08:00
|
|
|
DisassemblerTables::~DisassemblerTables() {}
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2012-07-31 05:42:02 +00:00
|
|
|
void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
|
2012-07-31 06:02:05 +00:00
|
|
|
unsigned &i1, unsigned &i2,
|
2013-09-30 06:23:19 +00:00
|
|
|
unsigned &ModRMTableNum,
|
2012-07-31 05:42:02 +00:00
|
|
|
ModRMDecision &decision) const {
|
2024-08-04 21:05:45 +08:00
|
|
|
static uint64_t sEntryNumber = 1;
|
2009-12-19 02:59:52 +00:00
|
|
|
ModRMDecisionType dt = getDecisionType(decision);
|
2012-02-09 07:45:30 +00:00
|
|
|
|
2020-01-11 16:27:25 -08:00
|
|
|
if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) {
|
|
|
|
|
// Empty table.
|
2020-04-25 19:13:16 -07:00
|
|
|
o2 << "{" << stringForDecisionType(dt) << ", 0}";
|
2009-12-19 02:59:52 +00:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-30 06:23:19 +00:00
|
|
|
std::vector<unsigned> ModRMDecision;
|
2012-02-09 07:45:30 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
switch (dt) {
|
2023-12-07 20:58:04 +08:00
|
|
|
default:
|
|
|
|
|
llvm_unreachable("Unknown decision type");
|
|
|
|
|
case MODRM_ONEENTRY:
|
|
|
|
|
ModRMDecision.push_back(decision.instructionIDs[0]);
|
|
|
|
|
break;
|
|
|
|
|
case MODRM_SPLITRM:
|
|
|
|
|
ModRMDecision.push_back(decision.instructionIDs[0x00]);
|
|
|
|
|
ModRMDecision.push_back(decision.instructionIDs[0xc0]);
|
|
|
|
|
break;
|
|
|
|
|
case MODRM_SPLITREG:
|
|
|
|
|
for (unsigned index = 0; index < 64; index += 8)
|
|
|
|
|
ModRMDecision.push_back(decision.instructionIDs[index]);
|
|
|
|
|
for (unsigned index = 0xc0; index < 256; index += 8)
|
|
|
|
|
ModRMDecision.push_back(decision.instructionIDs[index]);
|
|
|
|
|
break;
|
|
|
|
|
case MODRM_SPLITMISC:
|
|
|
|
|
for (unsigned index = 0; index < 64; index += 8)
|
|
|
|
|
ModRMDecision.push_back(decision.instructionIDs[index]);
|
|
|
|
|
for (unsigned index = 0xc0; index < 256; ++index)
|
|
|
|
|
ModRMDecision.push_back(decision.instructionIDs[index]);
|
|
|
|
|
break;
|
|
|
|
|
case MODRM_FULL:
|
|
|
|
|
for (unsigned short InstructionID : decision.instructionIDs)
|
|
|
|
|
ModRMDecision.push_back(InstructionID);
|
|
|
|
|
break;
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
2012-02-09 07:45:30 +00:00
|
|
|
|
2013-09-30 06:23:19 +00:00
|
|
|
unsigned &EntryNumber = ModRMTable[ModRMDecision];
|
|
|
|
|
if (EntryNumber == 0) {
|
|
|
|
|
EntryNumber = ModRMTableNum;
|
|
|
|
|
|
|
|
|
|
ModRMTableNum += ModRMDecision.size();
|
2020-04-25 19:13:16 -07:00
|
|
|
o1 << "/*Table" << EntryNumber << "*/\n";
|
2013-09-30 06:23:19 +00:00
|
|
|
i1++;
|
2021-05-06 18:36:52 +08:00
|
|
|
for (unsigned I : ModRMDecision) {
|
|
|
|
|
o1.indent(i1 * 2) << format("0x%hx", I) << ", /*"
|
|
|
|
|
<< InstructionSpecifiers[I].name << "*/\n";
|
2013-09-30 06:23:19 +00:00
|
|
|
}
|
|
|
|
|
i1--;
|
|
|
|
|
}
|
2012-02-09 07:45:30 +00:00
|
|
|
|
2020-04-25 19:13:16 -07:00
|
|
|
o2 << "{" << stringForDecisionType(dt) << ", " << EntryNumber << "}";
|
2012-02-09 07:45:30 +00:00
|
|
|
|
|
|
|
|
switch (dt) {
|
2023-12-07 20:58:04 +08:00
|
|
|
default:
|
|
|
|
|
llvm_unreachable("Unknown decision type");
|
|
|
|
|
case MODRM_ONEENTRY:
|
|
|
|
|
sEntryNumber += 1;
|
|
|
|
|
break;
|
|
|
|
|
case MODRM_SPLITRM:
|
|
|
|
|
sEntryNumber += 2;
|
|
|
|
|
break;
|
|
|
|
|
case MODRM_SPLITREG:
|
|
|
|
|
sEntryNumber += 16;
|
|
|
|
|
break;
|
|
|
|
|
case MODRM_SPLITMISC:
|
|
|
|
|
sEntryNumber += 8 + 64;
|
|
|
|
|
break;
|
|
|
|
|
case MODRM_FULL:
|
|
|
|
|
sEntryNumber += 256;
|
|
|
|
|
break;
|
2012-02-09 07:45:30 +00:00
|
|
|
}
|
|
|
|
|
|
2024-08-04 21:05:45 +08:00
|
|
|
// We assume that the index can fit into uint32_t.
|
|
|
|
|
assert(sEntryNumber < -1U &&
|
|
|
|
|
"Index into ModRMDecision is too large for uint32_t!");
|
2021-06-04 23:34:43 -07:00
|
|
|
(void)sEntryNumber;
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
|
|
|
|
|
2012-07-31 05:42:02 +00:00
|
|
|
void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
|
2012-07-31 06:02:05 +00:00
|
|
|
unsigned &i1, unsigned &i2,
|
2013-09-30 06:23:19 +00:00
|
|
|
unsigned &ModRMTableNum,
|
2020-01-11 16:27:25 -08:00
|
|
|
OpcodeDecision &opDecision) const {
|
|
|
|
|
o2 << "{";
|
|
|
|
|
++i2;
|
|
|
|
|
|
|
|
|
|
unsigned index;
|
|
|
|
|
for (index = 0; index < 256; ++index) {
|
|
|
|
|
auto &decision = opDecision.modRMDecisions[index];
|
|
|
|
|
ModRMDecisionType dt = getDecisionType(decision);
|
|
|
|
|
if (!(dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0))
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if (index == 256) {
|
|
|
|
|
// If all 256 entries are MODRM_ONEENTRY, omit output.
|
2022-09-03 11:17:47 -07:00
|
|
|
static_assert(MODRM_ONEENTRY == 0);
|
2020-01-11 16:27:25 -08:00
|
|
|
--i2;
|
|
|
|
|
o2 << "},\n";
|
|
|
|
|
} else {
|
|
|
|
|
o2 << " /* struct OpcodeDecision */ {\n";
|
|
|
|
|
for (index = 0; index < 256; ++index) {
|
|
|
|
|
o2.indent(i2);
|
|
|
|
|
|
2020-04-25 19:13:16 -07:00
|
|
|
o2 << "/*0x" << format("%02hhx", index) << "*/";
|
2020-01-11 16:27:25 -08:00
|
|
|
|
|
|
|
|
emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
|
|
|
|
|
opDecision.modRMDecisions[index]);
|
|
|
|
|
|
|
|
|
|
if (index < 255)
|
|
|
|
|
o2 << ",";
|
|
|
|
|
|
|
|
|
|
o2 << "\n";
|
|
|
|
|
}
|
|
|
|
|
o2.indent(i2) << "}\n";
|
|
|
|
|
--i2;
|
|
|
|
|
o2.indent(i2) << "},\n";
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2012-07-31 05:42:02 +00:00
|
|
|
void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
|
2012-07-31 06:02:05 +00:00
|
|
|
unsigned &i1, unsigned &i2,
|
2013-09-30 06:23:19 +00:00
|
|
|
unsigned &ModRMTableNum,
|
2012-07-31 05:42:02 +00:00
|
|
|
ContextDecision &decision,
|
2023-12-07 20:58:04 +08:00
|
|
|
const char *name) const {
|
|
|
|
|
o2.indent(i2) << "static const struct ContextDecision " << name
|
|
|
|
|
<< " = {{/* opcodeDecisions */\n";
|
2009-12-19 02:59:52 +00:00
|
|
|
i2++;
|
|
|
|
|
|
2012-07-31 06:02:05 +00:00
|
|
|
for (unsigned index = 0; index < IC_max; ++index) {
|
2020-04-25 19:13:16 -07:00
|
|
|
o2.indent(i2) << "/*";
|
2009-12-19 02:59:52 +00:00
|
|
|
o2 << stringForContext((InstructionContext)index);
|
2020-04-25 19:13:16 -07:00
|
|
|
o2 << "*/ ";
|
2009-12-19 02:59:52 +00:00
|
|
|
|
2013-09-30 06:23:19 +00:00
|
|
|
emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
|
|
|
|
|
decision.opcodeDecisions[index]);
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
i2--;
|
2020-04-25 19:13:16 -07:00
|
|
|
o2.indent(i2) << "}};"
|
|
|
|
|
<< "\n";
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
|
|
|
|
|
2012-07-31 06:02:05 +00:00
|
|
|
void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
|
|
|
|
|
unsigned &i) const {
|
2012-08-01 07:39:18 +00:00
|
|
|
unsigned NumInstructions = InstructionSpecifiers.size();
|
|
|
|
|
|
|
|
|
|
o << "static const struct OperandSpecifier x86OperandSets[]["
|
|
|
|
|
<< X86_MAX_OPERANDS << "] = {\n";
|
|
|
|
|
|
2023-12-07 20:58:04 +08:00
|
|
|
typedef SmallVector<std::pair<OperandEncoding, OperandType>, X86_MAX_OPERANDS>
|
|
|
|
|
OperandListTy;
|
2012-08-01 07:39:18 +00:00
|
|
|
std::map<OperandListTy, unsigned> OperandSets;
|
|
|
|
|
|
|
|
|
|
unsigned OperandSetNum = 0;
|
|
|
|
|
for (unsigned Index = 0; Index < NumInstructions; ++Index) {
|
|
|
|
|
OperandListTy OperandList;
|
|
|
|
|
|
2021-05-06 18:36:52 +08:00
|
|
|
for (auto Operand : InstructionSpecifiers[Index].operands) {
|
|
|
|
|
OperandEncoding Encoding = (OperandEncoding)Operand.encoding;
|
|
|
|
|
OperandType Type = (OperandType)Operand.type;
|
2024-02-14 13:16:20 +00:00
|
|
|
OperandList.push_back(std::pair(Encoding, Type));
|
2012-08-01 07:39:18 +00:00
|
|
|
}
|
|
|
|
|
unsigned &N = OperandSets[OperandList];
|
2023-12-07 20:58:04 +08:00
|
|
|
if (N != 0)
|
|
|
|
|
continue;
|
2012-08-01 07:39:18 +00:00
|
|
|
|
|
|
|
|
N = ++OperandSetNum;
|
|
|
|
|
|
|
|
|
|
o << " { /* " << (OperandSetNum - 1) << " */\n";
|
|
|
|
|
for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
|
2015-04-09 04:08:42 +00:00
|
|
|
const char *Encoding = stringForOperandEncoding(OperandList[i].first);
|
2023-12-07 20:58:04 +08:00
|
|
|
const char *Type = stringForOperandType(OperandList[i].second);
|
2015-04-09 04:08:42 +00:00
|
|
|
o << " { " << Encoding << ", " << Type << " },\n";
|
2012-08-01 07:39:18 +00:00
|
|
|
}
|
|
|
|
|
o << " },\n";
|
|
|
|
|
}
|
|
|
|
|
o << "};"
|
|
|
|
|
<< "\n\n";
|
|
|
|
|
|
2010-10-23 09:10:44 +00:00
|
|
|
o.indent(i * 2) << "static const struct InstructionSpecifier ";
|
|
|
|
|
o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
i++;
|
|
|
|
|
|
2012-08-01 07:39:18 +00:00
|
|
|
for (unsigned index = 0; index < NumInstructions; ++index) {
|
2015-04-09 04:08:46 +00:00
|
|
|
o.indent(i * 2) << "{ /* " << index << " */\n";
|
2009-12-19 02:59:52 +00:00
|
|
|
i++;
|
2012-03-04 02:16:41 +00:00
|
|
|
|
2012-08-01 07:39:18 +00:00
|
|
|
OperandListTy OperandList;
|
2021-05-06 18:36:52 +08:00
|
|
|
for (auto Operand : InstructionSpecifiers[index].operands) {
|
|
|
|
|
OperandEncoding Encoding = (OperandEncoding)Operand.encoding;
|
|
|
|
|
OperandType Type = (OperandType)Operand.type;
|
2024-02-14 13:16:20 +00:00
|
|
|
OperandList.push_back(std::pair(Encoding, Type));
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
2012-08-01 07:39:18 +00:00
|
|
|
o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2015-04-09 04:08:46 +00:00
|
|
|
o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */\n";
|
2009-12-19 02:59:52 +00:00
|
|
|
|
|
|
|
|
i--;
|
2015-04-09 04:08:46 +00:00
|
|
|
o.indent(i * 2) << "},\n";
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
i--;
|
|
|
|
|
o.indent(i * 2) << "};"
|
|
|
|
|
<< "\n";
|
|
|
|
|
}
|
|
|
|
|
|
2012-07-31 06:02:05 +00:00
|
|
|
void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
|
2023-12-07 20:58:04 +08:00
|
|
|
o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR "[" << ATTR_max
|
|
|
|
|
<< "] = {\n";
|
2009-12-19 02:59:52 +00:00
|
|
|
i++;
|
|
|
|
|
|
2019-06-13 22:15:25 +00:00
|
|
|
for (unsigned index = 0; index < ATTR_max; ++index) {
|
2009-12-19 02:59:52 +00:00
|
|
|
o.indent(i * 2);
|
|
|
|
|
|
2024-01-25 22:24:43 -08:00
|
|
|
if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_OPSIZE))
|
2023-12-15 16:03:17 +08:00
|
|
|
o << "IC_EVEX_OPSIZE_ADSIZE";
|
2024-01-25 22:24:43 -08:00
|
|
|
else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XD))
|
|
|
|
|
o << "IC_EVEX_XD_ADSIZE";
|
|
|
|
|
else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XS))
|
|
|
|
|
o << "IC_EVEX_XS_ADSIZE";
|
2023-12-28 21:22:03 +08:00
|
|
|
else if (index & ATTR_EVEXNF) {
|
|
|
|
|
o << "IC_EVEX";
|
|
|
|
|
if (index & ATTR_REXW)
|
|
|
|
|
o << "_W";
|
|
|
|
|
else if (index & ATTR_OPSIZE)
|
|
|
|
|
o << "_OPSIZE";
|
|
|
|
|
|
|
|
|
|
if (index & ATTR_EVEXB)
|
|
|
|
|
o << "_B";
|
|
|
|
|
|
|
|
|
|
o << "_NF";
|
|
|
|
|
} else if ((index & ATTR_EVEX) || (index & ATTR_VEX) ||
|
|
|
|
|
(index & ATTR_VEXL)) {
|
2019-06-13 22:15:25 +00:00
|
|
|
if (index & ATTR_EVEX)
|
|
|
|
|
o << "IC_EVEX";
|
|
|
|
|
else
|
|
|
|
|
o << "IC_VEX";
|
|
|
|
|
|
2024-08-03 09:26:07 +08:00
|
|
|
if ((index & ATTR_EVEXB) && (index & ATTR_EVEXU))
|
|
|
|
|
; // Ignore ATTR_VEXL and ATTR_EVEXL2 under YMM rounding.
|
|
|
|
|
else if ((index & ATTR_EVEX) && (index & ATTR_EVEXL2))
|
2013-12-25 11:40:51 +00:00
|
|
|
o << "_L2";
|
2019-06-13 22:15:25 +00:00
|
|
|
else if (index & ATTR_VEXL)
|
2013-12-25 11:40:51 +00:00
|
|
|
o << "_L";
|
2019-06-13 22:15:25 +00:00
|
|
|
|
2013-12-25 11:40:51 +00:00
|
|
|
if (index & ATTR_REXW)
|
|
|
|
|
o << "_W";
|
2019-06-13 22:15:25 +00:00
|
|
|
|
[X86] Fix handling of maskmovdqu in x32 differently
This reverts the functional changes of D103427 but keeps its tests, and
and reimplements the functionality by reusing the existing 32-bit
MASKMOVDQU and VMASKMOVDQU instructions as suggested by skan in review.
These instructions were previously predicated on Not64BitMode. This
reimplementation restores the disassembly of a class of instructions,
which will see a test added in followup patch D122449.
These instructions are in 64-bit mode special cased in
X86MCInstLower::Lower, because we use flags with one meaning for subtly
different things: we have an AdSize32 class which indicates both that
the instruction needs a 0x67 prefix and that the text form of the
instruction implies a 0x67 prefix. These instructions are special in
needing a 0x67 prefix but having a text form that does *not* imply a
0x67 prefix, so we encode this in MCInst as an instruction that has an
explicit address size override.
Note that originally VMASKMOVDQU64 was special cased to be excluded from
disassembly, as we cannot distinguish between VMASKMOVDQU and
VMASKMOVDQU64 and rely on the fact that these are indistinguishable, or
close enough to it, at the MCInst level that it does not matter which we
use. Because VMASKMOVDQU now receives special casing, even though it
does not make a difference in the current implementation, as a
precaution VMASKMOVDQU is excluded from disassembly rather than
VMASKMOVDQU64.
Reviewed By: RKSimon, skan
Differential Revision: https://reviews.llvm.org/D122540
2022-04-12 18:32:14 +01:00
|
|
|
if (index & ATTR_OPSIZE)
|
2013-12-25 11:40:51 +00:00
|
|
|
o << "_OPSIZE";
|
[X86] Fix handling of maskmovdqu in x32 differently
This reverts the functional changes of D103427 but keeps its tests, and
and reimplements the functionality by reusing the existing 32-bit
MASKMOVDQU and VMASKMOVDQU instructions as suggested by skan in review.
These instructions were previously predicated on Not64BitMode. This
reimplementation restores the disassembly of a class of instructions,
which will see a test added in followup patch D122449.
These instructions are in 64-bit mode special cased in
X86MCInstLower::Lower, because we use flags with one meaning for subtly
different things: we have an AdSize32 class which indicates both that
the instruction needs a 0x67 prefix and that the text form of the
instruction implies a 0x67 prefix. These instructions are special in
needing a 0x67 prefix but having a text form that does *not* imply a
0x67 prefix, so we encode this in MCInst as an instruction that has an
explicit address size override.
Note that originally VMASKMOVDQU64 was special cased to be excluded from
disassembly, as we cannot distinguish between VMASKMOVDQU and
VMASKMOVDQU64 and rely on the fact that these are indistinguishable, or
close enough to it, at the MCInst level that it does not matter which we
use. Because VMASKMOVDQU now receives special casing, even though it
does not make a difference in the current implementation, as a
precaution VMASKMOVDQU is excluded from disassembly rather than
VMASKMOVDQU64.
Reviewed By: RKSimon, skan
Differential Revision: https://reviews.llvm.org/D122540
2022-04-12 18:32:14 +01:00
|
|
|
else if (index & ATTR_XD)
|
2013-12-25 11:40:51 +00:00
|
|
|
o << "_XD";
|
|
|
|
|
else if (index & ATTR_XS)
|
|
|
|
|
o << "_XS";
|
2019-06-13 22:15:25 +00:00
|
|
|
|
2023-12-15 16:03:17 +08:00
|
|
|
if (index & ATTR_EVEX) {
|
2019-06-13 22:15:25 +00:00
|
|
|
if (index & ATTR_EVEXKZ)
|
|
|
|
|
o << "_KZ";
|
|
|
|
|
else if (index & ATTR_EVEXK)
|
|
|
|
|
o << "_K";
|
|
|
|
|
|
|
|
|
|
if (index & ATTR_EVEXB)
|
|
|
|
|
o << "_B";
|
2024-08-03 09:26:07 +08:00
|
|
|
|
|
|
|
|
if ((index & ATTR_EVEXB) && (index & ATTR_EVEXU))
|
|
|
|
|
o << "_U";
|
2019-06-13 22:15:25 +00:00
|
|
|
}
|
2023-12-07 20:58:04 +08:00
|
|
|
} else if ((index & ATTR_64BIT) && (index & ATTR_REX2))
|
2023-11-22 10:26:23 +08:00
|
|
|
o << "IC_64BIT_REX2";
|
[X86] Fix handling of maskmovdqu in x32 differently
This reverts the functional changes of D103427 but keeps its tests, and
and reimplements the functionality by reusing the existing 32-bit
MASKMOVDQU and VMASKMOVDQU instructions as suggested by skan in review.
These instructions were previously predicated on Not64BitMode. This
reimplementation restores the disassembly of a class of instructions,
which will see a test added in followup patch D122449.
These instructions are in 64-bit mode special cased in
X86MCInstLower::Lower, because we use flags with one meaning for subtly
different things: we have an AdSize32 class which indicates both that
the instruction needs a 0x67 prefix and that the text form of the
instruction implies a 0x67 prefix. These instructions are special in
needing a 0x67 prefix but having a text form that does *not* imply a
0x67 prefix, so we encode this in MCInst as an instruction that has an
explicit address size override.
Note that originally VMASKMOVDQU64 was special cased to be excluded from
disassembly, as we cannot distinguish between VMASKMOVDQU and
VMASKMOVDQU64 and rely on the fact that these are indistinguishable, or
close enough to it, at the MCInst level that it does not matter which we
use. Because VMASKMOVDQU now receives special casing, even though it
does not make a difference in the current implementation, as a
precaution VMASKMOVDQU is excluded from disassembly rather than
VMASKMOVDQU64.
Reviewed By: RKSimon, skan
Differential Revision: https://reviews.llvm.org/D122540
2022-04-12 18:32:14 +01:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
|
2009-12-19 02:59:52 +00:00
|
|
|
o << "IC_64BIT_REXW_XS";
|
|
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
|
|
|
|
|
o << "IC_64BIT_REXW_XD";
|
2012-07-31 05:27:01 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
|
2009-12-19 02:59:52 +00:00
|
|
|
(index & ATTR_OPSIZE))
|
|
|
|
|
o << "IC_64BIT_REXW_OPSIZE";
|
2015-01-03 00:00:20 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
|
|
|
|
|
(index & ATTR_ADSIZE))
|
|
|
|
|
o << "IC_64BIT_REXW_ADSIZE";
|
2011-10-01 19:54:56 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
|
|
|
|
|
o << "IC_64BIT_XD_OPSIZE";
|
2018-04-05 18:20:14 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_ADSIZE))
|
|
|
|
|
o << "IC_64BIT_XD_ADSIZE";
|
2011-10-11 04:34:23 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
|
|
|
|
|
o << "IC_64BIT_XS_OPSIZE";
|
2018-04-05 18:20:14 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_ADSIZE))
|
|
|
|
|
o << "IC_64BIT_XS_ADSIZE";
|
2009-12-19 02:59:52 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_XS))
|
|
|
|
|
o << "IC_64BIT_XS";
|
|
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_XD))
|
|
|
|
|
o << "IC_64BIT_XD";
|
2014-12-31 07:07:31 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE) &&
|
|
|
|
|
(index & ATTR_ADSIZE))
|
|
|
|
|
o << "IC_64BIT_OPSIZE_ADSIZE";
|
2009-12-19 02:59:52 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
|
|
|
|
|
o << "IC_64BIT_OPSIZE";
|
2012-02-27 01:54:29 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
|
|
|
|
|
o << "IC_64BIT_ADSIZE";
|
2009-12-19 02:59:52 +00:00
|
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
|
|
|
|
|
o << "IC_64BIT_REXW";
|
|
|
|
|
else if ((index & ATTR_64BIT))
|
|
|
|
|
o << "IC_64BIT";
|
2011-10-11 04:34:23 +00:00
|
|
|
else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
|
|
|
|
|
o << "IC_XS_OPSIZE";
|
2011-10-01 19:54:56 +00:00
|
|
|
else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
|
|
|
|
|
o << "IC_XD_OPSIZE";
|
2018-04-05 18:20:14 +00:00
|
|
|
else if ((index & ATTR_XS) && (index & ATTR_ADSIZE))
|
|
|
|
|
o << "IC_XS_ADSIZE";
|
|
|
|
|
else if ((index & ATTR_XD) && (index & ATTR_ADSIZE))
|
|
|
|
|
o << "IC_XD_ADSIZE";
|
2009-12-19 02:59:52 +00:00
|
|
|
else if (index & ATTR_XS)
|
|
|
|
|
o << "IC_XS";
|
|
|
|
|
else if (index & ATTR_XD)
|
|
|
|
|
o << "IC_XD";
|
2014-12-31 07:07:31 +00:00
|
|
|
else if ((index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
|
|
|
|
|
o << "IC_OPSIZE_ADSIZE";
|
2009-12-19 02:59:52 +00:00
|
|
|
else if (index & ATTR_OPSIZE)
|
|
|
|
|
o << "IC_OPSIZE";
|
2012-02-27 01:54:29 +00:00
|
|
|
else if (index & ATTR_ADSIZE)
|
|
|
|
|
o << "IC_ADSIZE";
|
2009-12-19 02:59:52 +00:00
|
|
|
else
|
|
|
|
|
o << "IC";
|
|
|
|
|
|
2020-04-25 19:13:16 -07:00
|
|
|
o << ", // " << index << "\n";
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
i--;
|
|
|
|
|
o.indent(i * 2) << "};"
|
|
|
|
|
<< "\n";
|
|
|
|
|
}
|
|
|
|
|
|
2012-07-31 05:42:02 +00:00
|
|
|
void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
|
2013-09-30 06:23:19 +00:00
|
|
|
unsigned &i1, unsigned &i2,
|
|
|
|
|
unsigned &ModRMTableNum) const {
|
|
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
|
|
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
|
2023-12-07 20:58:04 +08:00
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2],
|
|
|
|
|
THREEBYTE38_STR);
|
|
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3],
|
|
|
|
|
THREEBYTE3A_STR);
|
2014-02-19 05:34:21 +00:00
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR);
|
|
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR);
|
|
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR);
|
2023-12-07 20:58:04 +08:00
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7],
|
|
|
|
|
THREEDNOW_MAP_STR);
|
2023-11-24 12:29:56 +08:00
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], MAP4_STR);
|
|
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[9], MAP5_STR);
|
|
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[10], MAP6_STR);
|
|
|
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[11], MAP7_STR);
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void DisassemblerTables::emit(raw_ostream &o) const {
|
2012-07-31 06:02:05 +00:00
|
|
|
unsigned i1 = 0;
|
|
|
|
|
unsigned i2 = 0;
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
std::string s1;
|
|
|
|
|
std::string s2;
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
raw_string_ostream o1(s1);
|
|
|
|
|
raw_string_ostream o2(s2);
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2009-12-19 02:59:52 +00:00
|
|
|
emitInstructionInfo(o, i2);
|
|
|
|
|
o << "\n";
|
|
|
|
|
|
|
|
|
|
emitContextTable(o, i2);
|
|
|
|
|
o << "\n";
|
2012-02-09 07:45:30 +00:00
|
|
|
|
2013-09-30 06:23:19 +00:00
|
|
|
unsigned ModRMTableNum = 0;
|
|
|
|
|
|
2012-02-09 07:45:30 +00:00
|
|
|
o << "static const InstrUID modRMTable[] = {\n";
|
|
|
|
|
i1++;
|
2013-09-30 06:23:19 +00:00
|
|
|
std::vector<unsigned> EmptyTable(1, 0);
|
|
|
|
|
ModRMTable[EmptyTable] = ModRMTableNum;
|
|
|
|
|
ModRMTableNum += EmptyTable.size();
|
2020-04-25 19:13:16 -07:00
|
|
|
o1 << "/*EmptyTable*/\n";
|
2013-09-30 06:23:19 +00:00
|
|
|
o1.indent(i1 * 2) << "0x0,\n";
|
2012-02-09 07:45:30 +00:00
|
|
|
i1--;
|
2013-09-30 06:23:19 +00:00
|
|
|
emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
|
2012-02-09 07:45:30 +00:00
|
|
|
|
2024-07-05 16:36:19 -05:00
|
|
|
o << s1;
|
2012-02-09 07:45:30 +00:00
|
|
|
o << " 0x0\n";
|
|
|
|
|
o << "};\n";
|
2009-12-19 02:59:52 +00:00
|
|
|
o << "\n";
|
2024-07-05 16:36:19 -05:00
|
|
|
o << s2;
|
2009-12-19 02:59:52 +00:00
|
|
|
o << "\n";
|
|
|
|
|
o << "\n";
|
|
|
|
|
}
|
|
|
|
|
|
2023-12-07 20:58:04 +08:00
|
|
|
void DisassemblerTables::setTableFields(ModRMDecision &decision,
|
|
|
|
|
const ModRMFilter &filter, InstrUID uid,
|
|
|
|
|
uint8_t opcode) {
|
2012-07-31 06:02:05 +00:00
|
|
|
for (unsigned index = 0; index < 256; ++index) {
|
2009-12-19 02:59:52 +00:00
|
|
|
if (filter.accepts(index)) {
|
|
|
|
|
if (decision.instructionIDs[index] == uid)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (decision.instructionIDs[index] != 0) {
|
2023-12-07 20:58:04 +08:00
|
|
|
InstructionSpecifier &newInfo = InstructionSpecifiers[uid];
|
2009-12-19 02:59:52 +00:00
|
|
|
InstructionSpecifier &previousInfo =
|
2023-12-07 20:58:04 +08:00
|
|
|
InstructionSpecifiers[decision.instructionIDs[index]];
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2023-12-07 20:58:04 +08:00
|
|
|
if (previousInfo.name == "NOOP" &&
|
|
|
|
|
(newInfo.name == "XCHG16ar" || newInfo.name == "XCHG32ar" ||
|
|
|
|
|
newInfo.name == "XCHG64ar"))
|
2011-09-11 20:23:20 +00:00
|
|
|
continue; // special case for XCHG*ar and NOOP
|
2009-12-19 02:59:52 +00:00
|
|
|
|
|
|
|
|
if (outranks(previousInfo.insnContext, newInfo.insnContext))
|
|
|
|
|
continue;
|
2012-07-31 05:27:01 +00:00
|
|
|
|
2014-02-13 07:07:16 +00:00
|
|
|
if (previousInfo.insnContext == newInfo.insnContext) {
|
2009-12-19 02:59:52 +00:00
|
|
|
errs() << "Error: Primary decode conflict: ";
|
|
|
|
|
errs() << newInfo.name << " would overwrite " << previousInfo.name;
|
|
|
|
|
errs() << "\n";
|
|
|
|
|
errs() << "ModRM " << index << "\n";
|
|
|
|
|
errs() << "Opcode " << (uint16_t)opcode << "\n";
|
|
|
|
|
errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
|
|
|
|
|
HasConflicts = true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
decision.instructionIDs[index] = uid;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-12-07 20:58:04 +08:00
|
|
|
void DisassemblerTables::setTableFields(
|
|
|
|
|
OpcodeType type, InstructionContext insnContext, uint8_t opcode,
|
|
|
|
|
const ModRMFilter &filter, InstrUID uid, bool is32bit, bool noPrefix,
|
|
|
|
|
bool ignoresVEX_L, bool ignoresW, unsigned addressSize) {
|
2009-12-19 02:59:52 +00:00
|
|
|
ContextDecision &decision = *Tables[type];
|
|
|
|
|
|
2012-07-31 06:02:05 +00:00
|
|
|
for (unsigned index = 0; index < IC_max; ++index) {
|
2015-01-02 07:02:25 +00:00
|
|
|
if ((is32bit || addressSize == 16) &&
|
|
|
|
|
inheritsFrom((InstructionContext)index, IC_64BIT))
|
2011-09-23 06:57:25 +00:00
|
|
|
continue;
|
|
|
|
|
|
2015-01-02 07:02:25 +00:00
|
|
|
bool adSize64 = addressSize == 64;
|
2012-07-31 05:27:01 +00:00
|
|
|
if (inheritsFrom((InstructionContext)index,
|
2017-10-23 16:49:26 +00:00
|
|
|
InstructionSpecifiers[uid].insnContext, noPrefix,
|
2023-04-20 11:07:18 +08:00
|
|
|
ignoresVEX_L, ignoresW, adSize64))
|
2012-07-31 05:27:01 +00:00
|
|
|
setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],
|
2023-12-07 20:58:04 +08:00
|
|
|
filter, uid, opcode);
|
2009-12-19 02:59:52 +00:00
|
|
|
}
|
|
|
|
|
}
|