2003-10-13 03:32:08 +00:00
|
|
|
//===-- Instruction.cpp - Implement the Instruction class -----------------===//
|
2005-04-21 23:48:37 +00:00
|
|
|
//
|
2019-01-19 08:50:56 +00:00
|
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2005-04-21 23:48:37 +00:00
|
|
|
//
|
2003-10-20 19:43:21 +00:00
|
|
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//===----------------------------------------------------------------------===//
|
2001-06-06 20:29:01 +00:00
|
|
|
//
|
2013-01-02 09:10:48 +00:00
|
|
|
// This file implements the Instruction class for the IR library.
|
2001-06-06 20:29:01 +00:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2013-01-02 11:36:10 +00:00
|
|
|
#include "llvm/IR/Instruction.h"
|
2017-06-06 11:49:48 +00:00
|
|
|
#include "llvm/ADT/DenseSet.h"
|
Only guard loop metadata that has non-debug info in it (#118825)
This PR is motivated by a mismatch we discovered between compilation
results with vs. without `-g3`. We noticed this when compiling SPEC2017
testcases. The specific instance we saw is fixed in this PR by modifying
a guard (see below), but it is likely similar instances exist elsewhere
in the codebase.
The specific case fixed in this PR manifests itself in the `SimplifyCFG`
pass doing different things depending on whether DebugInfo is generated
or not. At the end of this comment, there is reduced example code that
shows the behavior in question.
The differing behavior has two root causes:
1. Commit https://github.com/llvm/llvm-project/commit/c07e19b adds loop
metadata including debug locations to loops that otherwise would not
have loop metadata
2. Commit https://github.com/llvm/llvm-project/commit/ac28efa6c100 adds
a guard to a simplification action in `SImplifyCFG` that prevents it
from simplifying away loop metadata
So, the change in 2. does not consider that when compiling with debug
symbols, loops that otherwise would not have metadata that needs
preserving, now have debug locations in their loop metadata. Thus, with
`-g3`, `SimplifyCFG` behaves differently than without it.
The larger issue is that while debug info is not supposed to influence
the final compilation result, commits like 1. blur the line between what
is and is not debug info, and not all optimization passes account for
this.
This PR does not address that and rather just modifies this particular
guard in order to restore equivalent behavior between debug and
non-debug builds in this one instance.
---
Here is a reduced version of a file from `f526.blender_r` that showcases
the behavior in question:
```C
struct LinkNode;
typedef struct LinkNode {
struct LinkNode *next;
void *link;
} LinkNode;
void do_projectpaint_thread_ph_v_state() {
int *ps = do_projectpaint_thread_ph_v_state;
LinkNode *node;
while (do_projectpaint_thread_ph_v_state)
for (node = ps; node; node = node->next)
;
}
```
Compiling this with and without DebugInfo, and then disassembling the
results, leads to different outcomes (tested on SystemZ and X86). The
reason for this is that the `SimplifyCFG` pass does different things in
either case.
2024-12-20 15:15:51 +01:00
|
|
|
#include "llvm/ADT/STLExtras.h"
|
2023-06-25 18:04:47 +01:00
|
|
|
#include "llvm/IR/AttributeMask.h"
|
2024-04-18 08:27:36 +02:00
|
|
|
#include "llvm/IR/Attributes.h"
|
2013-01-02 11:36:10 +00:00
|
|
|
#include "llvm/IR/Constants.h"
|
2024-04-18 08:27:36 +02:00
|
|
|
#include "llvm/IR/InstrTypes.h"
|
2013-01-02 11:36:10 +00:00
|
|
|
#include "llvm/IR/Instructions.h"
|
2021-03-29 17:02:41 -07:00
|
|
|
#include "llvm/IR/IntrinsicInst.h"
|
|
|
|
#include "llvm/IR/Intrinsics.h"
|
Only guard loop metadata that has non-debug info in it (#118825)
This PR is motivated by a mismatch we discovered between compilation
results with vs. without `-g3`. We noticed this when compiling SPEC2017
testcases. The specific instance we saw is fixed in this PR by modifying
a guard (see below), but it is likely similar instances exist elsewhere
in the codebase.
The specific case fixed in this PR manifests itself in the `SimplifyCFG`
pass doing different things depending on whether DebugInfo is generated
or not. At the end of this comment, there is reduced example code that
shows the behavior in question.
The differing behavior has two root causes:
1. Commit https://github.com/llvm/llvm-project/commit/c07e19b adds loop
metadata including debug locations to loops that otherwise would not
have loop metadata
2. Commit https://github.com/llvm/llvm-project/commit/ac28efa6c100 adds
a guard to a simplification action in `SImplifyCFG` that prevents it
from simplifying away loop metadata
So, the change in 2. does not consider that when compiling with debug
symbols, loops that otherwise would not have metadata that needs
preserving, now have debug locations in their loop metadata. Thus, with
`-g3`, `SimplifyCFG` behaves differently than without it.
The larger issue is that while debug info is not supposed to influence
the final compilation result, commits like 1. blur the line between what
is and is not debug info, and not all optimization passes account for
this.
This PR does not address that and rather just modifies this particular
guard in order to restore equivalent behavior between debug and
non-debug builds in this one instance.
---
Here is a reduced version of a file from `f526.blender_r` that showcases
the behavior in question:
```C
struct LinkNode;
typedef struct LinkNode {
struct LinkNode *next;
void *link;
} LinkNode;
void do_projectpaint_thread_ph_v_state() {
int *ps = do_projectpaint_thread_ph_v_state;
LinkNode *node;
while (do_projectpaint_thread_ph_v_state)
for (node = ps; node; node = node->next)
;
}
```
Compiling this with and without DebugInfo, and then disassembling the
results, leads to different outcomes (tested on SystemZ and X86). The
reason for this is that the `SimplifyCFG` pass does different things in
either case.
2024-12-20 15:15:51 +01:00
|
|
|
#include "llvm/IR/LLVMContext.h"
|
2024-04-24 08:52:25 +02:00
|
|
|
#include "llvm/IR/MemoryModelRelaxationAnnotations.h"
|
2024-06-27 16:38:15 +02:00
|
|
|
#include "llvm/IR/Module.h"
|
2013-01-02 11:36:10 +00:00
|
|
|
#include "llvm/IR/Operator.h"
|
2023-01-19 12:04:53 +01:00
|
|
|
#include "llvm/IR/ProfDataUtils.h"
|
2013-01-02 11:36:10 +00:00
|
|
|
#include "llvm/IR/Type.h"
|
2003-11-20 17:45:12 +00:00
|
|
|
using namespace llvm;
|
2003-11-11 22:41:34 +00:00
|
|
|
|
2024-06-20 10:27:55 +01:00
|
|
|
InsertPosition::InsertPosition(Instruction *InsertBefore)
|
|
|
|
: InsertAt(InsertBefore ? InsertBefore->getIterator()
|
|
|
|
: InstListType::iterator()) {}
|
|
|
|
InsertPosition::InsertPosition(BasicBlock *InsertAtEnd)
|
|
|
|
: InsertAt(InsertAtEnd ? InsertAtEnd->end() : InstListType::iterator()) {}
|
2024-02-26 12:32:42 +00:00
|
|
|
|
2024-09-11 11:34:26 -07:00
|
|
|
Instruction::Instruction(Type *ty, unsigned it, AllocInfo AllocInfo,
|
2024-06-20 10:27:55 +01:00
|
|
|
InsertPosition InsertBefore)
|
2024-09-11 11:34:26 -07:00
|
|
|
: User(ty, Value::InstructionVal + it, AllocInfo) {
|
2024-06-20 10:27:55 +01:00
|
|
|
// When called with an iterator, there must be a block to insert into.
|
|
|
|
if (InstListType::iterator InsertIt = InsertBefore; InsertIt.isValid()) {
|
|
|
|
BasicBlock *BB = InsertIt.getNodeParent();
|
2015-06-15 17:03:35 +00:00
|
|
|
assert(BB && "Instruction to insert before is not in a basic block!");
|
2024-06-20 10:27:55 +01:00
|
|
|
insertInto(BB, InsertBefore);
|
2002-09-10 15:45:53 +00:00
|
|
|
}
|
2001-06-06 20:29:01 +00:00
|
|
|
}
|
|
|
|
|
2007-12-10 02:14:30 +00:00
|
|
|
Instruction::~Instruction() {
|
[LLVM] Add option to store Parent-pointer in ilist_node_base (#94224)
This patch adds a new option for `ilist`, `ilist_parent<ParentTy>`, that
enables storing an additional pointer in the `ilist_node_base` type to a
specified "parent" type, and uses that option for `Instruction`.
This is distinct from the `ilist_node_with_parent` class, despite their
apparent similarities. The `ilist_node_with_parent` class is a subclass
of `ilist_node` that requires its own subclasses to define a `getParent`
method, which is then used by the owning `ilist` for some of its
operations; it is purely an interface declaration. The `ilist_parent`
option on the other hand is concerned with data, adding a parent field
to the `ilist_node_base` class.
Currently, we can use `BasicBlock::iterator` to insert instructions,
_except_ when either the iterator is invalid (`NodePtr=0x0`), or when
the iterator points to a sentinel value (`BasicBlock::end()`). This patch
results in the sentinel value also having a valid pointer to its owning
basic block, which allows us to use iterators for all insertions,
without needing to store or pass an extra `BasicBlock *BB` argument
alongside it.
2024-06-18 19:59:35 +01:00
|
|
|
assert(!getParent() && "Instruction still linked in the program!");
|
[Instruction] Set metadata uses to undef on deletion
Summary:
Replace any extant metadata uses of a dying instruction with undef to
preserve debug info accuracy. Some alternatives include:
- Treat Instruction like any other Value, and point its extant metadata
uses to an empty ValueAsMetadata node. This makes extant dbg.value uses
trivially dead (i.e. fair game for deletion in many passes), leading to
stale dbg.values being in effect for too long.
- Call salvageDebugInfoOrMarkUndef. Not needed to make instruction removal
correct. OTOH results in wasted work in some common cases (e.g. when all
instructions in a BasicBlock are deleted).
This came up while discussing some basic cases in
https://reviews.llvm.org/D80052.
Reviewers: jmorse, TWeaver, aprantl, dexonsmith, jdoerfert
Subscribers: jholewinski, qcolombet, hiraditya, jfb, sstefan1, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D80264
2020-05-19 18:03:22 -07:00
|
|
|
|
2025-03-03 00:17:01 +00:00
|
|
|
// Replace any extant metadata uses of this instruction with poison to
|
[Instruction] Set metadata uses to undef on deletion
Summary:
Replace any extant metadata uses of a dying instruction with undef to
preserve debug info accuracy. Some alternatives include:
- Treat Instruction like any other Value, and point its extant metadata
uses to an empty ValueAsMetadata node. This makes extant dbg.value uses
trivially dead (i.e. fair game for deletion in many passes), leading to
stale dbg.values being in effect for too long.
- Call salvageDebugInfoOrMarkUndef. Not needed to make instruction removal
correct. OTOH results in wasted work in some common cases (e.g. when all
instructions in a BasicBlock are deleted).
This came up while discussing some basic cases in
https://reviews.llvm.org/D80052.
Reviewers: jmorse, TWeaver, aprantl, dexonsmith, jdoerfert
Subscribers: jholewinski, qcolombet, hiraditya, jfb, sstefan1, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D80264
2020-05-19 18:03:22 -07:00
|
|
|
// preserve debug info accuracy. Some alternatives include:
|
|
|
|
// - Treat Instruction like any other Value, and point its extant metadata
|
|
|
|
// uses to an empty ValueAsMetadata node. This makes extant dbg.value uses
|
|
|
|
// trivially dead (i.e. fair game for deletion in many passes), leading to
|
|
|
|
// stale dbg.values being in effect for too long.
|
|
|
|
// - Call salvageDebugInfoOrMarkUndef. Not needed to make instruction removal
|
|
|
|
// correct. OTOH results in wasted work in some common cases (e.g. when all
|
|
|
|
// instructions in a BasicBlock are deleted).
|
|
|
|
if (isUsedByMetadata())
|
2025-03-03 00:17:01 +00:00
|
|
|
ValueAsMetadata::handleRAUW(this, PoisonValue::get(getType()));
|
2022-11-07 11:56:36 +00:00
|
|
|
|
|
|
|
// Explicitly remove DIAssignID metadata to clear up ID -> Instruction(s)
|
|
|
|
// mapping in LLVMContext.
|
|
|
|
setMetadata(LLVMContext::MD_DIAssignID, nullptr);
|
2006-06-21 16:53:47 +00:00
|
|
|
}
|
|
|
|
|
2015-03-03 22:01:13 +00:00
|
|
|
const Module *Instruction::getModule() const {
|
|
|
|
return getParent()->getModule();
|
|
|
|
}
|
|
|
|
|
2015-12-08 00:13:12 +00:00
|
|
|
const Function *Instruction::getFunction() const {
|
|
|
|
return getParent()->getParent();
|
|
|
|
}
|
2015-05-26 21:03:23 +00:00
|
|
|
|
2024-06-27 16:38:15 +02:00
|
|
|
const DataLayout &Instruction::getDataLayout() const {
|
|
|
|
return getModule()->getDataLayout();
|
|
|
|
}
|
|
|
|
|
2004-10-11 22:21:39 +00:00
|
|
|
void Instruction::removeFromParent() {
|
2023-11-09 13:35:52 +00:00
|
|
|
// Perform any debug-info maintenence required.
|
|
|
|
handleMarkerRemoval();
|
|
|
|
|
2015-10-08 23:49:46 +00:00
|
|
|
getParent()->getInstList().remove(getIterator());
|
2004-10-11 22:21:39 +00:00
|
|
|
}
|
|
|
|
|
2023-11-09 13:35:52 +00:00
|
|
|
void Instruction::handleMarkerRemoval() {
|
[LLVM] Add option to store Parent-pointer in ilist_node_base (#94224)
This patch adds a new option for `ilist`, `ilist_parent<ParentTy>`, that
enables storing an additional pointer in the `ilist_node_base` type to a
specified "parent" type, and uses that option for `Instruction`.
This is distinct from the `ilist_node_with_parent` class, despite their
apparent similarities. The `ilist_node_with_parent` class is a subclass
of `ilist_node` that requires its own subclasses to define a `getParent`
method, which is then used by the owning `ilist` for some of its
operations; it is purely an interface declaration. The `ilist_parent`
option on the other hand is concerned with data, adding a parent field
to the `ilist_node_base` class.
Currently, we can use `BasicBlock::iterator` to insert instructions,
_except_ when either the iterator is invalid (`NodePtr=0x0`), or when
the iterator points to a sentinel value (`BasicBlock::end()`). This patch
results in the sentinel value also having a valid pointer to its owning
basic block, which allows us to use iterators for all insertions,
without needing to store or pass an extra `BasicBlock *BB` argument
alongside it.
2024-06-18 19:59:35 +01:00
|
|
|
if (!getParent()->IsNewDbgInfoFormat || !DebugMarker)
|
2023-11-09 13:35:52 +00:00
|
|
|
return;
|
|
|
|
|
2024-03-20 16:00:10 +00:00
|
|
|
DebugMarker->removeMarker();
|
2023-11-09 13:35:52 +00:00
|
|
|
}
|
|
|
|
|
2023-10-17 15:08:58 +01:00
|
|
|
BasicBlock::iterator Instruction::eraseFromParent() {
|
2023-11-09 13:35:52 +00:00
|
|
|
handleMarkerRemoval();
|
2015-10-08 23:49:46 +00:00
|
|
|
return getParent()->getInstList().erase(getIterator());
|
2004-10-11 22:21:39 +00:00
|
|
|
}
|
2002-07-14 23:09:40 +00:00
|
|
|
|
2023-11-09 13:35:52 +00:00
|
|
|
void Instruction::insertBefore(Instruction *InsertPos) {
|
|
|
|
insertBefore(InsertPos->getIterator());
|
|
|
|
}
|
|
|
|
|
2016-01-06 00:18:29 +00:00
|
|
|
/// Insert an unlinked instruction into a basic block immediately before the
|
|
|
|
/// specified instruction.
|
2023-11-09 13:35:52 +00:00
|
|
|
void Instruction::insertBefore(BasicBlock::iterator InsertPos) {
|
|
|
|
insertBefore(*InsertPos->getParent(), InsertPos);
|
2008-06-17 18:29:27 +00:00
|
|
|
}
|
|
|
|
|
2016-01-06 00:18:29 +00:00
|
|
|
/// Insert an unlinked instruction into a basic block immediately after the
|
|
|
|
/// specified instruction.
|
2009-01-13 07:43:51 +00:00
|
|
|
void Instruction::insertAfter(Instruction *InsertPos) {
|
2023-11-09 13:35:52 +00:00
|
|
|
BasicBlock *DestParent = InsertPos->getParent();
|
|
|
|
|
|
|
|
DestParent->getInstList().insertAfter(InsertPos->getIterator(), this);
|
2009-01-13 07:43:51 +00:00
|
|
|
}
|
|
|
|
|
2025-01-24 10:53:11 +00:00
|
|
|
void Instruction::insertAfter(BasicBlock::iterator InsertPos) {
|
|
|
|
BasicBlock *DestParent = InsertPos->getParent();
|
|
|
|
|
|
|
|
DestParent->getInstList().insertAfter(InsertPos, this);
|
|
|
|
}
|
|
|
|
|
2022-12-14 17:42:26 -08:00
|
|
|
BasicBlock::iterator Instruction::insertInto(BasicBlock *ParentBB,
|
|
|
|
BasicBlock::iterator It) {
|
2022-11-28 14:38:38 -08:00
|
|
|
assert(getParent() == nullptr && "Expected detached instruction");
|
2022-12-14 17:42:26 -08:00
|
|
|
assert((It == ParentBB->end() || It->getParent() == ParentBB) &&
|
|
|
|
"It not in ParentBB");
|
2023-11-09 13:35:52 +00:00
|
|
|
insertBefore(*ParentBB, It);
|
|
|
|
return getIterator();
|
|
|
|
}
|
|
|
|
|
|
|
|
extern cl::opt<bool> UseNewDbgInfoFormat;
|
|
|
|
|
|
|
|
void Instruction::insertBefore(BasicBlock &BB,
|
|
|
|
InstListType::iterator InsertPos) {
|
2024-03-20 16:00:10 +00:00
|
|
|
assert(!DebugMarker);
|
2023-11-09 13:35:52 +00:00
|
|
|
|
|
|
|
BB.getInstList().insert(InsertPos, this);
|
|
|
|
|
|
|
|
if (!BB.IsNewDbgInfoFormat)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// We've inserted "this": if InsertAtHead is set then it comes before any
|
[RemoveDIs][NFC] Rename DPValue -> DbgVariableRecord (#85216)
This is the major rename patch that prior patches have built towards.
The DPValue class is being renamed to DbgVariableRecord, which reflects
the updated terminology for the "final" implementation of the RemoveDI
feature. This is a pure string substitution + clang-format patch. The
only manual component of this patch was determining where to perform
these string substitutions: `DPValue` and `DPV` are almost exclusively
used for DbgRecords, *except* for:
- llvm/lib/target, where 'DP' is used to mean double-precision, and so
appears as part of .td files and in variable names. NB: There is a
single existing use of `DPValue` here that refers to debug info, which
I've manually updated.
- llvm/tools/gold, where 'LDPV' is used as a prefix for symbol
visibility enums.
Outside of these places, I've applied several basic string
substitutions, with the intent that they only affect DbgRecord-related
identifiers; I've checked them as I went through to verify this, with
reasonable confidence that there are no unintended changes that slipped
through the cracks. The substitutions applied are all case-sensitive,
and are applied in the order shown:
```
DPValue -> DbgVariableRecord
DPVal -> DbgVarRec
DPV -> DVR
```
Following the previous rename patches, it should be the case that there
are no instances of any of these strings that are meant to refer to the
general case of DbgRecords, or anything other than the DPValue class.
The idea behind this patch is therefore that pure string substitution is
correct in all cases as long as these assumptions hold.
2024-03-19 20:07:07 +00:00
|
|
|
// DbgVariableRecords attached to InsertPos. But if it's not set, then any
|
|
|
|
// DbgRecords should now come before "this".
|
2023-11-09 13:35:52 +00:00
|
|
|
bool InsertAtHead = InsertPos.getHeadBit();
|
|
|
|
if (!InsertAtHead) {
|
2024-03-20 16:00:10 +00:00
|
|
|
DbgMarker *SrcMarker = BB.getMarker(InsertPos);
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
if (SrcMarker && !SrcMarker->empty()) {
|
2024-03-11 08:58:59 +00:00
|
|
|
// If this assertion fires, the calling code is about to insert a PHI
|
|
|
|
// after debug-records, which would form a sequence like:
|
|
|
|
// %0 = PHI
|
|
|
|
// #dbg_value
|
|
|
|
// %1 = PHI
|
|
|
|
// Which is de-normalised and undesired -- hence the assertion. To avoid
|
|
|
|
// this, you must insert at that position using an iterator, and it must
|
|
|
|
// be aquired by calling getFirstNonPHIIt / begin or similar methods on
|
|
|
|
// the block. This will signal to this behind-the-scenes debug-info
|
|
|
|
// maintenence code that you intend the PHI to be ahead of everything,
|
|
|
|
// including any debug-info.
|
|
|
|
assert(!isa<PHINode>(this) && "Inserting PHI after debug-records!");
|
2024-03-12 14:53:13 +00:00
|
|
|
adoptDbgRecords(&BB, InsertPos, false);
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
}
|
2023-11-09 13:35:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// If we're inserting a terminator, check if we need to flush out
|
2024-03-13 16:39:35 +00:00
|
|
|
// TrailingDbgRecords. Inserting instructions at the end of an incomplete
|
2024-03-12 10:25:58 +00:00
|
|
|
// block is handled by the code block above.
|
2023-11-09 13:35:52 +00:00
|
|
|
if (isTerminator())
|
2024-03-13 16:39:35 +00:00
|
|
|
getParent()->flushTerminatorDbgRecords();
|
2022-11-28 14:38:38 -08:00
|
|
|
}
|
|
|
|
|
2016-01-06 00:18:29 +00:00
|
|
|
/// Unlink this instruction from its current basic block and insert it into the
|
|
|
|
/// basic block that MovePos lives in, right before MovePos.
|
2005-08-08 05:21:50 +00:00
|
|
|
void Instruction::moveBefore(Instruction *MovePos) {
|
2023-11-09 13:35:52 +00:00
|
|
|
moveBeforeImpl(*MovePos->getParent(), MovePos->getIterator(), false);
|
|
|
|
}
|
|
|
|
|
2025-01-24 10:53:11 +00:00
|
|
|
void Instruction::moveBefore(BasicBlock::iterator MovePos) {
|
|
|
|
moveBeforeImpl(*MovePos->getParent(), MovePos, false);
|
|
|
|
}
|
|
|
|
|
2023-11-09 13:35:52 +00:00
|
|
|
void Instruction::moveBeforePreserving(Instruction *MovePos) {
|
|
|
|
moveBeforeImpl(*MovePos->getParent(), MovePos->getIterator(), true);
|
2016-08-17 01:54:41 +00:00
|
|
|
}
|
|
|
|
|
2025-01-24 10:53:11 +00:00
|
|
|
void Instruction::moveBeforePreserving(BasicBlock::iterator MovePos) {
|
|
|
|
moveBeforeImpl(*MovePos->getParent(), MovePos, true);
|
|
|
|
}
|
|
|
|
|
2017-08-29 14:07:48 +00:00
|
|
|
void Instruction::moveAfter(Instruction *MovePos) {
|
2023-11-09 13:35:52 +00:00
|
|
|
auto NextIt = std::next(MovePos->getIterator());
|
|
|
|
// We want this instruction to be moved to before NextIt in the instruction
|
|
|
|
// list, but before NextIt's debug value range.
|
|
|
|
NextIt.setHeadBit(true);
|
|
|
|
moveBeforeImpl(*MovePos->getParent(), NextIt, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::moveAfterPreserving(Instruction *MovePos) {
|
|
|
|
auto NextIt = std::next(MovePos->getIterator());
|
|
|
|
// We want this instruction and its debug range to be moved to before NextIt
|
|
|
|
// in the instruction list, but before NextIt's debug value range.
|
|
|
|
NextIt.setHeadBit(true);
|
|
|
|
moveBeforeImpl(*MovePos->getParent(), NextIt, true);
|
2017-08-29 14:07:48 +00:00
|
|
|
}
|
|
|
|
|
2023-10-17 15:08:58 +01:00
|
|
|
void Instruction::moveBefore(BasicBlock &BB, InstListType::iterator I) {
|
2023-11-09 13:35:52 +00:00
|
|
|
moveBeforeImpl(BB, I, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::moveBeforePreserving(BasicBlock &BB,
|
|
|
|
InstListType::iterator I) {
|
|
|
|
moveBeforeImpl(BB, I, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::moveBeforeImpl(BasicBlock &BB, InstListType::iterator I,
|
|
|
|
bool Preserve) {
|
2016-08-17 01:54:41 +00:00
|
|
|
assert(I == BB.end() || I->getParent() == &BB);
|
2023-11-09 13:35:52 +00:00
|
|
|
bool InsertAtHead = I.getHeadBit();
|
|
|
|
|
2024-03-13 16:39:35 +00:00
|
|
|
// If we've been given the "Preserve" flag, then just move the DbgRecords with
|
2023-11-09 13:35:52 +00:00
|
|
|
// the instruction, no more special handling needed.
|
2024-03-20 16:00:10 +00:00
|
|
|
if (BB.IsNewDbgInfoFormat && DebugMarker && !Preserve) {
|
2023-12-05 14:05:00 +00:00
|
|
|
if (I != this->getIterator() || InsertAtHead) {
|
|
|
|
// "this" is definitely moving in the list, or it's moving ahead of its
|
[RemoveDIs][NFC] Rename DPValue -> DbgVariableRecord (#85216)
This is the major rename patch that prior patches have built towards.
The DPValue class is being renamed to DbgVariableRecord, which reflects
the updated terminology for the "final" implementation of the RemoveDI
feature. This is a pure string substitution + clang-format patch. The
only manual component of this patch was determining where to perform
these string substitutions: `DPValue` and `DPV` are almost exclusively
used for DbgRecords, *except* for:
- llvm/lib/target, where 'DP' is used to mean double-precision, and so
appears as part of .td files and in variable names. NB: There is a
single existing use of `DPValue` here that refers to debug info, which
I've manually updated.
- llvm/tools/gold, where 'LDPV' is used as a prefix for symbol
visibility enums.
Outside of these places, I've applied several basic string
substitutions, with the intent that they only affect DbgRecord-related
identifiers; I've checked them as I went through to verify this, with
reasonable confidence that there are no unintended changes that slipped
through the cracks. The substitutions applied are all case-sensitive,
and are applied in the order shown:
```
DPValue -> DbgVariableRecord
DPVal -> DbgVarRec
DPV -> DVR
```
Following the previous rename patches, it should be the case that there
are no instances of any of these strings that are meant to refer to the
general case of DbgRecords, or anything other than the DPValue class.
The idea behind this patch is therefore that pure string substitution is
correct in all cases as long as these assumptions hold.
2024-03-19 20:07:07 +00:00
|
|
|
// attached DbgVariableRecords. Detach any existing DbgRecords.
|
2023-11-09 13:35:52 +00:00
|
|
|
handleMarkerRemoval();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Move this single instruction. Use the list splice method directly, not
|
|
|
|
// the block splicer, which will do more debug-info things.
|
|
|
|
BB.getInstList().splice(I, getParent()->getInstList(), getIterator());
|
|
|
|
|
|
|
|
if (BB.IsNewDbgInfoFormat && !Preserve) {
|
2024-03-20 16:00:10 +00:00
|
|
|
DbgMarker *NextMarker = getParent()->getNextMarker(this);
|
2023-11-09 13:35:52 +00:00
|
|
|
|
2024-03-13 16:39:35 +00:00
|
|
|
// If we're inserting at point I, and not in front of the DbgRecords
|
|
|
|
// attached there, then we should absorb the DbgRecords attached to I.
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
if (!InsertAtHead && NextMarker && !NextMarker->empty()) {
|
2024-03-12 14:53:13 +00:00
|
|
|
adoptDbgRecords(&BB, I, false);
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
}
|
2023-11-09 13:35:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (isTerminator())
|
2024-03-13 16:39:35 +00:00
|
|
|
getParent()->flushTerminatorDbgRecords();
|
2023-11-09 13:35:52 +00:00
|
|
|
}
|
|
|
|
|
2024-02-20 16:00:55 +00:00
|
|
|
iterator_range<DbgRecord::self_iterator> Instruction::cloneDebugInfoFrom(
|
|
|
|
const Instruction *From, std::optional<DbgRecord::self_iterator> FromHere,
|
|
|
|
bool InsertAtHead) {
|
2024-03-20 16:00:10 +00:00
|
|
|
if (!From->DebugMarker)
|
|
|
|
return DbgMarker::getEmptyDbgRecordRange();
|
2023-11-09 13:35:52 +00:00
|
|
|
|
|
|
|
assert(getParent()->IsNewDbgInfoFormat);
|
|
|
|
assert(getParent()->IsNewDbgInfoFormat ==
|
|
|
|
From->getParent()->IsNewDbgInfoFormat);
|
|
|
|
|
2024-03-20 16:00:10 +00:00
|
|
|
if (!DebugMarker)
|
2023-11-09 13:35:52 +00:00
|
|
|
getParent()->createMarker(this);
|
|
|
|
|
2024-03-20 16:00:10 +00:00
|
|
|
return DebugMarker->cloneDebugInfoFrom(From->DebugMarker, FromHere,
|
|
|
|
InsertAtHead);
|
2023-11-09 13:35:52 +00:00
|
|
|
}
|
|
|
|
|
2024-02-20 16:00:55 +00:00
|
|
|
std::optional<DbgRecord::self_iterator>
|
|
|
|
Instruction::getDbgReinsertionPosition() {
|
2023-11-30 12:41:52 +00:00
|
|
|
// Is there a marker on the next instruction?
|
2024-03-20 16:00:10 +00:00
|
|
|
DbgMarker *NextMarker = getParent()->getNextMarker(this);
|
2023-11-30 12:41:52 +00:00
|
|
|
if (!NextMarker)
|
|
|
|
return std::nullopt;
|
|
|
|
|
2024-03-13 16:39:35 +00:00
|
|
|
// Are there any DbgRecords in the next marker?
|
|
|
|
if (NextMarker->StoredDbgRecords.empty())
|
2023-11-30 12:41:52 +00:00
|
|
|
return std::nullopt;
|
|
|
|
|
2024-03-13 16:39:35 +00:00
|
|
|
return NextMarker->StoredDbgRecords.begin();
|
2023-11-30 12:41:52 +00:00
|
|
|
}
|
|
|
|
|
2024-03-12 14:53:13 +00:00
|
|
|
bool Instruction::hasDbgRecords() const { return !getDbgRecordRange().empty(); }
|
2023-11-09 13:35:52 +00:00
|
|
|
|
2024-03-12 14:53:13 +00:00
|
|
|
void Instruction::adoptDbgRecords(BasicBlock *BB, BasicBlock::iterator It,
|
|
|
|
bool InsertAtHead) {
|
2024-03-20 16:00:10 +00:00
|
|
|
DbgMarker *SrcMarker = BB->getMarker(It);
|
2024-03-13 16:39:35 +00:00
|
|
|
auto ReleaseTrailingDbgRecords = [BB, It, SrcMarker]() {
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
if (BB->end() == It) {
|
|
|
|
SrcMarker->eraseFromParent();
|
2024-03-12 14:53:13 +00:00
|
|
|
BB->deleteTrailingDbgRecords();
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2024-03-13 16:39:35 +00:00
|
|
|
if (!SrcMarker || SrcMarker->StoredDbgRecords.empty()) {
|
|
|
|
ReleaseTrailingDbgRecords();
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2024-03-20 16:00:10 +00:00
|
|
|
// If we have DbgMarkers attached to this instruction, we have to honour the
|
2024-03-13 16:39:35 +00:00
|
|
|
// ordering of DbgRecords between this and the other marker. Fall back to just
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
// absorbing from the source.
|
2024-03-20 16:00:10 +00:00
|
|
|
if (DebugMarker || It == BB->end()) {
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
// Ensure we _do_ have a marker.
|
|
|
|
getParent()->createMarker(this);
|
2024-03-20 16:00:10 +00:00
|
|
|
DebugMarker->absorbDebugValues(*SrcMarker, InsertAtHead);
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
|
|
|
|
// Having transferred everything out of SrcMarker, we _could_ clean it up
|
|
|
|
// and free the marker now. However, that's a lot of heap-accounting for a
|
|
|
|
// small amount of memory with a good chance of re-use. Leave it for the
|
|
|
|
// moment. It will be released when the Instruction is freed in the worst
|
|
|
|
// case.
|
|
|
|
// However: if we transferred from a trailing marker off the end of the
|
|
|
|
// block, it's important to not leave the empty marker trailing. It will
|
|
|
|
// give a misleading impression that some debug records have been left
|
|
|
|
// trailing.
|
2024-03-13 16:39:35 +00:00
|
|
|
ReleaseTrailingDbgRecords();
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
} else {
|
2024-03-13 16:39:35 +00:00
|
|
|
// Optimisation: we're transferring all the DbgRecords from the source
|
|
|
|
// marker onto this empty location: just adopt the other instructions
|
|
|
|
// marker.
|
2024-03-20 16:00:10 +00:00
|
|
|
DebugMarker = SrcMarker;
|
|
|
|
DebugMarker->MarkedInstr = this;
|
|
|
|
It->DebugMarker = nullptr;
|
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
2024-02-06 13:08:44 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2024-03-12 14:53:13 +00:00
|
|
|
void Instruction::dropDbgRecords() {
|
2024-03-20 16:00:10 +00:00
|
|
|
if (DebugMarker)
|
|
|
|
DebugMarker->dropDbgRecords();
|
2023-11-09 13:35:52 +00:00
|
|
|
}
|
|
|
|
|
[RemoveDIs][NFC] Rename DPValue -> DbgVariableRecord (#85216)
This is the major rename patch that prior patches have built towards.
The DPValue class is being renamed to DbgVariableRecord, which reflects
the updated terminology for the "final" implementation of the RemoveDI
feature. This is a pure string substitution + clang-format patch. The
only manual component of this patch was determining where to perform
these string substitutions: `DPValue` and `DPV` are almost exclusively
used for DbgRecords, *except* for:
- llvm/lib/target, where 'DP' is used to mean double-precision, and so
appears as part of .td files and in variable names. NB: There is a
single existing use of `DPValue` here that refers to debug info, which
I've manually updated.
- llvm/tools/gold, where 'LDPV' is used as a prefix for symbol
visibility enums.
Outside of these places, I've applied several basic string
substitutions, with the intent that they only affect DbgRecord-related
identifiers; I've checked them as I went through to verify this, with
reasonable confidence that there are no unintended changes that slipped
through the cracks. The substitutions applied are all case-sensitive,
and are applied in the order shown:
```
DPValue -> DbgVariableRecord
DPVal -> DbgVarRec
DPV -> DVR
```
Following the previous rename patches, it should be the case that there
are no instances of any of these strings that are meant to refer to the
general case of DbgRecords, or anything other than the DPValue class.
The idea behind this patch is therefore that pure string substitution is
correct in all cases as long as these assumptions hold.
2024-03-19 20:07:07 +00:00
|
|
|
void Instruction::dropOneDbgRecord(DbgRecord *DVR) {
|
2024-03-20 16:00:10 +00:00
|
|
|
DebugMarker->dropOneDbgRecord(DVR);
|
2005-08-08 05:21:50 +00:00
|
|
|
}
|
|
|
|
|
[IR] Lazily number instructions for local dominance queries
Essentially, fold OrderedBasicBlock into BasicBlock, and make it
auto-invalidate the instruction ordering when new instructions are
added. Notably, we don't need to invalidate it when removing
instructions, which is helpful when a pass mostly delete dead
instructions rather than transforming them.
The downside is that Instruction grows from 56 bytes to 64 bytes. The
resulting LLVM code is substantially simpler and automatically handles
invalidation, which makes me think that this is the right speed and size
tradeoff.
The important change is in SymbolTableTraitsImpl.h, where the numbering
is invalidated. Everything else should be straightforward.
We probably want to implement a fancier re-numbering scheme so that
local updates don't invalidate the ordering, but I plan for that to be
future work, maybe for someone else.
Reviewed By: lattner, vsk, fhahn, dexonsmith
Differential Revision: https://reviews.llvm.org/D51664
2020-02-18 14:33:54 -08:00
|
|
|
bool Instruction::comesBefore(const Instruction *Other) const {
|
[LLVM] Add option to store Parent-pointer in ilist_node_base (#94224)
This patch adds a new option for `ilist`, `ilist_parent<ParentTy>`, that
enables storing an additional pointer in the `ilist_node_base` type to a
specified "parent" type, and uses that option for `Instruction`.
This is distinct from the `ilist_node_with_parent` class, despite their
apparent similarities. The `ilist_node_with_parent` class is a subclass
of `ilist_node` that requires its own subclasses to define a `getParent`
method, which is then used by the owning `ilist` for some of its
operations; it is purely an interface declaration. The `ilist_parent`
option on the other hand is concerned with data, adding a parent field
to the `ilist_node_base` class.
Currently, we can use `BasicBlock::iterator` to insert instructions,
_except_ when either the iterator is invalid (`NodePtr=0x0`), or when
the iterator points to a sentinel value (`BasicBlock::end()`). This patch
results in the sentinel value also having a valid pointer to its owning
basic block, which allows us to use iterators for all insertions,
without needing to store or pass an extra `BasicBlock *BB` argument
alongside it.
2024-06-18 19:59:35 +01:00
|
|
|
assert(getParent() && Other->getParent() &&
|
[IR] Lazily number instructions for local dominance queries
Essentially, fold OrderedBasicBlock into BasicBlock, and make it
auto-invalidate the instruction ordering when new instructions are
added. Notably, we don't need to invalidate it when removing
instructions, which is helpful when a pass mostly delete dead
instructions rather than transforming them.
The downside is that Instruction grows from 56 bytes to 64 bytes. The
resulting LLVM code is substantially simpler and automatically handles
invalidation, which makes me think that this is the right speed and size
tradeoff.
The important change is in SymbolTableTraitsImpl.h, where the numbering
is invalidated. Everything else should be straightforward.
We probably want to implement a fancier re-numbering scheme so that
local updates don't invalidate the ordering, but I plan for that to be
future work, maybe for someone else.
Reviewed By: lattner, vsk, fhahn, dexonsmith
Differential Revision: https://reviews.llvm.org/D51664
2020-02-18 14:33:54 -08:00
|
|
|
"instructions without BB parents have no order");
|
[LLVM] Add option to store Parent-pointer in ilist_node_base (#94224)
This patch adds a new option for `ilist`, `ilist_parent<ParentTy>`, that
enables storing an additional pointer in the `ilist_node_base` type to a
specified "parent" type, and uses that option for `Instruction`.
This is distinct from the `ilist_node_with_parent` class, despite their
apparent similarities. The `ilist_node_with_parent` class is a subclass
of `ilist_node` that requires its own subclasses to define a `getParent`
method, which is then used by the owning `ilist` for some of its
operations; it is purely an interface declaration. The `ilist_parent`
option on the other hand is concerned with data, adding a parent field
to the `ilist_node_base` class.
Currently, we can use `BasicBlock::iterator` to insert instructions,
_except_ when either the iterator is invalid (`NodePtr=0x0`), or when
the iterator points to a sentinel value (`BasicBlock::end()`). This patch
results in the sentinel value also having a valid pointer to its owning
basic block, which allows us to use iterators for all insertions,
without needing to store or pass an extra `BasicBlock *BB` argument
alongside it.
2024-06-18 19:59:35 +01:00
|
|
|
assert(getParent() == Other->getParent() &&
|
|
|
|
"cross-BB instruction order comparison");
|
|
|
|
if (!getParent()->isInstrOrderValid())
|
|
|
|
const_cast<BasicBlock *>(getParent())->renumberInstructions();
|
[IR] Lazily number instructions for local dominance queries
Essentially, fold OrderedBasicBlock into BasicBlock, and make it
auto-invalidate the instruction ordering when new instructions are
added. Notably, we don't need to invalidate it when removing
instructions, which is helpful when a pass mostly delete dead
instructions rather than transforming them.
The downside is that Instruction grows from 56 bytes to 64 bytes. The
resulting LLVM code is substantially simpler and automatically handles
invalidation, which makes me think that this is the right speed and size
tradeoff.
The important change is in SymbolTableTraitsImpl.h, where the numbering
is invalidated. Everything else should be straightforward.
We probably want to implement a fancier re-numbering scheme so that
local updates don't invalidate the ordering, but I plan for that to be
future work, maybe for someone else.
Reviewed By: lattner, vsk, fhahn, dexonsmith
Differential Revision: https://reviews.llvm.org/D51664
2020-02-18 14:33:54 -08:00
|
|
|
return Order < Other->Order;
|
|
|
|
}
|
|
|
|
|
2023-11-30 12:19:57 +00:00
|
|
|
std::optional<BasicBlock::iterator> Instruction::getInsertionPointAfterDef() {
|
2022-07-13 16:53:11 +02:00
|
|
|
assert(!getType()->isVoidTy() && "Instruction must define result");
|
|
|
|
BasicBlock *InsertBB;
|
|
|
|
BasicBlock::iterator InsertPt;
|
|
|
|
if (auto *PN = dyn_cast<PHINode>(this)) {
|
|
|
|
InsertBB = PN->getParent();
|
|
|
|
InsertPt = InsertBB->getFirstInsertionPt();
|
|
|
|
} else if (auto *II = dyn_cast<InvokeInst>(this)) {
|
|
|
|
InsertBB = II->getNormalDest();
|
|
|
|
InsertPt = InsertBB->getFirstInsertionPt();
|
2023-02-17 10:21:10 -08:00
|
|
|
} else if (isa<CallBrInst>(this)) {
|
2023-02-16 17:44:02 -08:00
|
|
|
// Def is available in multiple successors, there's no single dominating
|
|
|
|
// insertion point.
|
2023-11-30 12:19:57 +00:00
|
|
|
return std::nullopt;
|
2022-07-13 16:53:11 +02:00
|
|
|
} else {
|
|
|
|
assert(!isTerminator() && "Only invoke/callbr terminators return value");
|
|
|
|
InsertBB = getParent();
|
|
|
|
InsertPt = std::next(getIterator());
|
2023-11-30 12:19:57 +00:00
|
|
|
// Any instruction inserted immediately after "this" will come before any
|
|
|
|
// debug-info records take effect -- thus, set the head bit indicating that
|
|
|
|
// to debug-info-transfer code.
|
|
|
|
InsertPt.setHeadBit(true);
|
2022-07-13 16:53:11 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// catchswitch blocks don't have any legal insertion point (because they
|
|
|
|
// are both an exception pad and a terminator).
|
|
|
|
if (InsertPt == InsertBB->end())
|
2023-11-30 12:19:57 +00:00
|
|
|
return std::nullopt;
|
|
|
|
return InsertPt;
|
2022-07-13 16:53:11 +02:00
|
|
|
}
|
|
|
|
|
2021-06-01 08:31:23 -04:00
|
|
|
bool Instruction::isOnlyUserOfAnyOperand() {
|
|
|
|
return any_of(operands(), [](Value *V) { return V->hasOneUser(); });
|
|
|
|
}
|
|
|
|
|
2016-04-22 06:37:45 +00:00
|
|
|
void Instruction::setHasNoUnsignedWrap(bool b) {
|
2024-03-29 08:08:49 +02:00
|
|
|
if (auto *Inst = dyn_cast<OverflowingBinaryOperator>(this))
|
|
|
|
Inst->setHasNoUnsignedWrap(b);
|
|
|
|
else
|
|
|
|
cast<TruncInst>(this)->setHasNoUnsignedWrap(b);
|
2016-04-22 06:37:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::setHasNoSignedWrap(bool b) {
|
2024-03-29 08:08:49 +02:00
|
|
|
if (auto *Inst = dyn_cast<OverflowingBinaryOperator>(this))
|
|
|
|
Inst->setHasNoSignedWrap(b);
|
|
|
|
else
|
|
|
|
cast<TruncInst>(this)->setHasNoSignedWrap(b);
|
2016-04-22 06:37:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::setIsExact(bool b) {
|
|
|
|
cast<PossiblyExactOperator>(this)->setIsExact(b);
|
|
|
|
}
|
|
|
|
|
2023-10-30 09:04:04 +01:00
|
|
|
void Instruction::setNonNeg(bool b) {
|
2024-03-20 16:46:24 -05:00
|
|
|
assert(isa<PossiblyNonNegInst>(this) && "Must be zext/uitofp");
|
2023-10-30 09:04:04 +01:00
|
|
|
SubclassOptionalData = (SubclassOptionalData & ~PossiblyNonNegInst::NonNeg) |
|
|
|
|
(b * PossiblyNonNegInst::NonNeg);
|
|
|
|
}
|
|
|
|
|
2016-04-22 06:37:45 +00:00
|
|
|
bool Instruction::hasNoUnsignedWrap() const {
|
2024-03-29 08:08:49 +02:00
|
|
|
if (auto *Inst = dyn_cast<OverflowingBinaryOperator>(this))
|
|
|
|
return Inst->hasNoUnsignedWrap();
|
|
|
|
|
|
|
|
return cast<TruncInst>(this)->hasNoUnsignedWrap();
|
2016-04-22 06:37:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool Instruction::hasNoSignedWrap() const {
|
2024-03-29 08:08:49 +02:00
|
|
|
if (auto *Inst = dyn_cast<OverflowingBinaryOperator>(this))
|
|
|
|
return Inst->hasNoSignedWrap();
|
|
|
|
|
|
|
|
return cast<TruncInst>(this)->hasNoSignedWrap();
|
2016-04-22 06:37:45 +00:00
|
|
|
}
|
|
|
|
|
2023-10-30 09:04:04 +01:00
|
|
|
bool Instruction::hasNonNeg() const {
|
2024-03-20 16:46:24 -05:00
|
|
|
assert(isa<PossiblyNonNegInst>(this) && "Must be zext/uitofp");
|
2023-10-30 09:04:04 +01:00
|
|
|
return (SubclassOptionalData & PossiblyNonNegInst::NonNeg) != 0;
|
|
|
|
}
|
|
|
|
|
2021-11-16 08:48:16 -08:00
|
|
|
bool Instruction::hasPoisonGeneratingFlags() const {
|
|
|
|
return cast<Operator>(this)->hasPoisonGeneratingFlags();
|
|
|
|
}
|
|
|
|
|
2017-02-23 22:50:52 +00:00
|
|
|
void Instruction::dropPoisonGeneratingFlags() {
|
|
|
|
switch (getOpcode()) {
|
|
|
|
case Instruction::Add:
|
|
|
|
case Instruction::Sub:
|
|
|
|
case Instruction::Mul:
|
|
|
|
case Instruction::Shl:
|
|
|
|
cast<OverflowingBinaryOperator>(this)->setHasNoUnsignedWrap(false);
|
|
|
|
cast<OverflowingBinaryOperator>(this)->setHasNoSignedWrap(false);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case Instruction::UDiv:
|
|
|
|
case Instruction::SDiv:
|
|
|
|
case Instruction::AShr:
|
|
|
|
case Instruction::LShr:
|
|
|
|
cast<PossiblyExactOperator>(this)->setIsExact(false);
|
|
|
|
break;
|
|
|
|
|
2023-11-24 08:49:19 -08:00
|
|
|
case Instruction::Or:
|
|
|
|
cast<PossiblyDisjointInst>(this)->setIsDisjoint(false);
|
|
|
|
break;
|
|
|
|
|
2017-02-23 22:50:52 +00:00
|
|
|
case Instruction::GetElementPtr:
|
2024-05-27 16:05:17 +02:00
|
|
|
cast<GetElementPtrInst>(this)->setNoWrapFlags(GEPNoWrapFlags::none());
|
2017-02-23 22:50:52 +00:00
|
|
|
break;
|
2023-10-30 09:04:04 +01:00
|
|
|
|
2024-03-20 16:46:24 -05:00
|
|
|
case Instruction::UIToFP:
|
2023-10-30 09:04:04 +01:00
|
|
|
case Instruction::ZExt:
|
|
|
|
setNonNeg(false);
|
|
|
|
break;
|
2024-03-29 08:08:49 +02:00
|
|
|
|
|
|
|
case Instruction::Trunc:
|
|
|
|
cast<TruncInst>(this)->setHasNoUnsignedWrap(false);
|
|
|
|
cast<TruncInst>(this)->setHasNoSignedWrap(false);
|
|
|
|
break;
|
2024-10-15 12:11:25 +03:00
|
|
|
|
|
|
|
case Instruction::ICmp:
|
|
|
|
cast<ICmpInst>(this)->setSameSign(false);
|
|
|
|
break;
|
2017-02-23 22:50:52 +00:00
|
|
|
}
|
2023-10-30 09:04:04 +01:00
|
|
|
|
2021-12-14 08:09:00 -08:00
|
|
|
if (isa<FPMathOperator>(this)) {
|
|
|
|
setHasNoNaNs(false);
|
|
|
|
setHasNoInfs(false);
|
|
|
|
}
|
2021-10-27 10:51:03 -07:00
|
|
|
|
2021-11-16 08:48:16 -08:00
|
|
|
assert(!hasPoisonGeneratingFlags() && "must be kept in sync");
|
2017-02-23 22:50:52 +00:00
|
|
|
}
|
|
|
|
|
2023-01-19 15:34:35 +01:00
|
|
|
bool Instruction::hasPoisonGeneratingMetadata() const {
|
2025-01-16 20:45:56 +00:00
|
|
|
return any_of(Metadata::PoisonGeneratingIDs,
|
|
|
|
[this](unsigned ID) { return hasMetadata(ID); });
|
2023-01-19 15:34:35 +01:00
|
|
|
}
|
|
|
|
|
Only guard loop metadata that has non-debug info in it (#118825)
This PR is motivated by a mismatch we discovered between compilation
results with vs. without `-g3`. We noticed this when compiling SPEC2017
testcases. The specific instance we saw is fixed in this PR by modifying
a guard (see below), but it is likely similar instances exist elsewhere
in the codebase.
The specific case fixed in this PR manifests itself in the `SimplifyCFG`
pass doing different things depending on whether DebugInfo is generated
or not. At the end of this comment, there is reduced example code that
shows the behavior in question.
The differing behavior has two root causes:
1. Commit https://github.com/llvm/llvm-project/commit/c07e19b adds loop
metadata including debug locations to loops that otherwise would not
have loop metadata
2. Commit https://github.com/llvm/llvm-project/commit/ac28efa6c100 adds
a guard to a simplification action in `SImplifyCFG` that prevents it
from simplifying away loop metadata
So, the change in 2. does not consider that when compiling with debug
symbols, loops that otherwise would not have metadata that needs
preserving, now have debug locations in their loop metadata. Thus, with
`-g3`, `SimplifyCFG` behaves differently than without it.
The larger issue is that while debug info is not supposed to influence
the final compilation result, commits like 1. blur the line between what
is and is not debug info, and not all optimization passes account for
this.
This PR does not address that and rather just modifies this particular
guard in order to restore equivalent behavior between debug and
non-debug builds in this one instance.
---
Here is a reduced version of a file from `f526.blender_r` that showcases
the behavior in question:
```C
struct LinkNode;
typedef struct LinkNode {
struct LinkNode *next;
void *link;
} LinkNode;
void do_projectpaint_thread_ph_v_state() {
int *ps = do_projectpaint_thread_ph_v_state;
LinkNode *node;
while (do_projectpaint_thread_ph_v_state)
for (node = ps; node; node = node->next)
;
}
```
Compiling this with and without DebugInfo, and then disassembling the
results, leads to different outcomes (tested on SystemZ and X86). The
reason for this is that the `SimplifyCFG` pass does different things in
either case.
2024-12-20 15:15:51 +01:00
|
|
|
bool Instruction::hasNonDebugLocLoopMetadata() const {
|
|
|
|
// If there is no loop metadata at all, we also don't have
|
|
|
|
// non-debug loop metadata, obviously.
|
|
|
|
if (!hasMetadata(LLVMContext::MD_loop))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// If we do have loop metadata, retrieve it.
|
|
|
|
MDNode *LoopMD = getMetadata(LLVMContext::MD_loop);
|
|
|
|
|
|
|
|
// Check if the existing operands are debug locations. This loop
|
|
|
|
// should terminate after at most three iterations. Skip
|
|
|
|
// the first item because it is a self-reference.
|
|
|
|
for (const MDOperand &Op : llvm::drop_begin(LoopMD->operands())) {
|
|
|
|
// check for debug location type by attempting a cast.
|
|
|
|
if (!dyn_cast<DILocation>(Op)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If we get here, then all we have is debug locations in the loop metadata.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2023-01-19 15:34:35 +01:00
|
|
|
void Instruction::dropPoisonGeneratingMetadata() {
|
2025-01-16 20:45:56 +00:00
|
|
|
for (unsigned ID : Metadata::PoisonGeneratingIDs)
|
|
|
|
eraseMetadata(ID);
|
2023-01-19 15:34:35 +01:00
|
|
|
}
|
|
|
|
|
2024-04-18 08:27:36 +02:00
|
|
|
bool Instruction::hasPoisonGeneratingReturnAttributes() const {
|
|
|
|
if (const auto *CB = dyn_cast<CallBase>(this)) {
|
|
|
|
AttributeSet RetAttrs = CB->getAttributes().getRetAttrs();
|
|
|
|
return RetAttrs.hasAttribute(Attribute::Range) ||
|
|
|
|
RetAttrs.hasAttribute(Attribute::Alignment) ||
|
|
|
|
RetAttrs.hasAttribute(Attribute::NonNull);
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::dropPoisonGeneratingReturnAttributes() {
|
|
|
|
if (auto *CB = dyn_cast<CallBase>(this)) {
|
|
|
|
AttributeMask AM;
|
|
|
|
AM.addAttribute(Attribute::Range);
|
|
|
|
AM.addAttribute(Attribute::Alignment);
|
|
|
|
AM.addAttribute(Attribute::NonNull);
|
|
|
|
CB->removeRetAttrs(AM);
|
|
|
|
}
|
|
|
|
assert(!hasPoisonGeneratingReturnAttributes() && "must be kept in sync");
|
|
|
|
}
|
|
|
|
|
2023-03-22 10:48:26 +01:00
|
|
|
void Instruction::dropUBImplyingAttrsAndUnknownMetadata(
|
2021-07-27 09:48:13 -04:00
|
|
|
ArrayRef<unsigned> KnownIDs) {
|
|
|
|
dropUnknownNonDebugMetadata(KnownIDs);
|
|
|
|
auto *CB = dyn_cast<CallBase>(this);
|
|
|
|
if (!CB)
|
|
|
|
return;
|
|
|
|
// For call instructions, we also need to drop parameter and return attributes
|
|
|
|
// that are can cause UB if the call is moved to a location where the
|
|
|
|
// attribute is not valid.
|
|
|
|
AttributeList AL = CB->getAttributes();
|
|
|
|
if (AL.isEmpty())
|
|
|
|
return;
|
2022-01-04 09:44:47 +01:00
|
|
|
AttributeMask UBImplyingAttributes =
|
|
|
|
AttributeFuncs::getUBImplyingAttributes();
|
2021-10-04 08:40:24 -07:00
|
|
|
for (unsigned ArgNo = 0; ArgNo < CB->arg_size(); ArgNo++)
|
2021-07-27 09:48:13 -04:00
|
|
|
CB->removeParamAttrs(ArgNo, UBImplyingAttributes);
|
2021-08-17 20:25:16 -07:00
|
|
|
CB->removeRetAttrs(UBImplyingAttributes);
|
2021-07-27 09:48:13 -04:00
|
|
|
}
|
2019-07-09 18:49:29 +00:00
|
|
|
|
2023-03-22 11:53:01 +01:00
|
|
|
void Instruction::dropUBImplyingAttrsAndMetadata() {
|
|
|
|
// !annotation metadata does not impact semantics.
|
|
|
|
// !range, !nonnull and !align produce poison, so they are safe to speculate.
|
|
|
|
// !noundef and various AA metadata must be dropped, as it generally produces
|
|
|
|
// immediate undefined behavior.
|
|
|
|
unsigned KnownIDs[] = {LLVMContext::MD_annotation, LLVMContext::MD_range,
|
|
|
|
LLVMContext::MD_nonnull, LLVMContext::MD_align};
|
|
|
|
dropUBImplyingAttrsAndUnknownMetadata(KnownIDs);
|
|
|
|
}
|
|
|
|
|
2016-04-22 06:37:45 +00:00
|
|
|
bool Instruction::isExact() const {
|
|
|
|
return cast<PossiblyExactOperator>(this)->isExact();
|
|
|
|
}
|
|
|
|
|
[IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag
As discussed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-November/107104.html
and again more recently:
http://lists.llvm.org/pipermail/llvm-dev/2017-October/118118.html
...this is a step in cleaning up our fast-math-flags implementation in IR to better match
the capabilities of both clang's user-visible flags and the backend's flags for SDNode.
As proposed in the above threads, we're replacing the 'UnsafeAlgebra' bit (which had the
'umbrella' meaning that all flags are set) with a new bit that only applies to algebraic
reassociation - 'AllowReassoc'.
We're also adding a bit to allow approximations for library functions called 'ApproxFunc'
(this was initially proposed as 'libm' or similar).
...and we're out of bits. 7 bits ought to be enough for anyone, right? :) FWIW, I did
look at getting this out of SubclassOptionalData via SubclassData (spacious 16-bits),
but that's apparently already used for other purposes. Also, I don't think we can just
add a field to FPMathOperator because Operator is not intended to be instantiated.
We'll defer movement of FMF to another day.
We keep the 'fast' keyword. I thought about removing that, but seeing IR like this:
%f.fast = fadd reassoc nnan ninf nsz arcp contract afn float %op1, %op2
...made me think we want to keep the shortcut synonym.
Finally, this change is binary incompatible with existing IR as seen in the
compatibility tests. This statement:
"Newer releases can ignore features from older releases, but they cannot miscompile
them. For example, if nsw is ever replaced with something else, dropping it would be
a valid way to upgrade the IR."
( http://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility )
...provides the flexibility we want to make this change without requiring a new IR
version. Ie, we're not loosening the FP strictness of existing IR. At worst, we will
fail to optimize some previously 'fast' code because it's no longer recognized as
'fast'. This should get fixed as we audit/squash all of the uses of 'isFast()'.
Note: an inter-dependent clang commit to use the new API name should closely follow
commit.
Differential Revision: https://reviews.llvm.org/D39304
llvm-svn: 317488
2017-11-06 16:27:15 +00:00
|
|
|
void Instruction::setFast(bool B) {
|
2012-11-27 00:41:22 +00:00
|
|
|
assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
|
[IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag
As discussed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-November/107104.html
and again more recently:
http://lists.llvm.org/pipermail/llvm-dev/2017-October/118118.html
...this is a step in cleaning up our fast-math-flags implementation in IR to better match
the capabilities of both clang's user-visible flags and the backend's flags for SDNode.
As proposed in the above threads, we're replacing the 'UnsafeAlgebra' bit (which had the
'umbrella' meaning that all flags are set) with a new bit that only applies to algebraic
reassociation - 'AllowReassoc'.
We're also adding a bit to allow approximations for library functions called 'ApproxFunc'
(this was initially proposed as 'libm' or similar).
...and we're out of bits. 7 bits ought to be enough for anyone, right? :) FWIW, I did
look at getting this out of SubclassOptionalData via SubclassData (spacious 16-bits),
but that's apparently already used for other purposes. Also, I don't think we can just
add a field to FPMathOperator because Operator is not intended to be instantiated.
We'll defer movement of FMF to another day.
We keep the 'fast' keyword. I thought about removing that, but seeing IR like this:
%f.fast = fadd reassoc nnan ninf nsz arcp contract afn float %op1, %op2
...made me think we want to keep the shortcut synonym.
Finally, this change is binary incompatible with existing IR as seen in the
compatibility tests. This statement:
"Newer releases can ignore features from older releases, but they cannot miscompile
them. For example, if nsw is ever replaced with something else, dropping it would be
a valid way to upgrade the IR."
( http://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility )
...provides the flexibility we want to make this change without requiring a new IR
version. Ie, we're not loosening the FP strictness of existing IR. At worst, we will
fail to optimize some previously 'fast' code because it's no longer recognized as
'fast'. This should get fixed as we audit/squash all of the uses of 'isFast()'.
Note: an inter-dependent clang commit to use the new API name should closely follow
commit.
Differential Revision: https://reviews.llvm.org/D39304
llvm-svn: 317488
2017-11-06 16:27:15 +00:00
|
|
|
cast<FPMathOperator>(this)->setFast(B);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::setHasAllowReassoc(bool B) {
|
|
|
|
assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
|
|
|
|
cast<FPMathOperator>(this)->setHasAllowReassoc(B);
|
2012-11-27 00:41:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::setHasNoNaNs(bool B) {
|
|
|
|
assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
|
|
|
|
cast<FPMathOperator>(this)->setHasNoNaNs(B);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::setHasNoInfs(bool B) {
|
|
|
|
assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
|
|
|
|
cast<FPMathOperator>(this)->setHasNoInfs(B);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::setHasNoSignedZeros(bool B) {
|
|
|
|
assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
|
|
|
|
cast<FPMathOperator>(this)->setHasNoSignedZeros(B);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::setHasAllowReciprocal(bool B) {
|
|
|
|
assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
|
|
|
|
cast<FPMathOperator>(this)->setHasAllowReciprocal(B);
|
|
|
|
}
|
|
|
|
|
2020-05-27 08:29:09 -04:00
|
|
|
void Instruction::setHasAllowContract(bool B) {
|
|
|
|
assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
|
|
|
|
cast<FPMathOperator>(this)->setHasAllowContract(B);
|
|
|
|
}
|
|
|
|
|
[IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag
As discussed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-November/107104.html
and again more recently:
http://lists.llvm.org/pipermail/llvm-dev/2017-October/118118.html
...this is a step in cleaning up our fast-math-flags implementation in IR to better match
the capabilities of both clang's user-visible flags and the backend's flags for SDNode.
As proposed in the above threads, we're replacing the 'UnsafeAlgebra' bit (which had the
'umbrella' meaning that all flags are set) with a new bit that only applies to algebraic
reassociation - 'AllowReassoc'.
We're also adding a bit to allow approximations for library functions called 'ApproxFunc'
(this was initially proposed as 'libm' or similar).
...and we're out of bits. 7 bits ought to be enough for anyone, right? :) FWIW, I did
look at getting this out of SubclassOptionalData via SubclassData (spacious 16-bits),
but that's apparently already used for other purposes. Also, I don't think we can just
add a field to FPMathOperator because Operator is not intended to be instantiated.
We'll defer movement of FMF to another day.
We keep the 'fast' keyword. I thought about removing that, but seeing IR like this:
%f.fast = fadd reassoc nnan ninf nsz arcp contract afn float %op1, %op2
...made me think we want to keep the shortcut synonym.
Finally, this change is binary incompatible with existing IR as seen in the
compatibility tests. This statement:
"Newer releases can ignore features from older releases, but they cannot miscompile
them. For example, if nsw is ever replaced with something else, dropping it would be
a valid way to upgrade the IR."
( http://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility )
...provides the flexibility we want to make this change without requiring a new IR
version. Ie, we're not loosening the FP strictness of existing IR. At worst, we will
fail to optimize some previously 'fast' code because it's no longer recognized as
'fast'. This should get fixed as we audit/squash all of the uses of 'isFast()'.
Note: an inter-dependent clang commit to use the new API name should closely follow
commit.
Differential Revision: https://reviews.llvm.org/D39304
llvm-svn: 317488
2017-11-06 16:27:15 +00:00
|
|
|
void Instruction::setHasApproxFunc(bool B) {
|
|
|
|
assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
|
|
|
|
cast<FPMathOperator>(this)->setHasApproxFunc(B);
|
|
|
|
}
|
|
|
|
|
2012-11-27 00:41:22 +00:00
|
|
|
void Instruction::setFastMathFlags(FastMathFlags FMF) {
|
|
|
|
assert(isa<FPMathOperator>(this) && "setting fast-math flag on invalid op");
|
|
|
|
cast<FPMathOperator>(this)->setFastMathFlags(FMF);
|
|
|
|
}
|
|
|
|
|
2014-09-02 20:03:00 +00:00
|
|
|
void Instruction::copyFastMathFlags(FastMathFlags FMF) {
|
|
|
|
assert(isa<FPMathOperator>(this) && "copying fast-math flag on invalid op");
|
|
|
|
cast<FPMathOperator>(this)->copyFastMathFlags(FMF);
|
|
|
|
}
|
|
|
|
|
[IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag
As discussed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-November/107104.html
and again more recently:
http://lists.llvm.org/pipermail/llvm-dev/2017-October/118118.html
...this is a step in cleaning up our fast-math-flags implementation in IR to better match
the capabilities of both clang's user-visible flags and the backend's flags for SDNode.
As proposed in the above threads, we're replacing the 'UnsafeAlgebra' bit (which had the
'umbrella' meaning that all flags are set) with a new bit that only applies to algebraic
reassociation - 'AllowReassoc'.
We're also adding a bit to allow approximations for library functions called 'ApproxFunc'
(this was initially proposed as 'libm' or similar).
...and we're out of bits. 7 bits ought to be enough for anyone, right? :) FWIW, I did
look at getting this out of SubclassOptionalData via SubclassData (spacious 16-bits),
but that's apparently already used for other purposes. Also, I don't think we can just
add a field to FPMathOperator because Operator is not intended to be instantiated.
We'll defer movement of FMF to another day.
We keep the 'fast' keyword. I thought about removing that, but seeing IR like this:
%f.fast = fadd reassoc nnan ninf nsz arcp contract afn float %op1, %op2
...made me think we want to keep the shortcut synonym.
Finally, this change is binary incompatible with existing IR as seen in the
compatibility tests. This statement:
"Newer releases can ignore features from older releases, but they cannot miscompile
them. For example, if nsw is ever replaced with something else, dropping it would be
a valid way to upgrade the IR."
( http://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility )
...provides the flexibility we want to make this change without requiring a new IR
version. Ie, we're not loosening the FP strictness of existing IR. At worst, we will
fail to optimize some previously 'fast' code because it's no longer recognized as
'fast'. This should get fixed as we audit/squash all of the uses of 'isFast()'.
Note: an inter-dependent clang commit to use the new API name should closely follow
commit.
Differential Revision: https://reviews.llvm.org/D39304
llvm-svn: 317488
2017-11-06 16:27:15 +00:00
|
|
|
bool Instruction::isFast() const {
|
2014-06-11 18:26:29 +00:00
|
|
|
assert(isa<FPMathOperator>(this) && "getting fast-math flag on invalid op");
|
[IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag
As discussed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-November/107104.html
and again more recently:
http://lists.llvm.org/pipermail/llvm-dev/2017-October/118118.html
...this is a step in cleaning up our fast-math-flags implementation in IR to better match
the capabilities of both clang's user-visible flags and the backend's flags for SDNode.
As proposed in the above threads, we're replacing the 'UnsafeAlgebra' bit (which had the
'umbrella' meaning that all flags are set) with a new bit that only applies to algebraic
reassociation - 'AllowReassoc'.
We're also adding a bit to allow approximations for library functions called 'ApproxFunc'
(this was initially proposed as 'libm' or similar).
...and we're out of bits. 7 bits ought to be enough for anyone, right? :) FWIW, I did
look at getting this out of SubclassOptionalData via SubclassData (spacious 16-bits),
but that's apparently already used for other purposes. Also, I don't think we can just
add a field to FPMathOperator because Operator is not intended to be instantiated.
We'll defer movement of FMF to another day.
We keep the 'fast' keyword. I thought about removing that, but seeing IR like this:
%f.fast = fadd reassoc nnan ninf nsz arcp contract afn float %op1, %op2
...made me think we want to keep the shortcut synonym.
Finally, this change is binary incompatible with existing IR as seen in the
compatibility tests. This statement:
"Newer releases can ignore features from older releases, but they cannot miscompile
them. For example, if nsw is ever replaced with something else, dropping it would be
a valid way to upgrade the IR."
( http://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility )
...provides the flexibility we want to make this change without requiring a new IR
version. Ie, we're not loosening the FP strictness of existing IR. At worst, we will
fail to optimize some previously 'fast' code because it's no longer recognized as
'fast'. This should get fixed as we audit/squash all of the uses of 'isFast()'.
Note: an inter-dependent clang commit to use the new API name should closely follow
commit.
Differential Revision: https://reviews.llvm.org/D39304
llvm-svn: 317488
2017-11-06 16:27:15 +00:00
|
|
|
return cast<FPMathOperator>(this)->isFast();
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Instruction::hasAllowReassoc() const {
|
|
|
|
assert(isa<FPMathOperator>(this) && "getting fast-math flag on invalid op");
|
|
|
|
return cast<FPMathOperator>(this)->hasAllowReassoc();
|
2012-11-27 00:41:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool Instruction::hasNoNaNs() const {
|
2014-06-11 18:26:29 +00:00
|
|
|
assert(isa<FPMathOperator>(this) && "getting fast-math flag on invalid op");
|
2012-11-27 00:41:22 +00:00
|
|
|
return cast<FPMathOperator>(this)->hasNoNaNs();
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Instruction::hasNoInfs() const {
|
2014-06-11 18:26:29 +00:00
|
|
|
assert(isa<FPMathOperator>(this) && "getting fast-math flag on invalid op");
|
2012-11-27 00:41:22 +00:00
|
|
|
return cast<FPMathOperator>(this)->hasNoInfs();
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Instruction::hasNoSignedZeros() const {
|
2014-06-11 18:26:29 +00:00
|
|
|
assert(isa<FPMathOperator>(this) && "getting fast-math flag on invalid op");
|
2012-11-27 00:41:22 +00:00
|
|
|
return cast<FPMathOperator>(this)->hasNoSignedZeros();
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Instruction::hasAllowReciprocal() const {
|
2014-06-11 18:26:29 +00:00
|
|
|
assert(isa<FPMathOperator>(this) && "getting fast-math flag on invalid op");
|
2012-11-27 00:41:22 +00:00
|
|
|
return cast<FPMathOperator>(this)->hasAllowReciprocal();
|
|
|
|
}
|
|
|
|
|
2017-03-28 20:11:52 +00:00
|
|
|
bool Instruction::hasAllowContract() const {
|
|
|
|
assert(isa<FPMathOperator>(this) && "getting fast-math flag on invalid op");
|
|
|
|
return cast<FPMathOperator>(this)->hasAllowContract();
|
|
|
|
}
|
|
|
|
|
[IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag
As discussed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-November/107104.html
and again more recently:
http://lists.llvm.org/pipermail/llvm-dev/2017-October/118118.html
...this is a step in cleaning up our fast-math-flags implementation in IR to better match
the capabilities of both clang's user-visible flags and the backend's flags for SDNode.
As proposed in the above threads, we're replacing the 'UnsafeAlgebra' bit (which had the
'umbrella' meaning that all flags are set) with a new bit that only applies to algebraic
reassociation - 'AllowReassoc'.
We're also adding a bit to allow approximations for library functions called 'ApproxFunc'
(this was initially proposed as 'libm' or similar).
...and we're out of bits. 7 bits ought to be enough for anyone, right? :) FWIW, I did
look at getting this out of SubclassOptionalData via SubclassData (spacious 16-bits),
but that's apparently already used for other purposes. Also, I don't think we can just
add a field to FPMathOperator because Operator is not intended to be instantiated.
We'll defer movement of FMF to another day.
We keep the 'fast' keyword. I thought about removing that, but seeing IR like this:
%f.fast = fadd reassoc nnan ninf nsz arcp contract afn float %op1, %op2
...made me think we want to keep the shortcut synonym.
Finally, this change is binary incompatible with existing IR as seen in the
compatibility tests. This statement:
"Newer releases can ignore features from older releases, but they cannot miscompile
them. For example, if nsw is ever replaced with something else, dropping it would be
a valid way to upgrade the IR."
( http://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility )
...provides the flexibility we want to make this change without requiring a new IR
version. Ie, we're not loosening the FP strictness of existing IR. At worst, we will
fail to optimize some previously 'fast' code because it's no longer recognized as
'fast'. This should get fixed as we audit/squash all of the uses of 'isFast()'.
Note: an inter-dependent clang commit to use the new API name should closely follow
commit.
Differential Revision: https://reviews.llvm.org/D39304
llvm-svn: 317488
2017-11-06 16:27:15 +00:00
|
|
|
bool Instruction::hasApproxFunc() const {
|
|
|
|
assert(isa<FPMathOperator>(this) && "getting fast-math flag on invalid op");
|
|
|
|
return cast<FPMathOperator>(this)->hasApproxFunc();
|
|
|
|
}
|
|
|
|
|
2012-11-27 00:41:22 +00:00
|
|
|
FastMathFlags Instruction::getFastMathFlags() const {
|
2014-06-11 18:26:29 +00:00
|
|
|
assert(isa<FPMathOperator>(this) && "getting fast-math flag on invalid op");
|
2012-11-27 00:41:22 +00:00
|
|
|
return cast<FPMathOperator>(this)->getFastMathFlags();
|
|
|
|
}
|
2005-08-08 05:21:50 +00:00
|
|
|
|
2012-11-29 21:25:12 +00:00
|
|
|
void Instruction::copyFastMathFlags(const Instruction *I) {
|
2014-09-02 20:03:00 +00:00
|
|
|
copyFastMathFlags(I->getFastMathFlags());
|
2012-11-29 21:25:12 +00:00
|
|
|
}
|
|
|
|
|
[LoopVectorize] Don't preserve nsw/nuw flags on shrunken ops.
If we're shrinking a binary operation, it may be the case that the new
operations wraps where the old didn't. If this happens, the behavior
should be well-defined. So, we can't always carry wrapping flags with us
when we shrink operations.
If we do, we get incorrect optimizations in cases like:
void foo(const unsigned char *from, unsigned char *to, int n) {
for (int i = 0; i < n; i++)
to[i] = from[i] - 128;
}
which gets optimized to:
void foo(const unsigned char *from, unsigned char *to, int n) {
for (int i = 0; i < n; i++)
to[i] = from[i] | 128;
}
Because:
- InstCombine turned `sub i32 %from.i, 128` into
`add nuw nsw i32 %from.i, 128`.
- LoopVectorize vectorized the add to be `add nuw nsw <16 x i8>` with a
vector full of `i8 128`s
- InstCombine took advantage of the fact that the newly-shrunken add
"couldn't wrap", and changed the `add` to an `or`.
InstCombine seems happy to figure out whether we can add nuw/nsw on its
own, so I just decided to drop the flags. There are already a number of
places in LoopVectorize where we rely on InstCombine to clean up.
llvm-svn: 305053
2017-06-09 03:56:15 +00:00
|
|
|
void Instruction::copyIRFlags(const Value *V, bool IncludeWrapFlags) {
|
2016-04-22 06:37:45 +00:00
|
|
|
// Copy the wrapping flags.
|
[LoopVectorize] Don't preserve nsw/nuw flags on shrunken ops.
If we're shrinking a binary operation, it may be the case that the new
operations wraps where the old didn't. If this happens, the behavior
should be well-defined. So, we can't always carry wrapping flags with us
when we shrink operations.
If we do, we get incorrect optimizations in cases like:
void foo(const unsigned char *from, unsigned char *to, int n) {
for (int i = 0; i < n; i++)
to[i] = from[i] - 128;
}
which gets optimized to:
void foo(const unsigned char *from, unsigned char *to, int n) {
for (int i = 0; i < n; i++)
to[i] = from[i] | 128;
}
Because:
- InstCombine turned `sub i32 %from.i, 128` into
`add nuw nsw i32 %from.i, 128`.
- LoopVectorize vectorized the add to be `add nuw nsw <16 x i8>` with a
vector full of `i8 128`s
- InstCombine took advantage of the fact that the newly-shrunken add
"couldn't wrap", and changed the `add` to an `or`.
InstCombine seems happy to figure out whether we can add nuw/nsw on its
own, so I just decided to drop the flags. There are already a number of
places in LoopVectorize where we rely on InstCombine to clean up.
llvm-svn: 305053
2017-06-09 03:56:15 +00:00
|
|
|
if (IncludeWrapFlags && isa<OverflowingBinaryOperator>(this)) {
|
|
|
|
if (auto *OB = dyn_cast<OverflowingBinaryOperator>(V)) {
|
2016-04-22 06:37:51 +00:00
|
|
|
setHasNoSignedWrap(OB->hasNoSignedWrap());
|
|
|
|
setHasNoUnsignedWrap(OB->hasNoUnsignedWrap());
|
|
|
|
}
|
2016-04-22 06:37:45 +00:00
|
|
|
}
|
|
|
|
|
2024-04-19 17:10:35 +08:00
|
|
|
if (auto *TI = dyn_cast<TruncInst>(V)) {
|
|
|
|
if (isa<TruncInst>(this)) {
|
|
|
|
setHasNoSignedWrap(TI->hasNoSignedWrap());
|
|
|
|
setHasNoUnsignedWrap(TI->hasNoUnsignedWrap());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-04-22 06:37:45 +00:00
|
|
|
// Copy the exact flag.
|
|
|
|
if (auto *PE = dyn_cast<PossiblyExactOperator>(V))
|
2016-04-22 06:37:51 +00:00
|
|
|
if (isa<PossiblyExactOperator>(this))
|
|
|
|
setIsExact(PE->isExact());
|
2016-04-22 06:37:45 +00:00
|
|
|
|
2023-11-24 08:49:19 -08:00
|
|
|
if (auto *SrcPD = dyn_cast<PossiblyDisjointInst>(V))
|
|
|
|
if (auto *DestPD = dyn_cast<PossiblyDisjointInst>(this))
|
|
|
|
DestPD->setIsDisjoint(SrcPD->isDisjoint());
|
|
|
|
|
2016-04-22 06:37:45 +00:00
|
|
|
// Copy the fast-math flags.
|
|
|
|
if (auto *FP = dyn_cast<FPMathOperator>(V))
|
2016-04-22 06:37:51 +00:00
|
|
|
if (isa<FPMathOperator>(this))
|
|
|
|
copyFastMathFlags(FP->getFastMathFlags());
|
2016-07-15 05:02:31 +00:00
|
|
|
|
|
|
|
if (auto *SrcGEP = dyn_cast<GetElementPtrInst>(V))
|
|
|
|
if (auto *DestGEP = dyn_cast<GetElementPtrInst>(this))
|
2024-05-27 16:05:17 +02:00
|
|
|
DestGEP->setNoWrapFlags(SrcGEP->getNoWrapFlags() |
|
|
|
|
DestGEP->getNoWrapFlags());
|
2023-10-30 09:04:04 +01:00
|
|
|
|
|
|
|
if (auto *NNI = dyn_cast<PossiblyNonNegInst>(V))
|
|
|
|
if (isa<PossiblyNonNegInst>(this))
|
|
|
|
setNonNeg(NNI->hasNonNeg());
|
2024-10-15 12:11:25 +03:00
|
|
|
|
|
|
|
if (auto *SrcICmp = dyn_cast<ICmpInst>(V))
|
|
|
|
if (auto *DestICmp = dyn_cast<ICmpInst>(this))
|
|
|
|
DestICmp->setSameSign(SrcICmp->hasSameSign());
|
2016-04-22 06:37:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::andIRFlags(const Value *V) {
|
|
|
|
if (auto *OB = dyn_cast<OverflowingBinaryOperator>(V)) {
|
2016-04-22 06:37:51 +00:00
|
|
|
if (isa<OverflowingBinaryOperator>(this)) {
|
2021-10-03 13:57:57 +02:00
|
|
|
setHasNoSignedWrap(hasNoSignedWrap() && OB->hasNoSignedWrap());
|
|
|
|
setHasNoUnsignedWrap(hasNoUnsignedWrap() && OB->hasNoUnsignedWrap());
|
2016-04-22 06:37:51 +00:00
|
|
|
}
|
2016-04-22 06:37:45 +00:00
|
|
|
}
|
|
|
|
|
2024-03-29 08:08:49 +02:00
|
|
|
if (auto *TI = dyn_cast<TruncInst>(V)) {
|
|
|
|
if (isa<TruncInst>(this)) {
|
|
|
|
setHasNoSignedWrap(hasNoSignedWrap() && TI->hasNoSignedWrap());
|
|
|
|
setHasNoUnsignedWrap(hasNoUnsignedWrap() && TI->hasNoUnsignedWrap());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-04-22 06:37:45 +00:00
|
|
|
if (auto *PE = dyn_cast<PossiblyExactOperator>(V))
|
2016-04-22 06:37:51 +00:00
|
|
|
if (isa<PossiblyExactOperator>(this))
|
2021-10-03 13:57:57 +02:00
|
|
|
setIsExact(isExact() && PE->isExact());
|
2016-04-22 06:37:45 +00:00
|
|
|
|
2023-11-24 08:49:19 -08:00
|
|
|
if (auto *SrcPD = dyn_cast<PossiblyDisjointInst>(V))
|
|
|
|
if (auto *DestPD = dyn_cast<PossiblyDisjointInst>(this))
|
|
|
|
DestPD->setIsDisjoint(DestPD->isDisjoint() && SrcPD->isDisjoint());
|
|
|
|
|
2016-04-22 06:37:45 +00:00
|
|
|
if (auto *FP = dyn_cast<FPMathOperator>(V)) {
|
2016-04-22 06:37:51 +00:00
|
|
|
if (isa<FPMathOperator>(this)) {
|
|
|
|
FastMathFlags FM = getFastMathFlags();
|
|
|
|
FM &= FP->getFastMathFlags();
|
|
|
|
copyFastMathFlags(FM);
|
|
|
|
}
|
2016-04-22 06:37:45 +00:00
|
|
|
}
|
2016-07-15 05:02:31 +00:00
|
|
|
|
|
|
|
if (auto *SrcGEP = dyn_cast<GetElementPtrInst>(V))
|
|
|
|
if (auto *DestGEP = dyn_cast<GetElementPtrInst>(this))
|
2024-05-27 16:05:17 +02:00
|
|
|
DestGEP->setNoWrapFlags(SrcGEP->getNoWrapFlags() &
|
|
|
|
DestGEP->getNoWrapFlags());
|
2023-10-30 09:04:04 +01:00
|
|
|
|
|
|
|
if (auto *NNI = dyn_cast<PossiblyNonNegInst>(V))
|
|
|
|
if (isa<PossiblyNonNegInst>(this))
|
|
|
|
setNonNeg(hasNonNeg() && NNI->hasNonNeg());
|
2024-10-15 12:11:25 +03:00
|
|
|
|
|
|
|
if (auto *SrcICmp = dyn_cast<ICmpInst>(V))
|
|
|
|
if (auto *DestICmp = dyn_cast<ICmpInst>(this))
|
|
|
|
DestICmp->setSameSign(DestICmp->hasSameSign() && SrcICmp->hasSameSign());
|
2016-04-22 06:37:45 +00:00
|
|
|
}
|
2012-11-29 21:25:12 +00:00
|
|
|
|
2002-07-14 23:09:40 +00:00
|
|
|
const char *Instruction::getOpcodeName(unsigned OpCode) {
|
|
|
|
switch (OpCode) {
|
|
|
|
// Terminators
|
2002-08-14 18:18:02 +00:00
|
|
|
case Ret: return "ret";
|
|
|
|
case Br: return "br";
|
2002-07-14 23:09:40 +00:00
|
|
|
case Switch: return "switch";
|
2009-10-28 00:19:10 +00:00
|
|
|
case IndirectBr: return "indirectbr";
|
2002-07-14 23:09:40 +00:00
|
|
|
case Invoke: return "invoke";
|
2011-07-31 06:30:59 +00:00
|
|
|
case Resume: return "resume";
|
2004-10-16 18:08:06 +00:00
|
|
|
case Unreachable: return "unreachable";
|
2015-07-31 17:58:14 +00:00
|
|
|
case CleanupRet: return "cleanupret";
|
|
|
|
case CatchRet: return "catchret";
|
|
|
|
case CatchPad: return "catchpad";
|
[IR] Reformulate LLVM's EH funclet IR
While we have successfully implemented a funclet-oriented EH scheme on
top of LLVM IR, our scheme has some notable deficiencies:
- catchendpad and cleanupendpad are necessary in the current design
but they are difficult to explain to others, even to seasoned LLVM
experts.
- catchendpad and cleanupendpad are optimization barriers. They cannot
be split and force all potentially throwing call-sites to be invokes.
This has a noticable effect on the quality of our code generation.
- catchpad, while similar in some aspects to invoke, is fairly awkward.
It is unsplittable, starts a funclet, and has control flow to other
funclets.
- The nesting relationship between funclets is currently a property of
control flow edges. Because of this, we are forced to carefully
analyze the flow graph to see if there might potentially exist illegal
nesting among funclets. While we have logic to clone funclets when
they are illegally nested, it would be nicer if we had a
representation which forbade them upfront.
Let's clean this up a bit by doing the following:
- Instead, make catchpad more like cleanuppad and landingpad: no control
flow, just a bunch of simple operands; catchpad would be splittable.
- Introduce catchswitch, a control flow instruction designed to model
the constraints of funclet oriented EH.
- Make funclet scoping explicit by having funclet instructions consume
the token produced by the funclet which contains them.
- Remove catchendpad and cleanupendpad. Their presence can be inferred
implicitly using coloring information.
N.B. The state numbering code for the CLR has been updated but the
veracity of it's output cannot be spoken for. An expert should take a
look to make sure the results are reasonable.
Reviewers: rnk, JosephTremoulet, andrew.w.kaylor
Differential Revision: http://reviews.llvm.org/D15139
llvm-svn: 255422
2015-12-12 05:38:55 +00:00
|
|
|
case CatchSwitch: return "catchswitch";
|
2019-02-08 20:48:56 +00:00
|
|
|
case CallBr: return "callbr";
|
2005-04-21 23:48:37 +00:00
|
|
|
|
2018-11-13 18:15:47 +00:00
|
|
|
// Standard unary operators...
|
|
|
|
case FNeg: return "fneg";
|
|
|
|
|
2002-07-14 23:09:40 +00:00
|
|
|
// Standard binary operators...
|
|
|
|
case Add: return "add";
|
2009-06-04 22:49:04 +00:00
|
|
|
case FAdd: return "fadd";
|
2002-07-14 23:09:40 +00:00
|
|
|
case Sub: return "sub";
|
2009-06-04 22:49:04 +00:00
|
|
|
case FSub: return "fsub";
|
2002-07-14 23:09:40 +00:00
|
|
|
case Mul: return "mul";
|
2009-06-04 22:49:04 +00:00
|
|
|
case FMul: return "fmul";
|
2006-10-26 06:15:43 +00:00
|
|
|
case UDiv: return "udiv";
|
|
|
|
case SDiv: return "sdiv";
|
|
|
|
case FDiv: return "fdiv";
|
2006-11-02 01:53:59 +00:00
|
|
|
case URem: return "urem";
|
|
|
|
case SRem: return "srem";
|
|
|
|
case FRem: return "frem";
|
2002-07-14 23:09:40 +00:00
|
|
|
|
|
|
|
// Logical operators...
|
|
|
|
case And: return "and";
|
|
|
|
case Or : return "or";
|
|
|
|
case Xor: return "xor";
|
|
|
|
|
|
|
|
// Memory instructions...
|
|
|
|
case Alloca: return "alloca";
|
|
|
|
case Load: return "load";
|
|
|
|
case Store: return "store";
|
2011-07-28 21:48:00 +00:00
|
|
|
case AtomicCmpXchg: return "cmpxchg";
|
|
|
|
case AtomicRMW: return "atomicrmw";
|
2011-07-25 23:16:38 +00:00
|
|
|
case Fence: return "fence";
|
2002-07-14 23:09:40 +00:00
|
|
|
case GetElementPtr: return "getelementptr";
|
2005-04-21 23:48:37 +00:00
|
|
|
|
2006-11-27 01:05:10 +00:00
|
|
|
// Convert instructions...
|
2013-11-15 01:34:59 +00:00
|
|
|
case Trunc: return "trunc";
|
|
|
|
case ZExt: return "zext";
|
|
|
|
case SExt: return "sext";
|
|
|
|
case FPTrunc: return "fptrunc";
|
|
|
|
case FPExt: return "fpext";
|
|
|
|
case FPToUI: return "fptoui";
|
|
|
|
case FPToSI: return "fptosi";
|
|
|
|
case UIToFP: return "uitofp";
|
|
|
|
case SIToFP: return "sitofp";
|
|
|
|
case IntToPtr: return "inttoptr";
|
|
|
|
case PtrToInt: return "ptrtoint";
|
|
|
|
case BitCast: return "bitcast";
|
|
|
|
case AddrSpaceCast: return "addrspacecast";
|
2006-11-27 01:05:10 +00:00
|
|
|
|
2002-07-14 23:09:40 +00:00
|
|
|
// Other instructions...
|
2006-12-03 06:27:29 +00:00
|
|
|
case ICmp: return "icmp";
|
|
|
|
case FCmp: return "fcmp";
|
2006-11-27 01:05:10 +00:00
|
|
|
case PHI: return "phi";
|
|
|
|
case Select: return "select";
|
|
|
|
case Call: return "call";
|
|
|
|
case Shl: return "shl";
|
|
|
|
case LShr: return "lshr";
|
|
|
|
case AShr: return "ashr";
|
|
|
|
case VAArg: return "va_arg";
|
2006-01-10 19:05:34 +00:00
|
|
|
case ExtractElement: return "extractelement";
|
2006-11-27 01:05:10 +00:00
|
|
|
case InsertElement: return "insertelement";
|
|
|
|
case ShuffleVector: return "shufflevector";
|
2008-05-30 10:31:54 +00:00
|
|
|
case ExtractValue: return "extractvalue";
|
|
|
|
case InsertValue: return "insertvalue";
|
2011-08-12 20:24:12 +00:00
|
|
|
case LandingPad: return "landingpad";
|
2015-08-23 00:26:33 +00:00
|
|
|
case CleanupPad: return "cleanuppad";
|
[IR] Redefine Freeze instruction
Summary:
This patch redefines freeze instruction from being UnaryOperator to a subclass of UnaryInstruction.
ConstantExpr freeze is removed, as discussed in the previous review.
FreezeOperator is not added because there's no ConstantExpr freeze.
`freeze i8* null` test is added to `test/Bindings/llvm-c/freeze.ll` as well, because the null pointer-related bug in `tools/llvm-c/echo.cpp` is now fixed.
InstVisitor has visitFreeze now because freeze is not unaryop anymore.
Reviewers: whitequark, deadalnix, craig.topper, jdoerfert, lebedev.ri
Reviewed By: craig.topper, lebedev.ri
Subscribers: regehr, nlopes, mehdi_amini, hiraditya, steven_wu, dexonsmith, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69932
2019-11-07 01:17:49 +09:00
|
|
|
case Freeze: return "freeze";
|
2003-05-08 02:44:12 +00:00
|
|
|
|
2002-07-14 23:09:40 +00:00
|
|
|
default: return "<Invalid operator> ";
|
|
|
|
}
|
|
|
|
}
|
2002-10-31 04:14:01 +00:00
|
|
|
|
2023-03-28 16:47:58 -07:00
|
|
|
/// This must be kept in sync with FunctionComparator::cmpOperations in
|
2016-04-11 22:30:37 +00:00
|
|
|
/// lib/Transforms/IPO/MergeFunctions.cpp.
|
2023-03-28 16:47:58 -07:00
|
|
|
bool Instruction::hasSameSpecialState(const Instruction *I2,
|
2024-09-20 15:02:59 -05:00
|
|
|
bool IgnoreAlignment,
|
|
|
|
bool IntersectAttrs) const {
|
2023-03-28 16:47:58 -07:00
|
|
|
auto I1 = this;
|
2014-05-27 21:35:46 +00:00
|
|
|
assert(I1->getOpcode() == I2->getOpcode() &&
|
|
|
|
"Can not compare special state of different instructions");
|
|
|
|
|
2024-09-20 15:02:59 -05:00
|
|
|
auto CheckAttrsSame = [IntersectAttrs](const CallBase *CB0,
|
|
|
|
const CallBase *CB1) {
|
|
|
|
return IntersectAttrs
|
|
|
|
? CB0->getAttributes()
|
|
|
|
.intersectWith(CB0->getContext(), CB1->getAttributes())
|
|
|
|
.has_value()
|
|
|
|
: CB0->getAttributes() == CB1->getAttributes();
|
|
|
|
};
|
|
|
|
|
2016-04-12 18:06:55 +00:00
|
|
|
if (const AllocaInst *AI = dyn_cast<AllocaInst>(I1))
|
|
|
|
return AI->getAllocatedType() == cast<AllocaInst>(I2)->getAllocatedType() &&
|
2021-12-09 13:19:09 -08:00
|
|
|
(AI->getAlign() == cast<AllocaInst>(I2)->getAlign() ||
|
2016-04-12 18:06:55 +00:00
|
|
|
IgnoreAlignment);
|
2014-05-27 21:35:46 +00:00
|
|
|
if (const LoadInst *LI = dyn_cast<LoadInst>(I1))
|
|
|
|
return LI->isVolatile() == cast<LoadInst>(I2)->isVolatile() &&
|
2021-12-09 13:19:09 -08:00
|
|
|
(LI->getAlign() == cast<LoadInst>(I2)->getAlign() ||
|
2014-05-27 21:35:46 +00:00
|
|
|
IgnoreAlignment) &&
|
|
|
|
LI->getOrdering() == cast<LoadInst>(I2)->getOrdering() &&
|
2017-07-11 22:23:00 +00:00
|
|
|
LI->getSyncScopeID() == cast<LoadInst>(I2)->getSyncScopeID();
|
2014-05-27 21:35:46 +00:00
|
|
|
if (const StoreInst *SI = dyn_cast<StoreInst>(I1))
|
|
|
|
return SI->isVolatile() == cast<StoreInst>(I2)->isVolatile() &&
|
2021-12-09 13:19:09 -08:00
|
|
|
(SI->getAlign() == cast<StoreInst>(I2)->getAlign() ||
|
2014-05-27 21:35:46 +00:00
|
|
|
IgnoreAlignment) &&
|
|
|
|
SI->getOrdering() == cast<StoreInst>(I2)->getOrdering() &&
|
2017-07-11 22:23:00 +00:00
|
|
|
SI->getSyncScopeID() == cast<StoreInst>(I2)->getSyncScopeID();
|
2014-05-27 21:35:46 +00:00
|
|
|
if (const CmpInst *CI = dyn_cast<CmpInst>(I1))
|
|
|
|
return CI->getPredicate() == cast<CmpInst>(I2)->getPredicate();
|
|
|
|
if (const CallInst *CI = dyn_cast<CallInst>(I1))
|
|
|
|
return CI->isTailCall() == cast<CallInst>(I2)->isTailCall() &&
|
|
|
|
CI->getCallingConv() == cast<CallInst>(I2)->getCallingConv() &&
|
2024-09-20 15:02:59 -05:00
|
|
|
CheckAttrsSame(CI, cast<CallInst>(I2)) &&
|
2015-12-14 19:11:35 +00:00
|
|
|
CI->hasIdenticalOperandBundleSchema(*cast<CallInst>(I2));
|
2014-05-27 21:35:46 +00:00
|
|
|
if (const InvokeInst *CI = dyn_cast<InvokeInst>(I1))
|
|
|
|
return CI->getCallingConv() == cast<InvokeInst>(I2)->getCallingConv() &&
|
2024-09-20 15:02:59 -05:00
|
|
|
CheckAttrsSame(CI, cast<InvokeInst>(I2)) &&
|
2015-12-14 19:11:35 +00:00
|
|
|
CI->hasIdenticalOperandBundleSchema(*cast<InvokeInst>(I2));
|
2019-02-08 20:48:56 +00:00
|
|
|
if (const CallBrInst *CI = dyn_cast<CallBrInst>(I1))
|
|
|
|
return CI->getCallingConv() == cast<CallBrInst>(I2)->getCallingConv() &&
|
2024-09-20 15:02:59 -05:00
|
|
|
CheckAttrsSame(CI, cast<CallBrInst>(I2)) &&
|
2019-02-08 20:48:56 +00:00
|
|
|
CI->hasIdenticalOperandBundleSchema(*cast<CallBrInst>(I2));
|
2014-05-27 21:35:46 +00:00
|
|
|
if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(I1))
|
|
|
|
return IVI->getIndices() == cast<InsertValueInst>(I2)->getIndices();
|
|
|
|
if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(I1))
|
|
|
|
return EVI->getIndices() == cast<ExtractValueInst>(I2)->getIndices();
|
|
|
|
if (const FenceInst *FI = dyn_cast<FenceInst>(I1))
|
|
|
|
return FI->getOrdering() == cast<FenceInst>(I2)->getOrdering() &&
|
2017-07-11 22:23:00 +00:00
|
|
|
FI->getSyncScopeID() == cast<FenceInst>(I2)->getSyncScopeID();
|
2014-05-27 21:35:46 +00:00
|
|
|
if (const AtomicCmpXchgInst *CXI = dyn_cast<AtomicCmpXchgInst>(I1))
|
|
|
|
return CXI->isVolatile() == cast<AtomicCmpXchgInst>(I2)->isVolatile() &&
|
IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
llvm-svn: 210903
2014-06-13 14:24:07 +00:00
|
|
|
CXI->isWeak() == cast<AtomicCmpXchgInst>(I2)->isWeak() &&
|
2014-05-27 21:35:46 +00:00
|
|
|
CXI->getSuccessOrdering() ==
|
|
|
|
cast<AtomicCmpXchgInst>(I2)->getSuccessOrdering() &&
|
|
|
|
CXI->getFailureOrdering() ==
|
|
|
|
cast<AtomicCmpXchgInst>(I2)->getFailureOrdering() &&
|
2017-07-11 22:23:00 +00:00
|
|
|
CXI->getSyncScopeID() ==
|
|
|
|
cast<AtomicCmpXchgInst>(I2)->getSyncScopeID();
|
2014-05-27 21:35:46 +00:00
|
|
|
if (const AtomicRMWInst *RMWI = dyn_cast<AtomicRMWInst>(I1))
|
|
|
|
return RMWI->getOperation() == cast<AtomicRMWInst>(I2)->getOperation() &&
|
|
|
|
RMWI->isVolatile() == cast<AtomicRMWInst>(I2)->isVolatile() &&
|
|
|
|
RMWI->getOrdering() == cast<AtomicRMWInst>(I2)->getOrdering() &&
|
2017-07-11 22:23:00 +00:00
|
|
|
RMWI->getSyncScopeID() == cast<AtomicRMWInst>(I2)->getSyncScopeID();
|
2020-03-31 13:08:59 -07:00
|
|
|
if (const ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(I1))
|
|
|
|
return SVI->getShuffleMask() ==
|
|
|
|
cast<ShuffleVectorInst>(I2)->getShuffleMask();
|
2022-02-11 12:25:36 +01:00
|
|
|
if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I1))
|
|
|
|
return GEP->getSourceElementType() ==
|
|
|
|
cast<GetElementPtrInst>(I2)->getSourceElementType();
|
2014-05-27 21:35:46 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2008-11-27 08:39:18 +00:00
|
|
|
bool Instruction::isIdenticalTo(const Instruction *I) const {
|
2009-08-25 22:24:20 +00:00
|
|
|
return isIdenticalToWhenDefined(I) &&
|
2009-08-25 22:11:20 +00:00
|
|
|
SubclassOptionalData == I->SubclassOptionalData;
|
|
|
|
}
|
|
|
|
|
2024-09-20 15:02:59 -05:00
|
|
|
bool Instruction::isIdenticalToWhenDefined(const Instruction *I,
|
|
|
|
bool IntersectAttrs) const {
|
2004-11-30 02:51:53 +00:00
|
|
|
if (getOpcode() != I->getOpcode() ||
|
2024-09-20 15:02:59 -05:00
|
|
|
getNumOperands() != I->getNumOperands() || getType() != I->getType())
|
2004-11-30 02:51:53 +00:00
|
|
|
return false;
|
|
|
|
|
2014-06-02 01:35:34 +00:00
|
|
|
// If both instructions have no operands, they are identical.
|
|
|
|
if (getNumOperands() == 0 && I->getNumOperands() == 0)
|
2024-10-02 11:35:03 -05:00
|
|
|
return this->hasSameSpecialState(I, /*IgnoreAlignment=*/false,
|
|
|
|
IntersectAttrs);
|
2014-06-02 01:35:34 +00:00
|
|
|
|
[InstCombine] Take 2: Perform trivial PHI CSE
The original take was 6102310d814ad73eab60a88b21dd70874f7a056f,
which taught InstSimplify to do that, which seemed better at time,
since we got EarlyCSE support for free.
However, it was proven that we can not do that there,
the simplified-to PHI would not be reachable from the original PHI,
and that is not something InstSimplify is allowed to do,
as noted in the commit ed90f15efb40d26b5d3ead3bb8e9e284218e0186
that reverted it :
> It appears to cause compilation non-determinism and caused stage3 mismatches.
However InstCombine already does many different optimizations,
so it should be a safe place to do it here.
Note that we still can't just compare incoming values ranges,
because there is no guarantee that these PHI's we'd simplify to
were already re-visited and sorted.
However coming up with a test is problematic.
Effects on vanilla llvm test-suite + RawSpeed:
```
| statistic name | baseline | proposed | Δ | % | |%| |
|----------------------------------------------------|-----------|-----------|-------:|---------:|---------:|
| instcombine.NumPHICSEs | 0 | 22228 | 22228 | 0.00% | 0.00% |
| asm-printer.EmittedInsts | 7942329 | 7942456 | 127 | 0.00% | 0.00% |
| assembler.ObjectBytes | 254295632 | 254313792 | 18160 | 0.01% | 0.01% |
| early-cse.NumCSE | 2183283 | 2183272 | -11 | 0.00% | 0.00% |
| early-cse.NumSimplify | 550105 | 541842 | -8263 | -1.50% | 1.50% |
| instcombine.NumAggregateReconstructionsSimplified | 73 | 4506 | 4433 | 6072.60% | 6072.60% |
| instcombine.NumCombined | 3640311 | 3666911 | 26600 | 0.73% | 0.73% |
| instcombine.NumDeadInst | 1778204 | 1783318 | 5114 | 0.29% | 0.29% |
| instcount.NumCallInst | 1758395 | 1758804 | 409 | 0.02% | 0.02% |
| instcount.NumInvokeInst | 59478 | 59502 | 24 | 0.04% | 0.04% |
| instcount.NumPHIInst | 330557 | 330549 | -8 | 0.00% | 0.00% |
| instcount.TotalBlocks | 1077138 | 1077221 | 83 | 0.01% | 0.01% |
| instcount.TotalFuncs | 101442 | 101441 | -1 | 0.00% | 0.00% |
| instcount.TotalInsts | 8831946 | 8832611 | 665 | 0.01% | 0.01% |
| simplifycfg.NumInvokes | 4300 | 4410 | 110 | 2.56% | 2.56% |
| simplifycfg.NumSimpl | 1019813 | 999740 | -20073 | -1.97% | 1.97% |
```
So it fires ~22k times, which is less than ~24k the take 1 did.
It allows foldAggregateConstructionIntoAggregateReuse() to actually work
after PHI-of-extractvalue folds did their thing. Previously SimplifyCFG
would have done this PHI CSE, of all places. Additionally, allows some
more `invoke`->`call` folds to happen (+110, +2.56%).
All in all, expectedly, this catches less things overall,
but all the motivational cases are still caught, so all good.
2020-08-29 10:42:38 +03:00
|
|
|
// We have two instructions of identical opcode and #operands. Check to see
|
|
|
|
// if all operands are the same.
|
|
|
|
if (!std::equal(op_begin(), op_end(), I->op_begin()))
|
|
|
|
return false;
|
|
|
|
|
2020-08-29 19:38:33 +03:00
|
|
|
// WARNING: this logic must be kept in sync with EliminateDuplicatePHINodes()!
|
|
|
|
if (const PHINode *thisPHI = dyn_cast<PHINode>(this)) {
|
|
|
|
const PHINode *otherPHI = cast<PHINode>(I);
|
|
|
|
return std::equal(thisPHI->block_begin(), thisPHI->block_end(),
|
|
|
|
otherPHI->block_begin());
|
|
|
|
}
|
|
|
|
|
2024-09-20 15:02:59 -05:00
|
|
|
return this->hasSameSpecialState(I, /*IgnoreAlignment=*/false,
|
|
|
|
IntersectAttrs);
|
2006-12-23 06:05:41 +00:00
|
|
|
}
|
|
|
|
|
2016-04-11 22:30:37 +00:00
|
|
|
// Keep this in sync with FunctionComparator::cmpOperations in
|
2009-06-12 19:03:05 +00:00
|
|
|
// lib/Transforms/IPO/MergeFunctions.cpp.
|
2012-06-28 05:42:26 +00:00
|
|
|
bool Instruction::isSameOperationAs(const Instruction *I,
|
|
|
|
unsigned flags) const {
|
|
|
|
bool IgnoreAlignment = flags & CompareIgnoringAlignment;
|
2024-09-20 15:02:59 -05:00
|
|
|
bool UseScalarTypes = flags & CompareUsingScalarTypes;
|
|
|
|
bool IntersectAttrs = flags & CompareUsingIntersectedAttrs;
|
2012-06-28 05:42:26 +00:00
|
|
|
|
2009-06-12 19:03:05 +00:00
|
|
|
if (getOpcode() != I->getOpcode() ||
|
|
|
|
getNumOperands() != I->getNumOperands() ||
|
2012-06-28 05:42:26 +00:00
|
|
|
(UseScalarTypes ?
|
|
|
|
getType()->getScalarType() != I->getType()->getScalarType() :
|
|
|
|
getType() != I->getType()))
|
2006-12-23 06:05:41 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// We have two instructions of identical opcode and #operands. Check to see
|
|
|
|
// if all operands are the same type
|
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
|
2012-06-28 05:42:26 +00:00
|
|
|
if (UseScalarTypes ?
|
|
|
|
getOperand(i)->getType()->getScalarType() !=
|
|
|
|
I->getOperand(i)->getType()->getScalarType() :
|
|
|
|
getOperand(i)->getType() != I->getOperand(i)->getType())
|
2006-12-23 06:05:41 +00:00
|
|
|
return false;
|
|
|
|
|
2024-09-20 15:02:59 -05:00
|
|
|
return this->hasSameSpecialState(I, IgnoreAlignment, IntersectAttrs);
|
2004-11-30 02:51:53 +00:00
|
|
|
}
|
|
|
|
|
2008-04-20 22:11:30 +00:00
|
|
|
bool Instruction::isUsedOutsideOfBlock(const BasicBlock *BB) const {
|
2014-03-09 03:16:01 +00:00
|
|
|
for (const Use &U : uses()) {
|
2008-04-20 22:11:30 +00:00
|
|
|
// PHI nodes uses values in the corresponding predecessor block. For other
|
|
|
|
// instructions, just check to see whether the parent of the use matches up.
|
2014-03-09 03:16:01 +00:00
|
|
|
const Instruction *I = cast<Instruction>(U.getUser());
|
|
|
|
const PHINode *PN = dyn_cast<PHINode>(I);
|
2014-04-09 06:08:46 +00:00
|
|
|
if (!PN) {
|
2014-03-09 03:16:01 +00:00
|
|
|
if (I->getParent() != BB)
|
2008-04-20 22:11:30 +00:00
|
|
|
return true;
|
|
|
|
continue;
|
|
|
|
}
|
2009-09-20 02:20:51 +00:00
|
|
|
|
2014-03-09 03:16:01 +00:00
|
|
|
if (PN->getIncomingBlock(U) != BB)
|
2008-04-20 22:11:30 +00:00
|
|
|
return true;
|
|
|
|
}
|
2009-09-20 02:20:51 +00:00
|
|
|
return false;
|
2008-04-20 22:11:30 +00:00
|
|
|
}
|
|
|
|
|
2008-05-08 17:16:51 +00:00
|
|
|
bool Instruction::mayReadFromMemory() const {
|
|
|
|
switch (getOpcode()) {
|
|
|
|
default: return false;
|
|
|
|
case Instruction::VAArg:
|
2008-05-08 21:58:49 +00:00
|
|
|
case Instruction::Load:
|
2011-07-27 01:08:30 +00:00
|
|
|
case Instruction::Fence: // FIXME: refine definition of mayReadFromMemory
|
2011-07-29 03:05:32 +00:00
|
|
|
case Instruction::AtomicCmpXchg:
|
|
|
|
case Instruction::AtomicRMW:
|
2015-09-10 18:50:09 +00:00
|
|
|
case Instruction::CatchPad:
|
2015-07-31 17:58:14 +00:00
|
|
|
case Instruction::CatchRet:
|
2008-05-08 17:16:51 +00:00
|
|
|
return true;
|
|
|
|
case Instruction::Call:
|
|
|
|
case Instruction::Invoke:
|
2019-02-08 20:48:56 +00:00
|
|
|
case Instruction::CallBr:
|
2022-01-05 08:20:53 -08:00
|
|
|
return !cast<CallBase>(this)->onlyWritesMemory();
|
2008-05-08 21:58:49 +00:00
|
|
|
case Instruction::Store:
|
2011-08-15 21:00:18 +00:00
|
|
|
return !cast<StoreInst>(this)->isUnordered();
|
2008-05-08 17:16:51 +00:00
|
|
|
}
|
|
|
|
}
|
2008-04-20 22:11:30 +00:00
|
|
|
|
2007-02-15 23:15:00 +00:00
|
|
|
bool Instruction::mayWriteToMemory() const {
|
|
|
|
switch (getOpcode()) {
|
|
|
|
default: return false;
|
2011-07-27 01:08:30 +00:00
|
|
|
case Instruction::Fence: // FIXME: refine definition of mayWriteToMemory
|
2007-12-03 20:06:50 +00:00
|
|
|
case Instruction::Store:
|
2007-02-15 23:15:00 +00:00
|
|
|
case Instruction::VAArg:
|
2011-07-29 03:05:32 +00:00
|
|
|
case Instruction::AtomicCmpXchg:
|
|
|
|
case Instruction::AtomicRMW:
|
2015-09-10 18:50:09 +00:00
|
|
|
case Instruction::CatchPad:
|
2015-07-31 17:58:14 +00:00
|
|
|
case Instruction::CatchRet:
|
2007-02-15 23:15:00 +00:00
|
|
|
return true;
|
|
|
|
case Instruction::Call:
|
2008-05-08 17:16:51 +00:00
|
|
|
case Instruction::Invoke:
|
2021-01-25 13:30:12 -08:00
|
|
|
case Instruction::CallBr:
|
|
|
|
return !cast<CallBase>(this)->onlyReadsMemory();
|
2007-02-15 23:15:00 +00:00
|
|
|
case Instruction::Load:
|
2011-08-15 21:00:18 +00:00
|
|
|
return !cast<LoadInst>(this)->isUnordered();
|
2007-02-15 23:15:00 +00:00
|
|
|
}
|
|
|
|
}
|
2002-10-31 04:14:01 +00:00
|
|
|
|
2014-09-03 21:29:59 +00:00
|
|
|
bool Instruction::isAtomic() const {
|
|
|
|
switch (getOpcode()) {
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
case Instruction::AtomicCmpXchg:
|
|
|
|
case Instruction::AtomicRMW:
|
|
|
|
case Instruction::Fence:
|
|
|
|
return true;
|
|
|
|
case Instruction::Load:
|
2016-04-06 21:19:33 +00:00
|
|
|
return cast<LoadInst>(this)->getOrdering() != AtomicOrdering::NotAtomic;
|
2014-09-03 21:29:59 +00:00
|
|
|
case Instruction::Store:
|
2016-04-06 21:19:33 +00:00
|
|
|
return cast<StoreInst>(this)->getOrdering() != AtomicOrdering::NotAtomic;
|
2014-09-03 21:29:59 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-05-09 15:27:17 +00:00
|
|
|
bool Instruction::hasAtomicLoad() const {
|
|
|
|
assert(isAtomic());
|
|
|
|
switch (getOpcode()) {
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
case Instruction::AtomicCmpXchg:
|
|
|
|
case Instruction::AtomicRMW:
|
|
|
|
case Instruction::Load:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Instruction::hasAtomicStore() const {
|
|
|
|
assert(isAtomic());
|
|
|
|
switch (getOpcode()) {
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
case Instruction::AtomicCmpXchg:
|
|
|
|
case Instruction::AtomicRMW:
|
|
|
|
case Instruction::Store:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-01 11:21:34 -07:00
|
|
|
bool Instruction::isVolatile() const {
|
|
|
|
switch (getOpcode()) {
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
case Instruction::AtomicRMW:
|
|
|
|
return cast<AtomicRMWInst>(this)->isVolatile();
|
|
|
|
case Instruction::Store:
|
|
|
|
return cast<StoreInst>(this)->isVolatile();
|
|
|
|
case Instruction::Load:
|
|
|
|
return cast<LoadInst>(this)->isVolatile();
|
|
|
|
case Instruction::AtomicCmpXchg:
|
|
|
|
return cast<AtomicCmpXchgInst>(this)->isVolatile();
|
|
|
|
case Instruction::Call:
|
|
|
|
case Instruction::Invoke:
|
|
|
|
// There are a very limited number of intrinsics with volatile flags.
|
|
|
|
if (auto *II = dyn_cast<IntrinsicInst>(this)) {
|
|
|
|
if (auto *MI = dyn_cast<MemIntrinsic>(II))
|
|
|
|
return MI->isVolatile();
|
|
|
|
switch (II->getIntrinsicID()) {
|
|
|
|
default: break;
|
|
|
|
case Intrinsic::matrix_column_major_load:
|
|
|
|
return cast<ConstantInt>(II->getArgOperand(2))->isOne();
|
|
|
|
case Intrinsic::matrix_column_major_store:
|
|
|
|
return cast<ConstantInt>(II->getArgOperand(3))->isOne();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2023-05-15 16:56:48 +01:00
|
|
|
Type *Instruction::getAccessType() const {
|
|
|
|
switch (getOpcode()) {
|
|
|
|
case Instruction::Store:
|
|
|
|
return cast<StoreInst>(this)->getValueOperand()->getType();
|
|
|
|
case Instruction::Load:
|
|
|
|
case Instruction::AtomicRMW:
|
|
|
|
return getType();
|
|
|
|
case Instruction::AtomicCmpXchg:
|
|
|
|
return cast<AtomicCmpXchgInst>(this)->getNewValOperand()->getType();
|
|
|
|
case Instruction::Call:
|
|
|
|
case Instruction::Invoke:
|
|
|
|
if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(this)) {
|
|
|
|
switch (II->getIntrinsicID()) {
|
|
|
|
case Intrinsic::masked_load:
|
|
|
|
case Intrinsic::masked_gather:
|
|
|
|
case Intrinsic::masked_expandload:
|
|
|
|
case Intrinsic::vp_load:
|
|
|
|
case Intrinsic::vp_gather:
|
|
|
|
case Intrinsic::experimental_vp_strided_load:
|
|
|
|
return II->getType();
|
|
|
|
case Intrinsic::masked_store:
|
|
|
|
case Intrinsic::masked_scatter:
|
|
|
|
case Intrinsic::masked_compressstore:
|
|
|
|
case Intrinsic::vp_store:
|
|
|
|
case Intrinsic::vp_scatter:
|
|
|
|
case Intrinsic::experimental_vp_strided_store:
|
|
|
|
return II->getOperand(0)->getType();
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return nullptr;
|
|
|
|
}
|
|
|
|
|
2023-04-06 10:49:42 +02:00
|
|
|
static bool canUnwindPastLandingPad(const LandingPadInst *LP,
|
|
|
|
bool IncludePhaseOneUnwind) {
|
|
|
|
// Because phase one unwinding skips cleanup landingpads, we effectively
|
|
|
|
// unwind past this frame, and callers need to have valid unwind info.
|
|
|
|
if (LP->isCleanup())
|
|
|
|
return IncludePhaseOneUnwind;
|
|
|
|
|
|
|
|
for (unsigned I = 0; I < LP->getNumClauses(); ++I) {
|
|
|
|
Constant *Clause = LP->getClause(I);
|
|
|
|
// catch ptr null catches all exceptions.
|
|
|
|
if (LP->isCatch(I) && isa<ConstantPointerNull>(Clause))
|
|
|
|
return false;
|
|
|
|
// filter [0 x ptr] catches all exceptions.
|
|
|
|
if (LP->isFilter(I) && Clause->getType()->getArrayNumElements() == 0)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// May catch only some subset of exceptions, in which case other exceptions
|
|
|
|
// will continue unwinding.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool Instruction::mayThrow(bool IncludePhaseOneUnwind) const {
|
2023-04-12 09:48:01 +02:00
|
|
|
switch (getOpcode()) {
|
|
|
|
case Instruction::Call:
|
|
|
|
return !cast<CallInst>(this)->doesNotThrow();
|
|
|
|
case Instruction::CleanupRet:
|
|
|
|
return cast<CleanupReturnInst>(this)->unwindsToCaller();
|
|
|
|
case Instruction::CatchSwitch:
|
|
|
|
return cast<CatchSwitchInst>(this)->unwindsToCaller();
|
|
|
|
case Instruction::Resume:
|
|
|
|
return true;
|
2023-04-06 10:49:42 +02:00
|
|
|
case Instruction::Invoke: {
|
|
|
|
// Landingpads themselves don't unwind -- however, an invoke of a skipped
|
|
|
|
// landingpad may continue unwinding.
|
|
|
|
BasicBlock *UnwindDest = cast<InvokeInst>(this)->getUnwindDest();
|
2025-01-24 09:06:01 +00:00
|
|
|
BasicBlock::iterator Pad = UnwindDest->getFirstNonPHIIt();
|
2023-04-06 10:49:42 +02:00
|
|
|
if (auto *LP = dyn_cast<LandingPadInst>(Pad))
|
|
|
|
return canUnwindPastLandingPad(LP, IncludePhaseOneUnwind);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
case Instruction::CleanupPad:
|
|
|
|
// Treat the same as cleanup landingpad.
|
|
|
|
return IncludePhaseOneUnwind;
|
2023-04-12 09:48:01 +02:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
2009-05-06 06:49:50 +00:00
|
|
|
}
|
|
|
|
|
2021-07-21 21:23:38 +02:00
|
|
|
bool Instruction::mayHaveSideEffects() const {
|
|
|
|
return mayWriteToMemory() || mayThrow() || !willReturn();
|
|
|
|
}
|
|
|
|
|
2018-01-09 21:58:46 +00:00
|
|
|
bool Instruction::isSafeToRemove() const {
|
|
|
|
return (!isa<CallInst>(this) || !this->mayHaveSideEffects()) &&
|
2022-03-14 14:34:01 +01:00
|
|
|
!this->isTerminator() && !this->isEHPad();
|
2018-01-09 21:58:46 +00:00
|
|
|
}
|
|
|
|
|
2021-02-18 22:15:17 +01:00
|
|
|
bool Instruction::willReturn() const {
|
2021-07-26 10:51:00 -07:00
|
|
|
// Volatile store isn't guaranteed to return; see LangRef.
|
|
|
|
if (auto *SI = dyn_cast<StoreInst>(this))
|
|
|
|
return !SI->isVolatile();
|
|
|
|
|
2021-02-18 22:15:17 +01:00
|
|
|
if (const auto *CB = dyn_cast<CallBase>(this))
|
2022-10-26 11:55:46 +02:00
|
|
|
return CB->hasFnAttr(Attribute::WillReturn);
|
2021-02-18 22:15:17 +01:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-12-21 21:49:40 +00:00
|
|
|
bool Instruction::isLifetimeStartOrEnd() const {
|
2021-03-29 17:02:41 -07:00
|
|
|
auto *II = dyn_cast<IntrinsicInst>(this);
|
2018-12-21 21:49:40 +00:00
|
|
|
if (!II)
|
|
|
|
return false;
|
|
|
|
Intrinsic::ID ID = II->getIntrinsicID();
|
|
|
|
return ID == Intrinsic::lifetime_start || ID == Intrinsic::lifetime_end;
|
|
|
|
}
|
|
|
|
|
2021-03-29 17:02:41 -07:00
|
|
|
bool Instruction::isLaunderOrStripInvariantGroup() const {
|
|
|
|
auto *II = dyn_cast<IntrinsicInst>(this);
|
|
|
|
if (!II)
|
|
|
|
return false;
|
|
|
|
Intrinsic::ID ID = II->getIntrinsicID();
|
|
|
|
return ID == Intrinsic::launder_invariant_group ||
|
|
|
|
ID == Intrinsic::strip_invariant_group;
|
|
|
|
}
|
|
|
|
|
2021-02-07 22:49:20 -08:00
|
|
|
bool Instruction::isDebugOrPseudoInst() const {
|
|
|
|
return isa<DbgInfoIntrinsic>(this) || isa<PseudoProbeInst>(this);
|
|
|
|
}
|
|
|
|
|
[CSSPGO] IR intrinsic for pseudo-probe block instrumentation
This change introduces a new IR intrinsic named `llvm.pseudoprobe` for pseudo-probe block instrumentation. Please refer to https://reviews.llvm.org/D86193 for the whole story.
A pseudo probe is used to collect the execution count of the block where the probe is instrumented. This requires a pseudo probe to be persisting. The LLVM PGO instrumentation also instruments in similar places by placing a counter in the form of atomic read/write operations or runtime helper calls. While these operations are very persisting or optimization-resilient, in theory we can borrow the atomic read/write implementation from PGO counters and cut it off at the end of compilation with all the atomics converted into binary data. This was our initial design and we’ve seen promising sample correlation quality with it. However, the atomics approach has a couple issues:
1. IR Optimizations are blocked unexpectedly. Those atomic instructions are not going to be physically present in the binary code, but since they are on the IR till very end of compilation, they can still prevent certain IR optimizations and result in lower code quality.
2. The counter atomics may not be fully cleaned up from the code stream eventually.
3. Extra work is needed for re-targeting.
We choose to implement pseudo probes based on a special LLVM intrinsic, which is expected to have most of the semantics that comes with an atomic operation but does not block desired optimizations as much as possible. More specifically the semantics associated with the new intrinsic enforces a pseudo probe to be virtually executed exactly the same number of times before and after an IR optimization. The intrinsic also comes with certain flags that are carefully chosen so that the places they are probing are not going to be messed up by the optimizer while most of the IR optimizations still work. The core flags given to the special intrinsic is `IntrInaccessibleMemOnly`, which means the intrinsic accesses memory and does have a side effect so that it is not removable, but is does not access memory locations that are accessible by any original instructions. This way the intrinsic does not alias with any original instruction and thus it does not block optimizations as much as an atomic operation does. We also assign a function GUID and a block index to an intrinsic so that they are uniquely identified and not merged in order to achieve good correlation quality.
Let's now look at an example. Given the following LLVM IR:
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
br i1 %cmp, label %bb1, label %bb2
bb1:
br label %bb3
bb2:
br label %bb3
bb3:
ret void
}
```
The instrumented IR will look like below. Note that each `llvm.pseudoprobe` intrinsic call represents a pseudo probe at a block, of which the first parameter is the GUID of the probe’s owner function and the second parameter is the probe’s ID.
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
call void @llvm.pseudoprobe(i64 837061429793323041, i64 1)
br i1 %cmp, label %bb1, label %bb2
bb1:
call void @llvm.pseudoprobe(i64 837061429793323041, i64 2)
br label %bb3
bb2:
call void @llvm.pseudoprobe(i64 837061429793323041, i64 3)
br label %bb3
bb3:
call void @llvm.pseudoprobe(i64 837061429793323041, i64 4)
ret void
}
```
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D86490
2020-11-18 12:42:51 -08:00
|
|
|
const Instruction *
|
|
|
|
Instruction::getNextNonDebugInstruction(bool SkipPseudoOp) const {
|
2018-06-19 23:42:17 +00:00
|
|
|
for (const Instruction *I = getNextNode(); I; I = I->getNextNode())
|
[CSSPGO] IR intrinsic for pseudo-probe block instrumentation
This change introduces a new IR intrinsic named `llvm.pseudoprobe` for pseudo-probe block instrumentation. Please refer to https://reviews.llvm.org/D86193 for the whole story.
A pseudo probe is used to collect the execution count of the block where the probe is instrumented. This requires a pseudo probe to be persisting. The LLVM PGO instrumentation also instruments in similar places by placing a counter in the form of atomic read/write operations or runtime helper calls. While these operations are very persisting or optimization-resilient, in theory we can borrow the atomic read/write implementation from PGO counters and cut it off at the end of compilation with all the atomics converted into binary data. This was our initial design and we’ve seen promising sample correlation quality with it. However, the atomics approach has a couple issues:
1. IR Optimizations are blocked unexpectedly. Those atomic instructions are not going to be physically present in the binary code, but since they are on the IR till very end of compilation, they can still prevent certain IR optimizations and result in lower code quality.
2. The counter atomics may not be fully cleaned up from the code stream eventually.
3. Extra work is needed for re-targeting.
We choose to implement pseudo probes based on a special LLVM intrinsic, which is expected to have most of the semantics that comes with an atomic operation but does not block desired optimizations as much as possible. More specifically the semantics associated with the new intrinsic enforces a pseudo probe to be virtually executed exactly the same number of times before and after an IR optimization. The intrinsic also comes with certain flags that are carefully chosen so that the places they are probing are not going to be messed up by the optimizer while most of the IR optimizations still work. The core flags given to the special intrinsic is `IntrInaccessibleMemOnly`, which means the intrinsic accesses memory and does have a side effect so that it is not removable, but is does not access memory locations that are accessible by any original instructions. This way the intrinsic does not alias with any original instruction and thus it does not block optimizations as much as an atomic operation does. We also assign a function GUID and a block index to an intrinsic so that they are uniquely identified and not merged in order to achieve good correlation quality.
Let's now look at an example. Given the following LLVM IR:
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
br i1 %cmp, label %bb1, label %bb2
bb1:
br label %bb3
bb2:
br label %bb3
bb3:
ret void
}
```
The instrumented IR will look like below. Note that each `llvm.pseudoprobe` intrinsic call represents a pseudo probe at a block, of which the first parameter is the GUID of the probe’s owner function and the second parameter is the probe’s ID.
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
call void @llvm.pseudoprobe(i64 837061429793323041, i64 1)
br i1 %cmp, label %bb1, label %bb2
bb1:
call void @llvm.pseudoprobe(i64 837061429793323041, i64 2)
br label %bb3
bb2:
call void @llvm.pseudoprobe(i64 837061429793323041, i64 3)
br label %bb3
bb3:
call void @llvm.pseudoprobe(i64 837061429793323041, i64 4)
ret void
}
```
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D86490
2020-11-18 12:42:51 -08:00
|
|
|
if (!isa<DbgInfoIntrinsic>(I) && !(SkipPseudoOp && isa<PseudoProbeInst>(I)))
|
2018-06-19 23:42:17 +00:00
|
|
|
return I;
|
|
|
|
return nullptr;
|
|
|
|
}
|
|
|
|
|
[CSSPGO] IR intrinsic for pseudo-probe block instrumentation
This change introduces a new IR intrinsic named `llvm.pseudoprobe` for pseudo-probe block instrumentation. Please refer to https://reviews.llvm.org/D86193 for the whole story.
A pseudo probe is used to collect the execution count of the block where the probe is instrumented. This requires a pseudo probe to be persisting. The LLVM PGO instrumentation also instruments in similar places by placing a counter in the form of atomic read/write operations or runtime helper calls. While these operations are very persisting or optimization-resilient, in theory we can borrow the atomic read/write implementation from PGO counters and cut it off at the end of compilation with all the atomics converted into binary data. This was our initial design and we’ve seen promising sample correlation quality with it. However, the atomics approach has a couple issues:
1. IR Optimizations are blocked unexpectedly. Those atomic instructions are not going to be physically present in the binary code, but since they are on the IR till very end of compilation, they can still prevent certain IR optimizations and result in lower code quality.
2. The counter atomics may not be fully cleaned up from the code stream eventually.
3. Extra work is needed for re-targeting.
We choose to implement pseudo probes based on a special LLVM intrinsic, which is expected to have most of the semantics that comes with an atomic operation but does not block desired optimizations as much as possible. More specifically the semantics associated with the new intrinsic enforces a pseudo probe to be virtually executed exactly the same number of times before and after an IR optimization. The intrinsic also comes with certain flags that are carefully chosen so that the places they are probing are not going to be messed up by the optimizer while most of the IR optimizations still work. The core flags given to the special intrinsic is `IntrInaccessibleMemOnly`, which means the intrinsic accesses memory and does have a side effect so that it is not removable, but is does not access memory locations that are accessible by any original instructions. This way the intrinsic does not alias with any original instruction and thus it does not block optimizations as much as an atomic operation does. We also assign a function GUID and a block index to an intrinsic so that they are uniquely identified and not merged in order to achieve good correlation quality.
Let's now look at an example. Given the following LLVM IR:
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
br i1 %cmp, label %bb1, label %bb2
bb1:
br label %bb3
bb2:
br label %bb3
bb3:
ret void
}
```
The instrumented IR will look like below. Note that each `llvm.pseudoprobe` intrinsic call represents a pseudo probe at a block, of which the first parameter is the GUID of the probe’s owner function and the second parameter is the probe’s ID.
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
call void @llvm.pseudoprobe(i64 837061429793323041, i64 1)
br i1 %cmp, label %bb1, label %bb2
bb1:
call void @llvm.pseudoprobe(i64 837061429793323041, i64 2)
br label %bb3
bb2:
call void @llvm.pseudoprobe(i64 837061429793323041, i64 3)
br label %bb3
bb3:
call void @llvm.pseudoprobe(i64 837061429793323041, i64 4)
ret void
}
```
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D86490
2020-11-18 12:42:51 -08:00
|
|
|
const Instruction *
|
|
|
|
Instruction::getPrevNonDebugInstruction(bool SkipPseudoOp) const {
|
2018-11-09 09:42:10 +00:00
|
|
|
for (const Instruction *I = getPrevNode(); I; I = I->getPrevNode())
|
2025-02-25 14:49:59 +00:00
|
|
|
if (!isa<DbgInfoIntrinsic>(I) && !(SkipPseudoOp && isa<PseudoProbeInst>(I)))
|
2018-11-09 09:42:10 +00:00
|
|
|
return I;
|
|
|
|
return nullptr;
|
|
|
|
}
|
|
|
|
|
2023-09-11 18:19:52 +01:00
|
|
|
const DebugLoc &Instruction::getStableDebugLoc() const {
|
|
|
|
if (isa<DbgInfoIntrinsic>(this))
|
2023-09-15 12:52:07 -04:00
|
|
|
if (const Instruction *Next = getNextNonDebugInstruction())
|
|
|
|
return Next->getDebugLoc();
|
2023-09-11 18:19:52 +01:00
|
|
|
return getDebugLoc();
|
|
|
|
}
|
|
|
|
|
2012-11-29 01:47:31 +00:00
|
|
|
bool Instruction::isAssociative() const {
|
2023-12-04 22:35:59 -08:00
|
|
|
if (auto *II = dyn_cast<IntrinsicInst>(this))
|
|
|
|
return II->isAssociative();
|
2012-11-29 01:47:31 +00:00
|
|
|
unsigned Opcode = getOpcode();
|
|
|
|
if (isAssociative(Opcode))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
switch (Opcode) {
|
|
|
|
case FMul:
|
|
|
|
case FAdd:
|
2018-05-24 20:16:43 +00:00
|
|
|
return cast<FPMathOperator>(this)->hasAllowReassoc() &&
|
|
|
|
cast<FPMathOperator>(this)->hasNoSignedZeros();
|
2012-11-29 01:47:31 +00:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-08-31 15:53:01 -04:00
|
|
|
bool Instruction::isCommutative() const {
|
|
|
|
if (auto *II = dyn_cast<IntrinsicInst>(this))
|
|
|
|
return II->isCommutative();
|
|
|
|
// TODO: Should allow icmp/fcmp?
|
|
|
|
return isCommutative(getOpcode());
|
|
|
|
}
|
|
|
|
|
2018-08-26 08:41:15 +00:00
|
|
|
unsigned Instruction::getNumSuccessors() const {
|
|
|
|
switch (getOpcode()) {
|
|
|
|
#define HANDLE_TERM_INST(N, OPC, CLASS) \
|
|
|
|
case Instruction::OPC: \
|
|
|
|
return static_cast<const CLASS *>(this)->getNumSuccessors();
|
|
|
|
#include "llvm/IR/Instruction.def"
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
llvm_unreachable("not a terminator");
|
|
|
|
}
|
|
|
|
|
|
|
|
BasicBlock *Instruction::getSuccessor(unsigned idx) const {
|
|
|
|
switch (getOpcode()) {
|
|
|
|
#define HANDLE_TERM_INST(N, OPC, CLASS) \
|
|
|
|
case Instruction::OPC: \
|
|
|
|
return static_cast<const CLASS *>(this)->getSuccessor(idx);
|
|
|
|
#include "llvm/IR/Instruction.def"
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
llvm_unreachable("not a terminator");
|
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::setSuccessor(unsigned idx, BasicBlock *B) {
|
|
|
|
switch (getOpcode()) {
|
|
|
|
#define HANDLE_TERM_INST(N, OPC, CLASS) \
|
|
|
|
case Instruction::OPC: \
|
|
|
|
return static_cast<CLASS *>(this)->setSuccessor(idx, B);
|
|
|
|
#include "llvm/IR/Instruction.def"
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
llvm_unreachable("not a terminator");
|
|
|
|
}
|
|
|
|
|
2019-05-05 18:59:22 +00:00
|
|
|
void Instruction::replaceSuccessorWith(BasicBlock *OldBB, BasicBlock *NewBB) {
|
|
|
|
for (unsigned Idx = 0, NumSuccessors = Instruction::getNumSuccessors();
|
|
|
|
Idx != NumSuccessors; ++Idx)
|
|
|
|
if (getSuccessor(Idx) == OldBB)
|
|
|
|
setSuccessor(Idx, NewBB);
|
|
|
|
}
|
|
|
|
|
2015-06-24 20:22:23 +00:00
|
|
|
Instruction *Instruction::cloneImpl() const {
|
|
|
|
llvm_unreachable("Subclass of Instruction failed to implement cloneImpl");
|
|
|
|
}
|
|
|
|
|
2016-08-23 15:39:03 +00:00
|
|
|
void Instruction::swapProfMetadata() {
|
2023-01-19 12:04:53 +01:00
|
|
|
MDNode *ProfileData = getBranchWeightMDNode(*this);
|
Reapply "[llvm][IR] Extend BranchWeightMetadata to track provenance o… (#95281)
…f weights" #95136
Reverts #95060, and relands #86609, with the unintended code generation
changes addressed.
This patch implements the changes to LLVM IR discussed in
https://discourse.llvm.org/t/rfc-update-branch-weights-metadata-to-allow-tracking-branch-weight-origins/75032
In this patch, we add an optional field to MD_prof meatdata nodes for
branch weights, which can be used to distinguish weights added from
llvm.expect* intrinsics from those added via other methods, e.g. from
profiles or inserted by the compiler.
One of the major motivations, is for use with MisExpect diagnostics,
which need to know if branch_weight metadata originates from an
llvm.expect intrinsic. Without that information, we end up checking
branch weights multiple times in the case if ThinLTO + SampleProfiling,
leading to some inaccuracy in how we report MisExpect related
diagnostics to users.
Since we change the format of MD_prof metadata in a fundamental way, we
need to update code handling branch weights in a number of places.
We also update the lang ref for branch weights to reflect the change.
2024-06-12 12:52:28 -07:00
|
|
|
if (!ProfileData)
|
|
|
|
return;
|
|
|
|
unsigned FirstIdx = getBranchWeightOffset(ProfileData);
|
|
|
|
if (ProfileData->getNumOperands() != 2 + FirstIdx)
|
2016-08-23 15:39:03 +00:00
|
|
|
return;
|
|
|
|
|
Reapply "[llvm][IR] Extend BranchWeightMetadata to track provenance o… (#95281)
…f weights" #95136
Reverts #95060, and relands #86609, with the unintended code generation
changes addressed.
This patch implements the changes to LLVM IR discussed in
https://discourse.llvm.org/t/rfc-update-branch-weights-metadata-to-allow-tracking-branch-weight-origins/75032
In this patch, we add an optional field to MD_prof meatdata nodes for
branch weights, which can be used to distinguish weights added from
llvm.expect* intrinsics from those added via other methods, e.g. from
profiles or inserted by the compiler.
One of the major motivations, is for use with MisExpect diagnostics,
which need to know if branch_weight metadata originates from an
llvm.expect intrinsic. Without that information, we end up checking
branch weights multiple times in the case if ThinLTO + SampleProfiling,
leading to some inaccuracy in how we report MisExpect related
diagnostics to users.
Since we change the format of MD_prof metadata in a fundamental way, we
need to update code handling branch weights in a number of places.
We also update the lang ref for branch weights to reflect the change.
2024-06-12 12:52:28 -07:00
|
|
|
unsigned SecondIdx = FirstIdx + 1;
|
|
|
|
SmallVector<Metadata *, 4> Ops;
|
|
|
|
// If there are more weights past the second, we can't swap them
|
|
|
|
if (ProfileData->getNumOperands() > SecondIdx + 1)
|
|
|
|
return;
|
|
|
|
for (unsigned Idx = 0; Idx < FirstIdx; ++Idx) {
|
|
|
|
Ops.push_back(ProfileData->getOperand(Idx));
|
|
|
|
}
|
|
|
|
// Switch the order of the weights
|
|
|
|
Ops.push_back(ProfileData->getOperand(SecondIdx));
|
|
|
|
Ops.push_back(ProfileData->getOperand(FirstIdx));
|
2016-08-23 15:39:03 +00:00
|
|
|
setMetadata(LLVMContext::MD_prof,
|
|
|
|
MDNode::get(ProfileData->getContext(), Ops));
|
|
|
|
}
|
|
|
|
|
|
|
|
void Instruction::copyMetadata(const Instruction &SrcInst,
|
|
|
|
ArrayRef<unsigned> WL) {
|
|
|
|
if (!SrcInst.hasMetadata())
|
|
|
|
return;
|
|
|
|
|
2024-01-26 17:18:42 -08:00
|
|
|
SmallDenseSet<unsigned, 4> WLS(WL.begin(), WL.end());
|
2016-08-23 15:39:03 +00:00
|
|
|
|
|
|
|
// Otherwise, enumerate and copy over metadata from the old instruction to the
|
|
|
|
// new one.
|
|
|
|
SmallVector<std::pair<unsigned, MDNode *>, 4> TheMDs;
|
|
|
|
SrcInst.getAllMetadataOtherThanDebugLoc(TheMDs);
|
|
|
|
for (const auto &MD : TheMDs) {
|
|
|
|
if (WL.empty() || WLS.count(MD.first))
|
|
|
|
setMetadata(MD.first, MD.second);
|
|
|
|
}
|
|
|
|
if (WL.empty() || WLS.count(LLVMContext::MD_dbg))
|
|
|
|
setDebugLoc(SrcInst.getDebugLoc());
|
|
|
|
}
|
|
|
|
|
2009-10-27 22:16:29 +00:00
|
|
|
Instruction *Instruction::clone() const {
|
2015-06-24 20:22:23 +00:00
|
|
|
Instruction *New = nullptr;
|
|
|
|
switch (getOpcode()) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unhandled Opcode.");
|
|
|
|
#define HANDLE_INST(num, opc, clas) \
|
|
|
|
case Instruction::opc: \
|
|
|
|
New = cast<clas>(this)->cloneImpl(); \
|
|
|
|
break;
|
|
|
|
#include "llvm/IR/Instruction.def"
|
|
|
|
#undef HANDLE_INST
|
|
|
|
}
|
|
|
|
|
2009-10-27 22:16:29 +00:00
|
|
|
New->SubclassOptionalData = SubclassOptionalData;
|
2016-08-23 15:39:03 +00:00
|
|
|
New->copyMetadata(*this);
|
2009-10-27 22:16:29 +00:00
|
|
|
return New;
|
|
|
|
}
|