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llvm-project/clang/test/CodeGenCUDA/builtins-unsafe-atomics-gfx90a.cu

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[Clang] Update some CUDA tests to opaque pointers (NFC)
2022-12-13 11:48:14 +01:00
// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx90a -x hip \
[HIP] Relax conditions for address space cast in builtin args Allow (implicit) address space casting between LLVM-equivalent target address spaces. Reviewed By: yaxunl, tra Differential Revision: https://reviews.llvm.org/D111734
2021-10-15 15:16:32 -06:00
// RUN: -aux-triple x86_64-unknown-linux-gnu -fcuda-is-device -emit-llvm %s \
// RUN: -o - | FileCheck %s
#define __device__ __attribute__((device))
typedef __attribute__((address_space(3))) float *LP;
// CHECK-LABEL: test_ds_atomic_add_f32
[Clang] Update some CUDA tests to opaque pointers (NFC)
2022-12-13 11:48:14 +01:00
// CHECK: %[[ADDR_ADDR:.*]] = alloca ptr, align 8, addrspace(5)
// CHECK: %[[ADDR_ADDR_ASCAST_PTR:.*]] = addrspacecast ptr addrspace(5) %[[ADDR_ADDR]] to ptr
// CHECK: store ptr %addr, ptr %[[ADDR_ADDR_ASCAST_PTR]], align 8
// CHECK: %[[ADDR_ADDR_ASCAST:.*]] = load ptr, ptr %[[ADDR_ADDR_ASCAST_PTR]], align 8
// CHECK: %[[AS_CAST:.*]] = addrspacecast ptr %[[ADDR_ADDR_ASCAST]] to ptr addrspace(3)
clang/AMDGPU: Emit atomicrmw from ds_fadd builtins (#95395) We should have done this for the f32/f64 case a long time ago. Now that codegen handles atomicrmw selection for the v2f16/v2bf16 case, start emitting it instead. This also does upgrade the behavior to respect a volatile qualified pointer, which was previously ignored (for the cases that don't have an explicit volatile argument).
2024-06-18 20:51:14 +02:00
// CHECK: [[TMP2:%.+]] = load float, ptr %val.addr.ascast, align 4
// CHECK: [[TMP3:%.+]] = atomicrmw fadd ptr addrspace(3) %[[AS_CAST]], float [[TMP2]] monotonic, align 4
[Clang] Update some CUDA tests to opaque pointers (NFC)
2022-12-13 11:48:14 +01:00
// CHECK: %4 = load ptr, ptr %rtn.ascast, align 8
clang/AMDGPU: Emit atomicrmw from ds_fadd builtins (#95395) We should have done this for the f32/f64 case a long time ago. Now that codegen handles atomicrmw selection for the v2f16/v2bf16 case, start emitting it instead. This also does upgrade the behavior to respect a volatile qualified pointer, which was previously ignored (for the cases that don't have an explicit volatile argument).
2024-06-18 20:51:14 +02:00
// CHECK: store float [[TMP3]], ptr %4, align 4
[HIP] Relax conditions for address space cast in builtin args Allow (implicit) address space casting between LLVM-equivalent target address spaces. Reviewed By: yaxunl, tra Differential Revision: https://reviews.llvm.org/D111734
2021-10-15 15:16:32 -06:00
__device__ void test_ds_atomic_add_f32(float *addr, float val) {
float *rtn;
*rtn = __builtin_amdgcn_ds_faddf((LP)addr, val, 0, 0, 0);
}
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