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llvm-project/clang/test/Frontend/x86-target-cpu.c

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Re-work the Clang system for classifying Intel x86 CPUs to use their basic microarchitecture names, and add support (with tests) for parsing all of the masic microarchitecture names for CPUs documented to be accepted by GCC with -march. I didn't go back through the 32-bit-only old microarchitectures, but this at least brings the recent architecture names up to speed. This is essentially the follow-up to the LLVM commit r223769 which did similar cleanups for the LLVM CPUs. One particular benefit is that you can now use -march=westmere in Clang and get the LLVM westmere processor which is a different ISA variant (!) and so quite significant. Much like with r223769, I would appreciate the Intel folks carefully thinking about the macros defined, names used, etc for the atom chips and newest primary x86 chips. The current patterns seem quite strange to me, especially here in Clang. Note that I haven't replicated the per-microarchitecture macro defines provided by GCC. I'm really opposed to source code using these rather than using ISA feature macros. llvm-svn: 223776
2014-12-09 14:50:25 +00:00
// Ensure we support the various CPU names.
//
Don't actually generate code for testing the frontend's target cpu flag, just verify. This should fix the bots where the x86 backend isn't built into Clang. Sorry for the breakage. llvm-svn: 223779
2014-12-09 15:52:55 +00:00
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu nocona -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu core2 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu penryn -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu nehalem -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu westmere -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu sandybridge -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu ivybridge -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu haswell -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu broadwell -verify %s
[X86] Add recent CPU strings to some of the tests that check other cpu names. llvm-svn: 291545
2017-01-10 06:02:16 +00:00
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu skylake -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu skylake-avx512 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu skx -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu cannonlake -verify %s
[X86] Split up -march=icelake to -client & -server Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45056 llvm-svn: 329741
2018-04-10 18:58:26 +00:00
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu icelake-client -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu icelake-server -verify %s
Reland "[X86] Remove knl/knm specific ISAs supports (#92883)" (#93136) This reverts commit aa4069ea96e5eb62bc8c7895b9d920f129611b3a.
2024-05-24 13:46:34 +08:00
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu knl -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu knm -verify %s
Don't actually generate code for testing the frontend's target cpu flag, just verify. This should fix the bots where the x86 backend isn't built into Clang. Sorry for the breakage. llvm-svn: 223779
2014-12-09 15:52:55 +00:00
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu bonnell -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu silvermont -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu k8 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu opteron -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu athlon64 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu athlon-fx -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu k8-sse3 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu opteron-sse3 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu athlon64-sse3 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu amdfam10 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu barcelona -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu bdver1 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu bdver2 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu bdver3 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu bdver4 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu btver1 -verify %s
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu btver2 -verify %s
AMD family 17h (znver1) enablement Summary: This patch enables the following 1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu). 2. ISAs that are enabled for "znver1" architecture. 3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used. 4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17. 5. For the time being, it uses the btver2 scheduler model. 6. Test file is updated to check this flag. This is linked to llvm review item https://reviews.llvm.org/D28017 Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper. Reviewers: RKSimon, craig.topper Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits Differential Revision: https://reviews.llvm.org/D28018 llvm-svn: 291544
2017-01-10 06:02:12 +00:00
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver1 -verify %s
[X86] AMD znver2 enablement This patch enables the following 1) AMD family 17h "znver2" tune flag (-march, -mcpu). 2) ISAs that are enabled for "znver2" architecture. 3) For the time being, it uses the znver1 scheduler model. 4) Tests are updated. 5) This patch is the clang counterpart to D58343 Reviewers: craig.topper Tags: #clang Differential Revision: https://reviews.llvm.org/D58344 llvm-svn: 354899
2019-02-26 17:15:36 +00:00
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver2 -verify %s
[X86] Update tests for znver3 Differential Revision: https://reviews.llvm.org/D92812
2021-01-07 00:59:38 +05:30
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver3 -verify %s
[X86] AMD Zen 4 Initial enablement Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D139073
2022-12-15 19:28:34 +05:30
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver4 -verify %s
[X86] AMD Zen 5 Initial enablement (#107964) This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.
2024-09-13 22:15:33 +05:30
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver5 -verify %s
Don't actually generate code for testing the frontend's target cpu flag, just verify. This should fix the bots where the x86 backend isn't built into Clang. Sorry for the breakage. llvm-svn: 223779
2014-12-09 15:52:55 +00:00
//
// expected-no-diagnostics
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