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llvm-project/llvm/docs/AMDGPU/gfx908_fx_operand.rst

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[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
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[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 17:16:22 +03:00
.. _amdgpu_synid_gfx908_fx_operand:
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 17:16:22 +03:00
FX Operand
==========
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
[AMDGPU][GFX908][DOC][NFC] Update assembler syntax description Summary of changes: - Enable VOP3 variants of dot2c/dot4c/dot8c instructions (https://reviews.llvm.org/D138494). - Enable abs and neg modifiers for v_dot2c_f32_f16_dpp. - Minor corrections and improvements.
2022-12-13 14:12:09 +03:00
This is a *f32* or *f16* operand depending on instruction modifiers:
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347
2019-07-08 16:50:11 +00:00
* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
[AMDGPU][GFX908][DOC][NFC] Update assembler syntax description Summary of changes: - Enable VOP3 variants of dot2c/dot4c/dot8c instructions (https://reviews.llvm.org/D138494). - Enable abs and neg modifiers for v_dot2c_f32_f16_dpp. - Minor corrections and improvements.
2022-12-13 14:12:09 +03:00
* Location of the 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
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