2018-07-06 10:46:19 -07:00
|
|
|
//===- Verifier.cpp - MLIR Verifier Implementation ------------------------===//
|
|
|
|
//
|
2020-01-26 03:58:30 +00:00
|
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
2019-12-23 09:35:36 -08:00
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2018-07-06 10:46:19 -07:00
|
|
|
//
|
2019-12-23 09:35:36 -08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2018-07-06 10:46:19 -07:00
|
|
|
//
|
|
|
|
// This file implements the verify() methods on the various IR types, performing
|
|
|
|
// (potentially expensive) checks on the holistic structure of the code. This
|
|
|
|
// can be used for detecting bugs in compiler transformations and hand written
|
|
|
|
// .mlir files.
|
|
|
|
//
|
|
|
|
// The checks in this file are only for things that can occur as part of IR
|
|
|
|
// transformations: e.g. violation of dominance information, malformed operation
|
|
|
|
// attributes, etc. MLIR supports transformations moving IR through locally
|
2019-03-27 08:55:17 -07:00
|
|
|
// invalid states (e.g. unlinking an operation from a block before re-inserting
|
|
|
|
// it in a new place), but each transformation must complete with the IR in a
|
|
|
|
// valid form.
|
2018-07-06 10:46:19 -07:00
|
|
|
//
|
|
|
|
// This should not check for things that are always wrong by construction (e.g.
|
2019-06-07 09:46:13 -07:00
|
|
|
// attributes or other immutable structures that are incorrect), because those
|
2018-07-06 10:46:19 -07:00
|
|
|
// are not mutable and can be checked at time of construction.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2020-04-30 13:09:13 -07:00
|
|
|
#include "mlir/IR/Verifier.h"
|
2018-08-21 08:42:19 -07:00
|
|
|
#include "mlir/IR/Attributes.h"
|
2019-03-02 22:34:18 -08:00
|
|
|
#include "mlir/IR/Dialect.h"
|
2020-04-30 13:09:13 -07:00
|
|
|
#include "mlir/IR/Dominance.h"
|
2019-03-26 14:45:38 -07:00
|
|
|
#include "mlir/IR/Operation.h"
|
[MLIR] Add RegionKindInterface
Some dialects have semantics which is not well represented by common
SSA structures with dominance constraints. This patch allows
operations to declare the 'kind' of their contained regions.
Currently, two kinds are allowed: "SSACFG" and "Graph". The only
difference between them at the moment is that SSACFG regions are
required to have dominance, while Graph regions are not required to
have dominance. The intention is that this Interface would be
generated by ODS for existing operations, although this has not yet
been implemented. Presumably, if someone were interested in code
generation, we might also have a "CFG" dialect, which defines control
flow, but does not require SSA.
The new behavior is mostly identical to the previous behavior, since
registered operations without a RegionKindInterface are assumed to
contain SSACFG regions. However, the behavior has changed for
unregistered operations. Previously, these were checked for
dominance, however the new behavior allows dominance violations, in
order to allow the processing of unregistered dialects with Graph
regions. One implication of this is that regions in unregistered
operations with more than one op are no longer CSE'd (since it
requires dominance info).
I've also reorganized the LangRef documentation to remove assertions
about "sequential execution", "SSA Values", and "Dominance". Instead,
the core IR is simply "ordered" (i.e. totally ordered) and consists of
"Values". I've also clarified some things about how control flow
passes between blocks in an SSACFG region. Control Flow must enter a
region at the entry block and follow terminator operation successors
or be returned to the containing op. Graph regions do not define a
notion of control flow.
see discussion here:
https://llvm.discourse.group/t/rfc-allowing-dialects-to-relax-the-ssa-dominance-condition/833/53
Differential Revision: https://reviews.llvm.org/D80358
2020-05-15 10:33:13 -07:00
|
|
|
#include "mlir/IR/RegionKindInterface.h"
|
2021-06-23 01:16:55 +00:00
|
|
|
#include "mlir/IR/Threading.h"
|
2023-07-12 08:52:21 +00:00
|
|
|
#include "llvm/ADT/DenseMapInfoVariant.h"
|
2024-08-09 10:50:25 -05:00
|
|
|
#include "llvm/ADT/PointerIntPair.h"
|
2019-10-19 13:38:31 -07:00
|
|
|
#include "llvm/ADT/StringMap.h"
|
2021-06-10 09:58:05 +02:00
|
|
|
#include "llvm/Support/FormatVariadic.h"
|
2018-08-05 21:12:29 -07:00
|
|
|
#include "llvm/Support/PrettyStackTrace.h"
|
2021-06-10 09:58:05 +02:00
|
|
|
#include "llvm/Support/Regex.h"
|
2021-06-08 17:08:30 +00:00
|
|
|
#include <atomic>
|
2023-01-13 21:05:06 -08:00
|
|
|
#include <optional>
|
2021-06-08 17:08:30 +00:00
|
|
|
|
2018-07-06 10:46:19 -07:00
|
|
|
using namespace mlir;
|
|
|
|
|
2018-07-21 14:32:09 -07:00
|
|
|
namespace {
|
2019-06-07 09:46:13 -07:00
|
|
|
/// This class encapsulates all the state used to verify an operation region.
|
|
|
|
class OperationVerifier {
|
2018-07-21 14:32:09 -07:00
|
|
|
public:
|
2022-03-16 11:45:14 -07:00
|
|
|
/// If `verifyRecursively` is true, then this will also recursively verify
|
|
|
|
/// nested operations.
|
|
|
|
explicit OperationVerifier(bool verifyRecursively)
|
|
|
|
: verifyRecursively(verifyRecursively) {}
|
|
|
|
|
2019-06-10 18:37:09 -07:00
|
|
|
/// Verify the given operation.
|
2021-04-25 16:15:17 -07:00
|
|
|
LogicalResult verifyOpAndDominance(Operation &op);
|
2019-06-10 18:37:09 -07:00
|
|
|
|
2019-06-07 09:46:13 -07:00
|
|
|
private:
|
2023-07-12 08:52:21 +00:00
|
|
|
using WorkItem = llvm::PointerUnion<Operation *, Block *>;
|
2024-08-09 10:50:25 -05:00
|
|
|
using WorkItemEntry = llvm::PointerIntPair<WorkItem, 1, bool>;
|
2023-07-12 08:52:21 +00:00
|
|
|
|
|
|
|
/// This verifier uses a DFS of the tree of operations/blocks. The method
|
|
|
|
/// verifyOnEntrance is invoked when we visit a node for the first time, i.e.
|
|
|
|
/// before visiting its children. The method verifyOnExit is invoked
|
|
|
|
/// upon exit from the subtree, i.e. when we visit a node for the second time.
|
|
|
|
LogicalResult verifyOnEntrance(Block &block);
|
|
|
|
LogicalResult verifyOnEntrance(Operation &op);
|
|
|
|
|
|
|
|
LogicalResult verifyOnExit(Block &block);
|
|
|
|
LogicalResult verifyOnExit(Operation &op);
|
2022-04-15 04:33:40 +00:00
|
|
|
|
|
|
|
/// Verify the properties and dominance relationships of this operation.
|
|
|
|
LogicalResult verifyOperation(Operation &op);
|
2019-06-07 09:46:13 -07:00
|
|
|
|
[MLIR] Add RegionKindInterface
Some dialects have semantics which is not well represented by common
SSA structures with dominance constraints. This patch allows
operations to declare the 'kind' of their contained regions.
Currently, two kinds are allowed: "SSACFG" and "Graph". The only
difference between them at the moment is that SSACFG regions are
required to have dominance, while Graph regions are not required to
have dominance. The intention is that this Interface would be
generated by ODS for existing operations, although this has not yet
been implemented. Presumably, if someone were interested in code
generation, we might also have a "CFG" dialect, which defines control
flow, but does not require SSA.
The new behavior is mostly identical to the previous behavior, since
registered operations without a RegionKindInterface are assumed to
contain SSACFG regions. However, the behavior has changed for
unregistered operations. Previously, these were checked for
dominance, however the new behavior allows dominance violations, in
order to allow the processing of unregistered dialects with Graph
regions. One implication of this is that regions in unregistered
operations with more than one op are no longer CSE'd (since it
requires dominance info).
I've also reorganized the LangRef documentation to remove assertions
about "sequential execution", "SSA Values", and "Dominance". Instead,
the core IR is simply "ordered" (i.e. totally ordered) and consists of
"Values". I've also clarified some things about how control flow
passes between blocks in an SSACFG region. Control Flow must enter a
region at the entry block and follow terminator operation successors
or be returned to the containing op. Graph regions do not define a
notion of control flow.
see discussion here:
https://llvm.discourse.group/t/rfc-allowing-dialects-to-relax-the-ssa-dominance-condition/833/53
Differential Revision: https://reviews.llvm.org/D80358
2020-05-15 10:33:13 -07:00
|
|
|
/// Verify the dominance property of regions contained within the given
|
|
|
|
/// Operation.
|
2021-06-13 21:42:06 -07:00
|
|
|
LogicalResult verifyDominanceOfContainedRegions(Operation &op,
|
|
|
|
DominanceInfo &domInfo);
|
2022-03-16 11:45:14 -07:00
|
|
|
|
|
|
|
/// A flag indicating if this verifier should recursively verify nested
|
|
|
|
/// operations.
|
|
|
|
bool verifyRecursively;
|
2018-07-21 14:32:09 -07:00
|
|
|
};
|
2021-12-07 18:27:58 +00:00
|
|
|
} // namespace
|
2018-07-06 10:46:19 -07:00
|
|
|
|
2021-04-25 16:15:17 -07:00
|
|
|
LogicalResult OperationVerifier::verifyOpAndDominance(Operation &op) {
|
2021-06-13 21:42:06 -07:00
|
|
|
// Verify the operation first, collecting any IsolatedFromAbove operations.
|
2022-04-15 04:33:40 +00:00
|
|
|
if (failed(verifyOperation(op)))
|
2019-06-10 18:37:09 -07:00
|
|
|
return failure();
|
|
|
|
|
|
|
|
// Since everything looks structurally ok to this point, we do a dominance
|
|
|
|
// check for any nested regions. We do this as a second pass since malformed
|
2021-06-13 21:42:06 -07:00
|
|
|
// CFG's can cause dominator analysis construction to crash and we want the
|
2019-06-10 18:37:09 -07:00
|
|
|
// verifier to be resilient to malformed code.
|
2021-06-13 21:42:06 -07:00
|
|
|
if (op.getNumRegions() != 0) {
|
|
|
|
DominanceInfo domInfo;
|
|
|
|
if (failed(verifyDominanceOfContainedRegions(op, domInfo)))
|
|
|
|
return failure();
|
|
|
|
}
|
2019-06-07 09:46:13 -07:00
|
|
|
|
2022-04-15 04:33:40 +00:00
|
|
|
return success();
|
2019-06-07 09:46:13 -07:00
|
|
|
}
|
|
|
|
|
2021-03-11 23:58:02 +00:00
|
|
|
/// Returns true if this block may be valid without terminator. That is if:
|
|
|
|
/// - it does not have a parent region.
|
|
|
|
/// - Or the parent region have a single block and:
|
|
|
|
/// - This region does not have a parent op.
|
|
|
|
/// - Or the parent op is unregistered.
|
|
|
|
/// - Or the parent op has the NoTerminator trait.
|
2021-04-25 16:15:17 -07:00
|
|
|
static bool mayBeValidWithoutTerminator(Block *block) {
|
2021-03-11 23:58:02 +00:00
|
|
|
if (!block->getParent())
|
|
|
|
return true;
|
|
|
|
if (!llvm::hasSingleElement(*block->getParent()))
|
|
|
|
return false;
|
|
|
|
Operation *op = block->getParentOp();
|
|
|
|
return !op || op->mightHaveTrait<OpTrait::NoTerminator>();
|
|
|
|
}
|
|
|
|
|
2023-07-12 08:52:21 +00:00
|
|
|
LogicalResult OperationVerifier::verifyOnEntrance(Block &block) {
|
2019-12-22 21:59:55 -08:00
|
|
|
for (auto arg : block.getArguments())
|
2020-01-11 08:54:04 -08:00
|
|
|
if (arg.getOwner() != &block)
|
2021-06-13 21:42:06 -07:00
|
|
|
return emitError(arg.getLoc(), "block argument not owned by block");
|
2018-12-29 09:11:58 -08:00
|
|
|
|
2019-02-08 09:52:26 -08:00
|
|
|
// Verify that this block has a terminator.
|
2021-03-11 23:58:02 +00:00
|
|
|
if (block.empty()) {
|
2021-04-25 16:15:17 -07:00
|
|
|
if (mayBeValidWithoutTerminator(&block))
|
2021-03-11 23:58:02 +00:00
|
|
|
return success();
|
2021-06-13 21:42:06 -07:00
|
|
|
return emitError(block.getParent()->getLoc(),
|
|
|
|
"empty block: expect at least a terminator");
|
2021-03-11 23:58:02 +00:00
|
|
|
}
|
2019-02-08 09:52:26 -08:00
|
|
|
|
2021-05-01 11:42:28 -07:00
|
|
|
// Check each operation, and make sure there are no branches out of the
|
|
|
|
// middle of this block.
|
2022-03-16 11:45:14 -07:00
|
|
|
for (Operation &op : block) {
|
2021-05-01 11:42:28 -07:00
|
|
|
// Only the last instructions is allowed to have successors.
|
|
|
|
if (op.getNumSuccessors() != 0 && &op != &block.back())
|
2019-06-07 09:46:13 -07:00
|
|
|
return op.emitError(
|
|
|
|
"operation with block successors must terminate its parent block");
|
2019-01-25 12:48:25 -08:00
|
|
|
}
|
|
|
|
|
2023-07-12 08:52:21 +00:00
|
|
|
return success();
|
|
|
|
}
|
|
|
|
|
|
|
|
LogicalResult OperationVerifier::verifyOnExit(Block &block) {
|
2019-02-08 09:52:26 -08:00
|
|
|
// Verify that this block is not branching to a block of a different
|
|
|
|
// region.
|
2019-03-21 17:53:00 -07:00
|
|
|
for (Block *successor : block.getSuccessors())
|
2019-02-08 09:52:26 -08:00
|
|
|
if (successor->getParent() != block.getParent())
|
2019-06-07 09:46:13 -07:00
|
|
|
return block.back().emitOpError(
|
|
|
|
"branching to block of a different region");
|
2019-02-08 09:52:26 -08:00
|
|
|
|
2021-04-25 16:15:17 -07:00
|
|
|
// If this block doesn't have to have a terminator, don't require it.
|
|
|
|
if (mayBeValidWithoutTerminator(&block))
|
|
|
|
return success();
|
|
|
|
|
2021-05-01 11:42:28 -07:00
|
|
|
Operation &terminator = block.back();
|
2021-04-25 16:15:17 -07:00
|
|
|
if (!terminator.mightHaveTrait<OpTrait::IsTerminator>())
|
|
|
|
return block.back().emitError("block with no terminator, has ")
|
|
|
|
<< terminator;
|
|
|
|
|
2019-04-02 10:24:11 -07:00
|
|
|
return success();
|
2018-12-29 09:11:58 -08:00
|
|
|
}
|
|
|
|
|
2023-07-12 08:52:21 +00:00
|
|
|
LogicalResult OperationVerifier::verifyOnEntrance(Operation &op) {
|
2018-09-05 17:45:19 -07:00
|
|
|
// Check that operands are non-nil and structurally ok.
|
2019-12-22 21:59:55 -08:00
|
|
|
for (auto operand : op.getOperands())
|
2018-09-05 17:45:19 -07:00
|
|
|
if (!operand)
|
2019-06-07 09:46:13 -07:00
|
|
|
return op.emitError("null operand found");
|
2018-08-21 08:42:19 -07:00
|
|
|
|
2019-02-26 16:43:12 -08:00
|
|
|
/// Verify that all of the attributes are okay.
|
2023-05-14 22:39:50 -07:00
|
|
|
for (auto attr : op.getDiscardableAttrDictionary()) {
|
2019-03-02 22:34:18 -08:00
|
|
|
// Check for any optional dialect specific attributes.
|
2021-11-18 05:23:32 +00:00
|
|
|
if (auto *dialect = attr.getNameDialect())
|
2019-04-02 14:02:32 -07:00
|
|
|
if (failed(dialect->verifyOperationAttribute(&op, attr)))
|
2019-04-02 10:24:11 -07:00
|
|
|
return failure();
|
2018-08-21 08:42:19 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
// If we can get operation info for this, check the custom hook.
|
2021-02-26 17:57:03 -08:00
|
|
|
OperationName opName = op.getName();
|
2023-01-14 01:25:58 -08:00
|
|
|
std::optional<RegisteredOperationName> registeredInfo =
|
|
|
|
opName.getRegisteredInfo();
|
2021-11-17 21:50:28 +00:00
|
|
|
if (registeredInfo && failed(registeredInfo->verifyInvariants(&op)))
|
2019-04-02 10:24:11 -07:00
|
|
|
return failure();
|
2018-08-21 08:42:19 -07:00
|
|
|
|
2023-07-12 08:52:21 +00:00
|
|
|
unsigned numRegions = op.getNumRegions();
|
|
|
|
if (!numRegions)
|
|
|
|
return success();
|
|
|
|
auto kindInterface = dyn_cast<RegionKindInterface>(&op);
|
2022-04-15 04:33:40 +00:00
|
|
|
SmallVector<Operation *> opsWithIsolatedRegions;
|
2023-07-12 08:52:21 +00:00
|
|
|
// Verify that all child regions are ok.
|
|
|
|
MutableArrayRef<Region> regions = op.getRegions();
|
|
|
|
for (unsigned i = 0; i < numRegions; ++i) {
|
|
|
|
Region ®ion = regions[i];
|
|
|
|
RegionKind kind =
|
|
|
|
kindInterface ? kindInterface.getRegionKind(i) : RegionKind::SSACFG;
|
|
|
|
// Check that Graph Regions only have a single basic block. This is
|
|
|
|
// similar to the code in SingleBlockImplicitTerminator, but doesn't
|
|
|
|
// require the trait to be specified. This arbitrary limitation is
|
|
|
|
// designed to limit the number of cases that have to be handled by
|
|
|
|
// transforms and conversions.
|
|
|
|
if (op.isRegistered() && kind == RegionKind::Graph) {
|
|
|
|
// Non-empty regions must contain a single basic block.
|
|
|
|
if (!region.empty() && !region.hasOneBlock())
|
|
|
|
return op.emitOpError("expects graph region #")
|
|
|
|
<< i << " to have 0 or 1 blocks";
|
|
|
|
}
|
2022-04-15 04:33:40 +00:00
|
|
|
|
2023-07-12 08:52:21 +00:00
|
|
|
if (region.empty())
|
|
|
|
continue;
|
2021-06-13 21:42:06 -07:00
|
|
|
|
2023-07-12 08:52:21 +00:00
|
|
|
// Verify the first block has no predecessors.
|
|
|
|
Block *firstBB = ®ion.front();
|
|
|
|
if (!firstBB->hasNoPredecessors())
|
|
|
|
return emitError(op.getLoc(),
|
|
|
|
"entry block of region may not have predecessors");
|
[MLIR] Add RegionKindInterface
Some dialects have semantics which is not well represented by common
SSA structures with dominance constraints. This patch allows
operations to declare the 'kind' of their contained regions.
Currently, two kinds are allowed: "SSACFG" and "Graph". The only
difference between them at the moment is that SSACFG regions are
required to have dominance, while Graph regions are not required to
have dominance. The intention is that this Interface would be
generated by ODS for existing operations, although this has not yet
been implemented. Presumably, if someone were interested in code
generation, we might also have a "CFG" dialect, which defines control
flow, but does not require SSA.
The new behavior is mostly identical to the previous behavior, since
registered operations without a RegionKindInterface are assumed to
contain SSACFG regions. However, the behavior has changed for
unregistered operations. Previously, these were checked for
dominance, however the new behavior allows dominance violations, in
order to allow the processing of unregistered dialects with Graph
regions. One implication of this is that regions in unregistered
operations with more than one op are no longer CSE'd (since it
requires dominance info).
I've also reorganized the LangRef documentation to remove assertions
about "sequential execution", "SSA Values", and "Dominance". Instead,
the core IR is simply "ordered" (i.e. totally ordered) and consists of
"Values". I've also clarified some things about how control flow
passes between blocks in an SSACFG region. Control Flow must enter a
region at the entry block and follow terminator operation successors
or be returned to the containing op. Graph regions do not define a
notion of control flow.
see discussion here:
https://llvm.discourse.group/t/rfc-allowing-dialects-to-relax-the-ssa-dominance-condition/833/53
Differential Revision: https://reviews.llvm.org/D80358
2020-05-15 10:33:13 -07:00
|
|
|
}
|
2023-07-12 08:52:21 +00:00
|
|
|
return success();
|
|
|
|
}
|
2019-01-25 12:48:25 -08:00
|
|
|
|
2023-07-12 08:52:21 +00:00
|
|
|
LogicalResult OperationVerifier::verifyOnExit(Operation &op) {
|
|
|
|
SmallVector<Operation *> opsWithIsolatedRegions;
|
|
|
|
if (verifyRecursively) {
|
|
|
|
for (Region ®ion : op.getRegions())
|
|
|
|
for (Block &block : region)
|
|
|
|
for (Operation &o : block)
|
|
|
|
if (o.getNumRegions() != 0 &&
|
|
|
|
o.hasTrait<OpTrait::IsIsolatedFromAbove>())
|
|
|
|
opsWithIsolatedRegions.push_back(&o);
|
|
|
|
}
|
2022-04-15 04:33:40 +00:00
|
|
|
if (failed(failableParallelForEach(
|
|
|
|
op.getContext(), opsWithIsolatedRegions,
|
2023-07-12 08:52:21 +00:00
|
|
|
[&](Operation *o) { return verifyOpAndDominance(*o); })))
|
2022-04-15 04:33:40 +00:00
|
|
|
return failure();
|
2023-07-12 08:52:21 +00:00
|
|
|
OperationName opName = op.getName();
|
|
|
|
std::optional<RegisteredOperationName> registeredInfo =
|
|
|
|
opName.getRegisteredInfo();
|
2022-02-25 18:17:30 +00:00
|
|
|
// After the region ops are verified, run the verifiers that have additional
|
|
|
|
// region invariants need to veirfy.
|
|
|
|
if (registeredInfo && failed(registeredInfo->verifyRegionInvariants(&op)))
|
|
|
|
return failure();
|
|
|
|
|
2019-03-31 23:30:22 -07:00
|
|
|
// If this is a registered operation, there is nothing left to do.
|
2021-11-17 21:50:28 +00:00
|
|
|
if (registeredInfo)
|
2019-04-02 10:24:11 -07:00
|
|
|
return success();
|
2019-03-31 23:30:22 -07:00
|
|
|
|
|
|
|
// Otherwise, verify that the parent dialect allows un-registered operations.
|
2021-02-26 17:57:03 -08:00
|
|
|
Dialect *dialect = opName.getDialect();
|
|
|
|
if (!dialect) {
|
2021-04-25 16:15:17 -07:00
|
|
|
if (!op.getContext()->allowsUnregisteredDialects()) {
|
2021-02-26 17:57:03 -08:00
|
|
|
return op.emitOpError()
|
|
|
|
<< "created with unregistered dialect. If this is "
|
|
|
|
"intended, please call allowUnregisteredDialects() on the "
|
|
|
|
"MLIRContext, or use -allow-unregistered-dialect with "
|
2021-07-15 02:13:30 +00:00
|
|
|
"the MLIR opt tool used";
|
2020-03-29 22:35:38 +00:00
|
|
|
}
|
2021-02-26 17:57:03 -08:00
|
|
|
return success();
|
2019-03-31 23:30:22 -07:00
|
|
|
}
|
|
|
|
|
2021-02-26 17:57:03 -08:00
|
|
|
if (!dialect->allowsUnknownOperations()) {
|
2019-06-07 09:46:13 -07:00
|
|
|
return op.emitError("unregistered operation '")
|
2021-02-26 17:57:03 -08:00
|
|
|
<< op.getName() << "' found in dialect ('" << dialect->getNamespace()
|
2019-06-07 09:46:13 -07:00
|
|
|
<< "') that does not allow unknown operations";
|
2019-03-31 23:30:22 -07:00
|
|
|
}
|
|
|
|
|
2019-04-02 10:24:11 -07:00
|
|
|
return success();
|
2018-08-21 08:42:19 -07:00
|
|
|
}
|
|
|
|
|
2023-07-12 08:52:21 +00:00
|
|
|
/// Verify the properties and dominance relationships of this operation,
|
|
|
|
/// stopping region "recursion" at any "isolated from above operations".
|
|
|
|
/// Such ops are collected separately and verified inside
|
|
|
|
/// verifyBlockPostChildren.
|
|
|
|
LogicalResult OperationVerifier::verifyOperation(Operation &op) {
|
2024-08-09 10:50:25 -05:00
|
|
|
SmallVector<WorkItemEntry> worklist{{&op, false}};
|
2023-07-12 08:52:21 +00:00
|
|
|
while (!worklist.empty()) {
|
2024-08-09 10:50:25 -05:00
|
|
|
WorkItemEntry &top = worklist.back();
|
2023-07-12 08:52:21 +00:00
|
|
|
|
|
|
|
auto visit = [](auto &&visitor, WorkItem w) {
|
2024-12-13 08:00:45 -08:00
|
|
|
if (auto *o = dyn_cast<Operation *>(w))
|
|
|
|
return visitor(o);
|
|
|
|
return visitor(cast<Block *>(w));
|
2023-07-12 08:52:21 +00:00
|
|
|
};
|
|
|
|
|
2024-08-09 10:50:25 -05:00
|
|
|
const bool isExit = top.getInt();
|
|
|
|
top.setInt(true);
|
|
|
|
auto item = top.getPointer();
|
|
|
|
|
2023-07-12 08:52:21 +00:00
|
|
|
// 2nd visit of this work item ("exit").
|
|
|
|
if (isExit) {
|
2024-08-09 10:50:25 -05:00
|
|
|
if (failed(
|
|
|
|
visit([this](auto *workItem) { return verifyOnExit(*workItem); },
|
|
|
|
item)))
|
2023-07-12 08:52:21 +00:00
|
|
|
return failure();
|
2024-08-09 10:50:25 -05:00
|
|
|
worklist.pop_back();
|
2023-07-12 08:52:21 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// 1st visit of this work item ("entrance").
|
|
|
|
if (failed(visit(
|
|
|
|
[this](auto *workItem) { return verifyOnEntrance(*workItem); },
|
2024-08-09 10:50:25 -05:00
|
|
|
item)))
|
2023-07-12 08:52:21 +00:00
|
|
|
return failure();
|
|
|
|
|
2024-12-13 08:00:45 -08:00
|
|
|
if (Block *currentBlock = dyn_cast<Block *>(item)) {
|
2023-07-12 08:52:21 +00:00
|
|
|
// Skip "isolated from above operations".
|
2024-12-13 08:00:45 -08:00
|
|
|
for (Operation &o : llvm::reverse(*currentBlock)) {
|
2023-07-12 08:52:21 +00:00
|
|
|
if (o.getNumRegions() == 0 ||
|
|
|
|
!o.hasTrait<OpTrait::IsIsolatedFromAbove>())
|
|
|
|
worklist.emplace_back(&o);
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2024-12-13 08:00:45 -08:00
|
|
|
Operation ¤tOp = *cast<Operation *>(item);
|
2023-07-12 08:52:21 +00:00
|
|
|
if (verifyRecursively)
|
|
|
|
for (Region ®ion : llvm::reverse(currentOp.getRegions()))
|
|
|
|
for (Block &block : llvm::reverse(region))
|
|
|
|
worklist.emplace_back(&block);
|
|
|
|
}
|
|
|
|
return success();
|
|
|
|
}
|
|
|
|
|
2021-05-01 11:42:28 -07:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Dominance Checking
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2021-04-25 16:15:17 -07:00
|
|
|
/// Emit an error when the specified operand of the specified operation is an
|
|
|
|
/// invalid use because of dominance properties.
|
|
|
|
static void diagnoseInvalidOperandDominance(Operation &op, unsigned operandNo) {
|
|
|
|
InFlightDiagnostic diag = op.emitError("operand #")
|
|
|
|
<< operandNo << " does not dominate this use";
|
|
|
|
|
|
|
|
Value operand = op.getOperand(operandNo);
|
|
|
|
|
|
|
|
/// Attach a note to an in-flight diagnostic that provide more information
|
|
|
|
/// about where an op operand is defined.
|
2020-12-16 04:18:41 +00:00
|
|
|
if (auto *useOp = operand.getDefiningOp()) {
|
|
|
|
Diagnostic ¬e = diag.attachNote(useOp->getLoc());
|
|
|
|
note << "operand defined here";
|
|
|
|
Block *block1 = op.getBlock();
|
|
|
|
Block *block2 = useOp->getBlock();
|
|
|
|
Region *region1 = block1->getParent();
|
|
|
|
Region *region2 = block2->getParent();
|
|
|
|
if (block1 == block2)
|
|
|
|
note << " (op in the same block)";
|
|
|
|
else if (region1 == region2)
|
|
|
|
note << " (op in the same region)";
|
|
|
|
else if (region2->isProperAncestor(region1))
|
|
|
|
note << " (op in a parent region)";
|
|
|
|
else if (region1->isProperAncestor(region2))
|
|
|
|
note << " (op in a child region)";
|
|
|
|
else
|
|
|
|
note << " (op is neither in a parent nor in a child region)";
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
// Block argument case.
|
|
|
|
Block *block1 = op.getBlock();
|
2023-05-11 11:10:46 +02:00
|
|
|
Block *block2 = llvm::cast<BlockArgument>(operand).getOwner();
|
2020-12-16 04:18:41 +00:00
|
|
|
Region *region1 = block1->getParent();
|
|
|
|
Region *region2 = block2->getParent();
|
|
|
|
Location loc = UnknownLoc::get(op.getContext());
|
|
|
|
if (block2->getParentOp())
|
|
|
|
loc = block2->getParentOp()->getLoc();
|
|
|
|
Diagnostic ¬e = diag.attachNote(loc);
|
|
|
|
if (!region2) {
|
|
|
|
note << " (block without parent)";
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (block1 == block2)
|
|
|
|
llvm::report_fatal_error("Internal error in dominance verification");
|
|
|
|
int index = std::distance(region2->begin(), block2->getIterator());
|
|
|
|
note << "operand defined as a block argument (block #" << index;
|
|
|
|
if (region1 == region2)
|
|
|
|
note << " in the same region)";
|
|
|
|
else if (region2->isProperAncestor(region1))
|
|
|
|
note << " in a parent region)";
|
|
|
|
else if (region1->isProperAncestor(region2))
|
|
|
|
note << " in a child region)";
|
|
|
|
else
|
|
|
|
note << " neither in a parent nor in a child region)";
|
|
|
|
}
|
|
|
|
|
2021-06-10 09:58:05 +02:00
|
|
|
/// Verify the dominance of each of the nested blocks within the given operation
|
[MLIR] Add RegionKindInterface
Some dialects have semantics which is not well represented by common
SSA structures with dominance constraints. This patch allows
operations to declare the 'kind' of their contained regions.
Currently, two kinds are allowed: "SSACFG" and "Graph". The only
difference between them at the moment is that SSACFG regions are
required to have dominance, while Graph regions are not required to
have dominance. The intention is that this Interface would be
generated by ODS for existing operations, although this has not yet
been implemented. Presumably, if someone were interested in code
generation, we might also have a "CFG" dialect, which defines control
flow, but does not require SSA.
The new behavior is mostly identical to the previous behavior, since
registered operations without a RegionKindInterface are assumed to
contain SSACFG regions. However, the behavior has changed for
unregistered operations. Previously, these were checked for
dominance, however the new behavior allows dominance violations, in
order to allow the processing of unregistered dialects with Graph
regions. One implication of this is that regions in unregistered
operations with more than one op are no longer CSE'd (since it
requires dominance info).
I've also reorganized the LangRef documentation to remove assertions
about "sequential execution", "SSA Values", and "Dominance". Instead,
the core IR is simply "ordered" (i.e. totally ordered) and consists of
"Values". I've also clarified some things about how control flow
passes between blocks in an SSACFG region. Control Flow must enter a
region at the entry block and follow terminator operation successors
or be returned to the containing op. Graph regions do not define a
notion of control flow.
see discussion here:
https://llvm.discourse.group/t/rfc-allowing-dialects-to-relax-the-ssa-dominance-condition/833/53
Differential Revision: https://reviews.llvm.org/D80358
2020-05-15 10:33:13 -07:00
|
|
|
LogicalResult
|
2021-06-13 21:42:06 -07:00
|
|
|
OperationVerifier::verifyDominanceOfContainedRegions(Operation &op,
|
|
|
|
DominanceInfo &domInfo) {
|
2023-12-05 18:06:28 +09:00
|
|
|
llvm::SmallVector<Operation *, 8> worklist{&op};
|
|
|
|
while (!worklist.empty()) {
|
|
|
|
auto *op = worklist.pop_back_val();
|
|
|
|
for (auto ®ion : op->getRegions())
|
|
|
|
for (auto &block : region.getBlocks()) {
|
|
|
|
// Dominance is only meaningful inside reachable blocks.
|
|
|
|
bool isReachable = domInfo.isReachableFromEntry(&block);
|
|
|
|
for (auto &op : block) {
|
|
|
|
if (isReachable) {
|
|
|
|
// Check that operands properly dominate this use.
|
|
|
|
for (const auto &operand : llvm::enumerate(op.getOperands())) {
|
|
|
|
if (domInfo.properlyDominates(operand.value(), &op))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
diagnoseInvalidOperandDominance(op, operand.index());
|
|
|
|
return failure();
|
|
|
|
}
|
2021-06-10 09:58:05 +02:00
|
|
|
}
|
2021-05-29 17:08:33 -07:00
|
|
|
|
2023-12-05 18:06:28 +09:00
|
|
|
// Recursively verify dominance within each operation in the block,
|
|
|
|
// even if the block itself is not reachable, or we are in a region
|
|
|
|
// which doesn't respect dominance.
|
|
|
|
if (verifyRecursively && op.getNumRegions() != 0) {
|
|
|
|
// If this operation is IsolatedFromAbove, then we'll handle it in
|
|
|
|
// the outer verification loop.
|
|
|
|
if (op.hasTrait<OpTrait::IsIsolatedFromAbove>())
|
|
|
|
continue;
|
|
|
|
worklist.push_back(&op);
|
|
|
|
}
|
2021-06-13 21:42:06 -07:00
|
|
|
}
|
2021-05-29 10:33:20 -07:00
|
|
|
}
|
[MLIR] Add RegionKindInterface
Some dialects have semantics which is not well represented by common
SSA structures with dominance constraints. This patch allows
operations to declare the 'kind' of their contained regions.
Currently, two kinds are allowed: "SSACFG" and "Graph". The only
difference between them at the moment is that SSACFG regions are
required to have dominance, while Graph regions are not required to
have dominance. The intention is that this Interface would be
generated by ODS for existing operations, although this has not yet
been implemented. Presumably, if someone were interested in code
generation, we might also have a "CFG" dialect, which defines control
flow, but does not require SSA.
The new behavior is mostly identical to the previous behavior, since
registered operations without a RegionKindInterface are assumed to
contain SSACFG regions. However, the behavior has changed for
unregistered operations. Previously, these were checked for
dominance, however the new behavior allows dominance violations, in
order to allow the processing of unregistered dialects with Graph
regions. One implication of this is that regions in unregistered
operations with more than one op are no longer CSE'd (since it
requires dominance info).
I've also reorganized the LangRef documentation to remove assertions
about "sequential execution", "SSA Values", and "Dominance". Instead,
the core IR is simply "ordered" (i.e. totally ordered) and consists of
"Values". I've also clarified some things about how control flow
passes between blocks in an SSACFG region. Control Flow must enter a
region at the entry block and follow terminator operation successors
or be returned to the containing op. Graph regions do not define a
notion of control flow.
see discussion here:
https://llvm.discourse.group/t/rfc-allowing-dialects-to-relax-the-ssa-dominance-condition/833/53
Differential Revision: https://reviews.llvm.org/D80358
2020-05-15 10:33:13 -07:00
|
|
|
}
|
2023-12-05 18:06:28 +09:00
|
|
|
|
2019-04-02 10:24:11 -07:00
|
|
|
return success();
|
2018-09-21 14:40:36 -07:00
|
|
|
}
|
|
|
|
|
2018-07-06 10:46:19 -07:00
|
|
|
//===----------------------------------------------------------------------===//
|
2019-07-03 13:21:24 -07:00
|
|
|
// Entrypoint
|
2018-07-06 10:46:19 -07:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2022-03-16 11:45:14 -07:00
|
|
|
LogicalResult mlir::verify(Operation *op, bool verifyRecursively) {
|
|
|
|
OperationVerifier verifier(verifyRecursively);
|
|
|
|
return verifier.verifyOpAndDominance(*op);
|
2019-07-02 15:00:38 -07:00
|
|
|
}
|