2021-05-05 15:13:14 -07:00
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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2022-10-07 14:56:02 +02:00
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4
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2022-04-07 12:03:55 +02:00
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2022-10-07 14:56:02 +02:00
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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[OPENMP] Codegen for 'reduction' clause in 'sections' directive.
Emit a code for reduction clause. Next code should be emitted for reductions:
static kmp_critical_name lock = { 0 };
void reduce_func(void *lhs[<n>], void *rhs[<n>]) {
*(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
...
*(Type<n>-1*)lhs[<n>-1] =
ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
*(Type<n>-1*)rhs[<n>-1]);
}
...
void *RedList[<n>] = {&<RHSExprs>[0], ..., &<RHSExprs>[<n>-1]};
switch (__kmpc_reduce{_nowait}(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>)) {
case 1:
<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]);
...
<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]);
__kmpc_end_reduce{_nowait}(<loc>, <gtid>, &<lock>);
break;
case 2:
Atomic(<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]));
...
Atomic(<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]));
break;
default:;
}
Reduction variables are a kind of a private variables, they have private copies, but initial values are chosen in accordance with the reduction operation.
If sections directive has only single section, then original shared variables are used instead with barrier at the end of the directive.
Differential Revision: http://reviews.llvm.org/D9242
llvm-svn: 235835
2015-04-27 05:04:13 +00:00
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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volatile double g;
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template <class T>
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struct S {
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T f;
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S(T a) : f(a + g) {}
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S() : f(g) {}
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operator T() { return T(); }
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S &operator&(const S &) { return *this; }
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~S() {}
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};
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template <typename T>
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T tmain() {
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T t;
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S<T> test;
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T t_var = T(), t_var1;
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T vec[] = {1, 2};
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S<T> s_arr[] = {1, 2};
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S<T> var(3), var1;
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#pragma omp parallel
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#pragma omp sections reduction(+:t_var) reduction(&:var) reduction(&& : var1) reduction(min: t_var1) nowait
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{
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vec[0] = t_var;
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#pragma omp section
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s_arr[0] = var;
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}
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return T();
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}
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int main() {
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#ifdef LAMBDA
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[&]() {
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#pragma omp parallel
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#pragma omp sections reduction(+:g)
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{
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// Reduction list for runtime.
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g = 1;
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2021-05-05 15:13:14 -07:00
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[OPENMP] Codegen for 'reduction' clause in 'sections' directive.
Emit a code for reduction clause. Next code should be emitted for reductions:
static kmp_critical_name lock = { 0 };
void reduce_func(void *lhs[<n>], void *rhs[<n>]) {
*(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
...
*(Type<n>-1*)lhs[<n>-1] =
ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
*(Type<n>-1*)rhs[<n>-1]);
}
...
void *RedList[<n>] = {&<RHSExprs>[0], ..., &<RHSExprs>[<n>-1]};
switch (__kmpc_reduce{_nowait}(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>)) {
case 1:
<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]);
...
<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]);
__kmpc_end_reduce{_nowait}(<loc>, <gtid>, &<lock>);
break;
case 2:
Atomic(<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]));
...
Atomic(<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]));
break;
default:;
}
Reduction variables are a kind of a private variables, they have private copies, but initial values are chosen in accordance with the reduction operation.
If sections directive has only single section, then original shared variables are used instead with barrier at the end of the directive.
Differential Revision: http://reviews.llvm.org/D9242
llvm-svn: 235835
2015-04-27 05:04:13 +00:00
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#pragma omp section
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[&]() {
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g = 2;
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}();
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}
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}();
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return 0;
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#elif defined(BLOCKS)
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^{
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#pragma omp parallel
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#pragma omp sections reduction(-:g)
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{
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// Reduction list for runtime.
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g = 1;
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2021-05-05 15:13:14 -07:00
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[OPENMP] Codegen for 'reduction' clause in 'sections' directive.
Emit a code for reduction clause. Next code should be emitted for reductions:
static kmp_critical_name lock = { 0 };
void reduce_func(void *lhs[<n>], void *rhs[<n>]) {
*(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
...
*(Type<n>-1*)lhs[<n>-1] =
ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
*(Type<n>-1*)rhs[<n>-1]);
}
...
void *RedList[<n>] = {&<RHSExprs>[0], ..., &<RHSExprs>[<n>-1]};
switch (__kmpc_reduce{_nowait}(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>)) {
case 1:
<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]);
...
<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]);
__kmpc_end_reduce{_nowait}(<loc>, <gtid>, &<lock>);
break;
case 2:
Atomic(<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]));
...
Atomic(<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]));
break;
default:;
}
Reduction variables are a kind of a private variables, they have private copies, but initial values are chosen in accordance with the reduction operation.
If sections directive has only single section, then original shared variables are used instead with barrier at the end of the directive.
Differential Revision: http://reviews.llvm.org/D9242
llvm-svn: 235835
2015-04-27 05:04:13 +00:00
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#pragma omp section
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^{
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g = 2;
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}();
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}
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}();
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return 0;
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#else
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S<float> test;
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float t_var = 0, t_var1;
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int vec[] = {1, 2};
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S<float> s_arr[] = {1, 2};
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S<float> var(3), var1;
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#pragma omp parallel
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#pragma omp sections reduction(+:t_var) reduction(&:var) reduction(&& : var1) reduction(min: t_var1)
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{
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{
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vec[0] = t_var;
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s_arr[0] = var;
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vec[1] = t_var1;
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s_arr[1] = var1;
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}
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}
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return tmain<int>();
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#endif
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}
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// Reduction list for runtime.
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2015-09-10 08:12:02 +00:00
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[OPENMP] Codegen for 'reduction' clause in 'sections' directive.
Emit a code for reduction clause. Next code should be emitted for reductions:
static kmp_critical_name lock = { 0 };
void reduce_func(void *lhs[<n>], void *rhs[<n>]) {
*(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
...
*(Type<n>-1*)lhs[<n>-1] =
ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
*(Type<n>-1*)rhs[<n>-1]);
}
...
void *RedList[<n>] = {&<RHSExprs>[0], ..., &<RHSExprs>[<n>-1]};
switch (__kmpc_reduce{_nowait}(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>)) {
case 1:
<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]);
...
<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]);
__kmpc_end_reduce{_nowait}(<loc>, <gtid>, &<lock>);
break;
case 2:
Atomic(<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]));
...
Atomic(<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]));
break;
default:;
}
Reduction variables are a kind of a private variables, they have private copies, but initial values are chosen in accordance with the reduction operation.
If sections directive has only single section, then original shared variables are used instead with barrier at the end of the directive.
Differential Revision: http://reviews.llvm.org/D9242
llvm-svn: 235835
2015-04-27 05:04:13 +00:00
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// For + reduction operation initial value of private variable is 0.
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// For & reduction operation initial value of private variable is ones in all bits.
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// For && reduction operation initial value of private variable is 1.0.
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// For min reduction operation initial value of private variable is largest repesentable value.
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// Skip checks for internal operations.
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2022-10-07 14:56:02 +02:00
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// ptr RedList[<n>] = {<ReductionVars>[0], ..., <ReductionVars>[<n>-1]};
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[OPENMP] Codegen for 'reduction' clause in 'sections' directive.
Emit a code for reduction clause. Next code should be emitted for reductions:
static kmp_critical_name lock = { 0 };
void reduce_func(void *lhs[<n>], void *rhs[<n>]) {
*(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
...
*(Type<n>-1*)lhs[<n>-1] =
ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
*(Type<n>-1*)rhs[<n>-1]);
}
...
void *RedList[<n>] = {&<RHSExprs>[0], ..., &<RHSExprs>[<n>-1]};
switch (__kmpc_reduce{_nowait}(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>)) {
case 1:
<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]);
...
<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]);
__kmpc_end_reduce{_nowait}(<loc>, <gtid>, &<lock>);
break;
case 2:
Atomic(<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]));
...
Atomic(<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]));
break;
default:;
}
Reduction variables are a kind of a private variables, they have private copies, but initial values are chosen in accordance with the reduction operation.
If sections directive has only single section, then original shared variables are used instead with barrier at the end of the directive.
Differential Revision: http://reviews.llvm.org/D9242
llvm-svn: 235835
2015-04-27 05:04:13 +00:00
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// res = __kmpc_reduce_nowait(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>);
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// switch(res)
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// case 1:
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// t_var += t_var_reduction;
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// var = var.operator &(var_reduction);
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// var1 = var1.operator &&(var1_reduction);
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// t_var1 = min(t_var1, t_var1_reduction);
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// __kmpc_end_reduce_nowait(<loc>, <gtid>, &<lock>);
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// break;
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// case 2:
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// t_var += t_var_reduction;
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// var = var.operator &(var_reduction);
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// var1 = var1.operator &&(var1_reduction);
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// t_var1 = min(t_var1, t_var1_reduction);
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// break;
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2022-10-07 14:56:02 +02:00
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// void reduce_func(ptr lhs[<n>], ptr rhs[<n>]) {
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[OPENMP] Codegen for 'reduction' clause in 'sections' directive.
Emit a code for reduction clause. Next code should be emitted for reductions:
static kmp_critical_name lock = { 0 };
void reduce_func(void *lhs[<n>], void *rhs[<n>]) {
*(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
...
*(Type<n>-1*)lhs[<n>-1] =
ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
*(Type<n>-1*)rhs[<n>-1]);
}
...
void *RedList[<n>] = {&<RHSExprs>[0], ..., &<RHSExprs>[<n>-1]};
switch (__kmpc_reduce{_nowait}(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>)) {
case 1:
<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]);
...
<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]);
__kmpc_end_reduce{_nowait}(<loc>, <gtid>, &<lock>);
break;
case 2:
Atomic(<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]));
...
Atomic(<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]));
break;
default:;
}
Reduction variables are a kind of a private variables, they have private copies, but initial values are chosen in accordance with the reduction operation.
If sections directive has only single section, then original shared variables are used instead with barrier at the end of the directive.
Differential Revision: http://reviews.llvm.org/D9242
llvm-svn: 235835
2015-04-27 05:04:13 +00:00
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// *(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
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// ...
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// *(Type<n>-1*)lhs[<n>-1] = ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
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// *(Type<n>-1*)rhs[<n>-1]);
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// }
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2022-10-07 14:56:02 +02:00
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// t_var_lhs = (iptr)lhs[0];
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// t_var_rhs = (iptr)rhs[0];
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[OPENMP] Codegen for 'reduction' clause in 'sections' directive.
Emit a code for reduction clause. Next code should be emitted for reductions:
static kmp_critical_name lock = { 0 };
void reduce_func(void *lhs[<n>], void *rhs[<n>]) {
*(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
...
*(Type<n>-1*)lhs[<n>-1] =
ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
*(Type<n>-1*)rhs[<n>-1]);
}
...
void *RedList[<n>] = {&<RHSExprs>[0], ..., &<RHSExprs>[<n>-1]};
switch (__kmpc_reduce{_nowait}(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>)) {
case 1:
<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]);
...
<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]);
__kmpc_end_reduce{_nowait}(<loc>, <gtid>, &<lock>);
break;
case 2:
Atomic(<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]));
...
Atomic(<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]));
break;
default:;
}
Reduction variables are a kind of a private variables, they have private copies, but initial values are chosen in accordance with the reduction operation.
If sections directive has only single section, then original shared variables are used instead with barrier at the end of the directive.
Differential Revision: http://reviews.llvm.org/D9242
llvm-svn: 235835
2015-04-27 05:04:13 +00:00
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2022-10-07 14:56:02 +02:00
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// var_lhs = (Sptr)lhs[1];
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// var_rhs = (Sptr)rhs[1];
|
[OPENMP] Codegen for 'reduction' clause in 'sections' directive.
Emit a code for reduction clause. Next code should be emitted for reductions:
static kmp_critical_name lock = { 0 };
void reduce_func(void *lhs[<n>], void *rhs[<n>]) {
*(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
...
*(Type<n>-1*)lhs[<n>-1] =
ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
*(Type<n>-1*)rhs[<n>-1]);
}
...
void *RedList[<n>] = {&<RHSExprs>[0], ..., &<RHSExprs>[<n>-1]};
switch (__kmpc_reduce{_nowait}(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>)) {
case 1:
<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]);
...
<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]);
__kmpc_end_reduce{_nowait}(<loc>, <gtid>, &<lock>);
break;
case 2:
Atomic(<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]));
...
Atomic(<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]));
break;
default:;
}
Reduction variables are a kind of a private variables, they have private copies, but initial values are chosen in accordance with the reduction operation.
If sections directive has only single section, then original shared variables are used instead with barrier at the end of the directive.
Differential Revision: http://reviews.llvm.org/D9242
llvm-svn: 235835
2015-04-27 05:04:13 +00:00
|
|
|
|
2022-10-07 14:56:02 +02:00
|
|
|
// var1_lhs = (Sptr)lhs[2];
|
|
|
|
// var1_rhs = (Sptr)rhs[2];
|
[OPENMP] Codegen for 'reduction' clause in 'sections' directive.
Emit a code for reduction clause. Next code should be emitted for reductions:
static kmp_critical_name lock = { 0 };
void reduce_func(void *lhs[<n>], void *rhs[<n>]) {
*(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
...
*(Type<n>-1*)lhs[<n>-1] =
ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
*(Type<n>-1*)rhs[<n>-1]);
}
...
void *RedList[<n>] = {&<RHSExprs>[0], ..., &<RHSExprs>[<n>-1]};
switch (__kmpc_reduce{_nowait}(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>)) {
case 1:
<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]);
...
<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]);
__kmpc_end_reduce{_nowait}(<loc>, <gtid>, &<lock>);
break;
case 2:
Atomic(<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]));
...
Atomic(<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]));
break;
default:;
}
Reduction variables are a kind of a private variables, they have private copies, but initial values are chosen in accordance with the reduction operation.
If sections directive has only single section, then original shared variables are used instead with barrier at the end of the directive.
Differential Revision: http://reviews.llvm.org/D9242
llvm-svn: 235835
2015-04-27 05:04:13 +00:00
|
|
|
|
2022-10-07 14:56:02 +02:00
|
|
|
// t_var1_lhs = (iptr)lhs[3];
|
|
|
|
// t_var1_rhs = (iptr)rhs[3];
|
[OPENMP] Codegen for 'reduction' clause in 'sections' directive.
Emit a code for reduction clause. Next code should be emitted for reductions:
static kmp_critical_name lock = { 0 };
void reduce_func(void *lhs[<n>], void *rhs[<n>]) {
*(Type0*)lhs[0] = ReductionOperation0(*(Type0*)lhs[0], *(Type0*)rhs[0]);
...
*(Type<n>-1*)lhs[<n>-1] =
ReductionOperation<n>-1(*(Type<n>-1*)lhs[<n>-1],
*(Type<n>-1*)rhs[<n>-1]);
}
...
void *RedList[<n>] = {&<RHSExprs>[0], ..., &<RHSExprs>[<n>-1]};
switch (__kmpc_reduce{_nowait}(<loc>, <gtid>, <n>, sizeof(RedList), RedList, reduce_func, &<lock>)) {
case 1:
<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]);
...
<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]);
__kmpc_end_reduce{_nowait}(<loc>, <gtid>, &<lock>);
break;
case 2:
Atomic(<LHSExprs>[0] = ReductionOperation0(*<LHSExprs>[0], *<RHSExprs>[0]));
...
Atomic(<LHSExprs>[<n>-1] = ReductionOperation<n>-1(*<LHSExprs>[<n>-1], *<RHSExprs>[<n>-1]));
break;
default:;
}
Reduction variables are a kind of a private variables, they have private copies, but initial values are chosen in accordance with the reduction operation.
If sections directive has only single section, then original shared variables are used instead with barrier at the end of the directive.
Differential Revision: http://reviews.llvm.org/D9242
llvm-svn: 235835
2015-04-27 05:04:13 +00:00
|
|
|
|
|
|
|
// t_var_lhs += t_var_rhs;
|
|
|
|
|
|
|
|
// var_lhs = var_lhs.operator &(var_rhs);
|
|
|
|
|
|
|
|
// var1_lhs = var1_lhs.operator &&(var1_rhs);
|
|
|
|
|
|
|
|
// t_var1_lhs = min(t_var1_lhs, t_var1_rhs);
|
|
|
|
|
|
|
|
#endif
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@main
|
|
|
|
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
|
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
|
|
|
|
// CHECK1-NEXT: [[T_VAR:%.*]] = alloca float, align 4
|
|
|
|
// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca float, align 4
|
|
|
|
// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
|
|
|
// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
|
|
|
|
// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4
|
|
|
|
// CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
|
|
|
|
// CHECK1-NEXT: store float 0.000000e+00, ptr [[T_VAR]], align 4
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
|
|
|
|
// CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
|
|
|
|
// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], float noundef 3.000000e+00)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]])
|
|
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 6, ptr @.omp_outlined., ptr [[T_VAR]], ptr [[VAR]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]])
|
2022-01-16 18:53:11 +09:00
|
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]]
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK1: arraydestroy.body:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK1: arraydestroy.done1:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: ret i32 [[TMP2]]
|
2021-05-05 15:13:14 -07:00
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3:[0-9]+]] {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[VAR1_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[T_VAR1_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[T_VAR2:%.*]] = alloca float, align 4
|
|
|
|
// CHECK1-NEXT: [[VAR3:%.*]] = alloca [[STRUCT_S:%.*]], align 4
|
|
|
|
// CHECK1-NEXT: [[VAR14:%.*]] = alloca [[STRUCT_S]], align 4
|
|
|
|
// CHECK1-NEXT: [[T_VAR15:%.*]] = alloca float, align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [4 x ptr], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[REF_TMP16:%.*]] = alloca [[STRUCT_S]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[ATOMIC_TEMP:%.*]] = alloca float, align 4
|
|
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca float, align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[VAR1]], ptr [[VAR1_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4
|
|
|
|
// CHECK1-NEXT: store float 0.000000e+00, ptr [[T_VAR2]], align 4
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
|
|
|
|
// CHECK1-NEXT: store float 0x47EFFFFFE0000000, ptr [[T_VAR15]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)
|
|
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 0
|
|
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP8]], i32 0
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.cond:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.body:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: switch i32 [[TMP14]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]
|
|
|
|
// CHECK1-NEXT: ]
|
|
|
|
// CHECK1: .omp.sections.case:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load float, ptr [[T_VAR2]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP15]] to i32
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4
|
|
|
|
// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR3]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[T_VAR15]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[CONV7:%.*]] = fptosi float [[TMP18]] to i32
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 1
|
|
|
|
// CHECK1-NEXT: store i32 [[CONV7]], ptr [[ARRAYIDX8]], align 4
|
|
|
|
// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i64 0, i64 1
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR14]], i64 4, i1 false)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]
|
|
|
|
// CHECK1: .omp.sections.exit:
|
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.inc:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP21]], 1
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
|
|
// CHECK1: omp.inner.for.end:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP7]])
|
|
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP22]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1
|
|
|
|
// CHECK1-NEXT: store ptr [[VAR3]], ptr [[TMP24]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2
|
|
|
|
// CHECK1-NEXT: store ptr [[VAR14]], ptr [[TMP26]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 3
|
|
|
|
// CHECK1-NEXT: store ptr [[T_VAR15]], ptr [[TMP28]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 4, i64 32, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var)
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: switch i32 [[TMP31]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
|
|
|
|
// CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
|
|
|
|
// CHECK1-NEXT: ]
|
|
|
|
// CHECK1: .omp.reduction.case1:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = load float, ptr [[TMP0]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = load float, ptr [[T_VAR2]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP32]], [[TMP33]]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store float [[ADD]], ptr [[TMP0]], align 4
|
|
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[CALL]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: [[CALL10:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]])
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL10]], 0.000000e+00
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
|
|
|
|
// CHECK1: land.rhs:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[CALL11:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TOBOOL12:%.*]] = fcmp une float [[CALL11]], 0.000000e+00
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[LAND_END]]
|
|
|
|
// CHECK1: land.end:
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL12]], [[LAND_RHS]] ]
|
|
|
|
// CHECK1-NEXT: [[CONV13:%.*]] = uitofp i1 [[TMP36]] to float
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], float noundef [[CONV13]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = load float, ptr [[TMP3]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = load float, ptr [[T_VAR15]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[CMP14:%.*]] = fcmp olt float [[TMP39]], [[TMP40]]
|
|
|
|
// CHECK1-NEXT: br i1 [[CMP14]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1: cond.true:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP41:%.*]] = load float, ptr [[TMP3]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
|
|
// CHECK1: cond.false:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP42:%.*]] = load float, ptr [[T_VAR15]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
|
|
// CHECK1: cond.end:
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi float [ [[TMP41]], [[COND_TRUE]] ], [ [[TMP42]], [[COND_FALSE]] ]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store float [[COND]], ptr [[TMP3]], align 4
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP7]], ptr @.gomp_critical_user_.reduction.var)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
|
|
|
|
// CHECK1: .omp.reduction.case2:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP43:%.*]] = load float, ptr [[T_VAR2]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP44:%.*]] = atomicrmw fadd ptr [[TMP0]], float [[TMP43]] monotonic, align 4
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
|
|
|
|
// CHECK1-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[CALL15]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
|
|
|
|
// CHECK1-NEXT: [[CALL17:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]])
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TOBOOL18:%.*]] = fcmp une float [[CALL17]], 0.000000e+00
|
|
|
|
// CHECK1-NEXT: br i1 [[TOBOOL18]], label [[LAND_RHS19:%.*]], label [[LAND_END22:%.*]]
|
|
|
|
// CHECK1: land.rhs19:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[CALL20:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TOBOOL21:%.*]] = fcmp une float [[CALL20]], 0.000000e+00
|
|
|
|
// CHECK1-NEXT: br label [[LAND_END22]]
|
|
|
|
// CHECK1: land.end22:
|
|
|
|
// CHECK1-NEXT: [[TMP47:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL21]], [[LAND_RHS19]] ]
|
|
|
|
// CHECK1-NEXT: [[CONV23:%.*]] = uitofp i1 [[TMP47]] to float
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP16]], float noundef [[CONV23]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP16]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
|
|
|
|
// CHECK1-NEXT: [[TMP50:%.*]] = load float, ptr [[T_VAR15]], align 4
|
|
|
|
// CHECK1-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i32, ptr [[TMP3]] monotonic, align 4
|
2022-05-03 11:30:46 -04:00
|
|
|
// CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]]
|
|
|
|
// CHECK1: atomic_cont:
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TMP52:%.*]] = phi i32 [ [[ATOMIC_LOAD]], [[LAND_END22]] ], [ [[TMP62:%.*]], [[COND_END27:%.*]] ]
|
|
|
|
// CHECK1-NEXT: [[TMP54:%.*]] = bitcast i32 [[TMP52]] to float
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store float [[TMP54]], ptr [[TMP]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP55:%.*]] = load float, ptr [[TMP]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP56:%.*]] = load float, ptr [[T_VAR15]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[CMP24:%.*]] = fcmp olt float [[TMP55]], [[TMP56]]
|
|
|
|
// CHECK1-NEXT: br i1 [[CMP24]], label [[COND_TRUE25:%.*]], label [[COND_FALSE26:%.*]]
|
|
|
|
// CHECK1: cond.true25:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP57:%.*]] = load float, ptr [[TMP]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: br label [[COND_END27]]
|
|
|
|
// CHECK1: cond.false26:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP58:%.*]] = load float, ptr [[T_VAR15]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: br label [[COND_END27]]
|
|
|
|
// CHECK1: cond.end27:
|
|
|
|
// CHECK1-NEXT: [[COND28:%.*]] = phi float [ [[TMP57]], [[COND_TRUE25]] ], [ [[TMP58]], [[COND_FALSE26]] ]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store float [[COND28]], ptr [[ATOMIC_TEMP]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP61:%.*]] = cmpxchg ptr [[TMP3]], i32 [[TMP52]], i32 [[TMP59]] monotonic monotonic, align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TMP62]] = extractvalue { i32, i1 } [[TMP61]], 0
|
|
|
|
// CHECK1-NEXT: [[TMP63:%.*]] = extractvalue { i32, i1 } [[TMP61]], 1
|
|
|
|
// CHECK1-NEXT: br i1 [[TMP63]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]
|
2022-05-03 11:30:46 -04:00
|
|
|
// CHECK1: atomic_exit:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP7]], ptr @.gomp_critical_user_.reduction.var)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
|
|
|
|
// CHECK1: .omp.reduction.default:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP7]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S:%.*]], align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP4]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP4]], i64 0, i64 1
|
|
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 1
|
|
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP4]], i64 0, i64 2
|
|
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 2
|
|
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP4]], i64 0, i64 3
|
|
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 3
|
|
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = load float, ptr [[TMP10]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load float, ptr [[TMP7]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP30]], [[TMP31]]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store float [[ADD]], ptr [[TMP10]], align 4
|
|
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP16]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP16]], ptr align 4 [[CALL]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: [[CALL2:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP22]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[TOBOOL:%.*]] = fcmp une float [[CALL2]], 0.000000e+00
|
|
|
|
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
|
|
|
|
// CHECK1: land.rhs:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[CALL3:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP19]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[TOBOOL4:%.*]] = fcmp une float [[CALL3]], 0.000000e+00
|
|
|
|
// CHECK1-NEXT: br label [[LAND_END]]
|
|
|
|
// CHECK1: land.end:
|
|
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ]
|
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP34]] to float
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], float noundef [[CONV]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP22]], ptr align 4 [[REF_TMP]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = load float, ptr [[TMP28]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP38:%.*]] = load float, ptr [[TMP25]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP37]], [[TMP38]]
|
|
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
|
|
// CHECK1: cond.true:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = load float, ptr [[TMP28]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
|
|
// CHECK1: cond.false:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = load float, ptr [[TMP25]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
|
|
// CHECK1: cond.end:
|
|
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi float [ [[TMP39]], [[COND_TRUE]] ], [ [[TMP40]], [[COND_FALSE]] ]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store float [[COND]], ptr [[TMP28]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: ret ptr [[THIS1]]
|
2021-05-05 15:13:14 -07:00
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR6]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret float 0.000000e+00
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
|
|
|
|
// CHECK1-SAME: () #[[ATTR6]] {
|
|
|
|
// CHECK1-NEXT: entry:
|
|
|
|
// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[T:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
|
|
|
|
// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
|
|
|
|
// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
|
|
|
|
// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
|
|
|
|
// CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
|
|
|
|
// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
|
|
|
|
// CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
|
|
|
|
// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]])
|
|
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @.omp_outlined..1, ptr [[T_VAR]], ptr [[VAR]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]])
|
|
|
|
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
|
|
|
|
// CHECK1: arraydestroy.body:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
|
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
|
|
|
|
// CHECK1: arraydestroy.done1:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: ret i32 [[TMP2]]
|
2021-05-05 15:13:14 -07:00
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile double, ptr @g, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = fptrunc double [[TMP0]] to float
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, ptr @g, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]]
|
|
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = fptrunc double [[ADD]] to float
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store float [[CONV2]], ptr [[F]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR3]] {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[VAR1_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[T_VAR1_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK1-NEXT: [[VAR3:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
|
|
|
|
// CHECK1-NEXT: [[VAR14:%.*]] = alloca [[STRUCT_S_0]], align 4
|
|
|
|
// CHECK1-NEXT: [[T_VAR15:%.*]] = alloca i32, align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [4 x ptr], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[REF_TMP13:%.*]] = alloca [[STRUCT_S_0]], align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[VAR1]], ptr [[VAR1_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
|
|
|
|
// CHECK1-NEXT: store i32 2147483647, ptr [[T_VAR15]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)
|
|
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = icmp slt i32 [[TMP8]], 1
|
|
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP8]], i32 1
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.cond:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.body:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: switch i32 [[TMP14]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE6:%.*]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ]
|
|
|
|
// CHECK1: .omp.sections.case:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4
|
|
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1: .omp.sections.case6:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP5]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR3]], i64 4, i1 false)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]
|
|
|
|
// CHECK1: .omp.sections.exit:
|
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
|
|
// CHECK1: omp.inner.for.inc:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP18]], 1
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
|
|
// CHECK1: omp.inner.for.end:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP7]])
|
|
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP19]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1
|
|
|
|
// CHECK1-NEXT: store ptr [[VAR3]], ptr [[TMP21]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 2
|
|
|
|
// CHECK1-NEXT: store ptr [[VAR14]], ptr [[TMP23]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 3
|
|
|
|
// CHECK1-NEXT: store ptr [[T_VAR15]], ptr [[TMP25]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP7]], i32 4, i64 32, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @.omp.reduction.reduction_func.2, ptr @.gomp_critical_user_.reduction.var)
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: switch i32 [[TMP28]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
|
|
|
|
// CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
|
|
|
|
// CHECK1-NEXT: ]
|
|
|
|
// CHECK1: .omp.reduction.case1:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[T_VAR2]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP0]], align 4
|
|
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[CALL]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: [[CALL8:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]])
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL8]], 0
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
|
|
|
|
// CHECK1: land.rhs:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[CALL9:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TOBOOL10:%.*]] = icmp ne i32 [[CALL9]], 0
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[LAND_END]]
|
|
|
|
// CHECK1: land.end:
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE1]] ], [ [[TOBOOL10]], [[LAND_RHS]] ]
|
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP33]] to i32
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[CONV]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP3]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[T_VAR15]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP36]], [[TMP37]]
|
|
|
|
// CHECK1-NEXT: br i1 [[CMP11]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1: cond.true:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP3]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
|
|
// CHECK1: cond.false:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[T_VAR15]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
|
|
// CHECK1: cond.end:
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP38]], [[COND_TRUE]] ], [ [[TMP39]], [[COND_FALSE]] ]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[COND]], ptr [[TMP3]], align 4
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP7]], ptr @.gomp_critical_user_.reduction.var)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
|
|
|
|
// CHECK1: .omp.reduction.case2:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[T_VAR2]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP41:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP40]] monotonic, align 4
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
|
|
|
|
// CHECK1-NEXT: [[CALL12:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[CALL12]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
|
|
|
|
// CHECK1-NEXT: [[CALL14:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]])
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TOBOOL15:%.*]] = icmp ne i32 [[CALL14]], 0
|
|
|
|
// CHECK1-NEXT: br i1 [[TOBOOL15]], label [[LAND_RHS16:%.*]], label [[LAND_END19:%.*]]
|
|
|
|
// CHECK1: land.rhs16:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[CALL17:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]])
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK1-NEXT: [[TOBOOL18:%.*]] = icmp ne i32 [[CALL17]], 0
|
|
|
|
// CHECK1-NEXT: br label [[LAND_END19]]
|
|
|
|
// CHECK1: land.end19:
|
|
|
|
// CHECK1-NEXT: [[TMP44:%.*]] = phi i1 [ false, [[DOTOMP_REDUCTION_CASE2]] ], [ [[TOBOOL18]], [[LAND_RHS16]] ]
|
|
|
|
// CHECK1-NEXT: [[CONV20:%.*]] = zext i1 [[TMP44]] to i32
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP13]], i32 noundef [[CONV20]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP13]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP13]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var)
|
|
|
|
// CHECK1-NEXT: [[TMP47:%.*]] = load i32, ptr [[T_VAR15]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP48:%.*]] = atomicrmw min ptr [[TMP3]], i32 [[TMP47]] monotonic, align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
|
|
|
|
// CHECK1: .omp.reduction.default:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR4]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR5]] {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP4]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 0
|
|
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP4]], i64 0, i64 1
|
|
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 1
|
|
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP4]], i64 0, i64 2
|
|
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 2
|
|
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP4]], i64 0, i64 3
|
|
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x ptr], ptr [[TMP2]], i64 0, i64 3
|
|
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8
|
|
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP10]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP7]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP10]], align 4
|
|
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP16]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP16]], ptr align 4 [[CALL]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP22]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL2]], 0
|
|
|
|
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
|
|
|
|
// CHECK1: land.rhs:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP19]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[TOBOOL4:%.*]] = icmp ne i32 [[CALL3]], 0
|
|
|
|
// CHECK1-NEXT: br label [[LAND_END]]
|
|
|
|
// CHECK1: land.end:
|
|
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TOBOOL4]], [[LAND_RHS]] ]
|
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP34]] to i32
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[CONV]])
|
|
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP22]], ptr align 4 [[REF_TMP]], i64 4, i1 false)
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
|
|
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP28]], align 4
|
|
|
|
// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP25]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]]
|
|
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
|
|
// CHECK1: cond.true:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP28]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
|
|
// CHECK1: cond.false:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP25]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
|
|
// CHECK1: cond.end:
|
|
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE]] ], [ [[TMP40]], [[COND_FALSE]] ]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[COND]], ptr [[TMP28]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR6]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: ret ptr [[THIS1]]
|
2021-05-05 15:13:14 -07:00
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR6]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret i32 0
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load volatile double, ptr @g, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i32
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[CONV]], ptr [[F]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to double
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, ptr @g, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], [[TMP1]]
|
|
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = fptosi double [[ADD]] to i32
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: store i32 [[CONV2]], ptr [[F]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK1-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@main
|
|
|
|
// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
|
|
|
|
// CHECK3-NEXT: entry:
|
|
|
|
// CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
|
|
|
// CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: ret i32 0
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK3-NEXT: [[G:%.*]] = alloca double, align 8
|
|
|
|
// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8
|
|
|
|
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4
|
|
|
|
// CHECK3-NEXT: store double 0.000000e+00, ptr [[G]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)
|
|
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 1
|
|
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 1
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
|
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4
|
|
|
|
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
|
|
// CHECK3: omp.inner.for.cond:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
|
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
|
|
// CHECK3: omp.inner.for.body:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK3-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]
|
|
|
|
// CHECK3-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]]
|
|
|
|
// CHECK3-NEXT: ]
|
|
|
|
// CHECK3: .omp.sections.case:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: store double 1.000000e+00, ptr [[G]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]
|
|
|
|
// CHECK3: .omp.sections.case1:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
|
|
|
|
// CHECK3-NEXT: store ptr [[G]], ptr [[TMP9]], align 8
|
|
|
|
// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]
|
|
|
|
// CHECK3: .omp.sections.exit:
|
|
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
|
|
// CHECK3: omp.inner.for.inc:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
|
|
// CHECK3: omp.inner.for.end:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
|
|
|
|
// CHECK3-NEXT: store ptr [[G]], ptr [[TMP11]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var)
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK3-NEXT: switch i32 [[TMP14]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
|
|
|
|
// CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
|
|
|
|
// CHECK3-NEXT: ]
|
|
|
|
// CHECK3: .omp.reduction.case1:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load double, ptr @g, align 8
|
|
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load double, ptr [[G]], align 8
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[TMP15]], [[TMP16]]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: store double [[ADD]], ptr @g, align 8
|
|
|
|
// CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP1]], ptr @.gomp_critical_user_.reduction.var)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
|
|
|
|
// CHECK3: .omp.reduction.case2:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = load double, ptr [[G]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = atomicrmw fadd ptr @g, double [[TMP17]] monotonic, align 8
|
|
|
|
// CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP1]], ptr @.gomp_critical_user_.reduction.var)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
|
|
|
|
// CHECK3: .omp.reduction.default:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP1]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
|
|
|
|
// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0
|
|
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0
|
|
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load double, ptr [[TMP10]], align 8
|
|
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[TMP7]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[TMP12]], [[TMP13]]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK3-NEXT: store double [[ADD]], ptr [[TMP10]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK3-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@main
|
|
|
|
// CHECK4-SAME: () #[[ATTR1:[0-9]+]] {
|
|
|
|
// CHECK4-NEXT: entry:
|
|
|
|
// CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8
|
|
|
|
// CHECK4-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: ret i32 0
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4:[0-9]+]], i32 0, ptr @.omp_outlined.)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4
|
|
|
|
// CHECK4-NEXT: [[G:%.*]] = alloca double, align 8
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double }>, align 8
|
|
|
|
// CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8
|
|
|
|
// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4
|
|
|
|
// CHECK4-NEXT: store double 0.000000e+00, ptr [[G]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1)
|
|
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 1
|
|
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 1
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
|
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_LB_]], align 4
|
|
|
|
// CHECK4-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
|
|
// CHECK4: omp.inner.for.cond:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
|
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_UB_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
|
|
// CHECK4: omp.inner.for.body:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK4-NEXT: switch i32 [[TMP8]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]]
|
|
|
|
// CHECK4-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]]
|
|
|
|
// CHECK4-NEXT: ]
|
|
|
|
// CHECK4: .omp.sections.case:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: store double 1.000000e+00, ptr [[G]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]
|
|
|
|
// CHECK4: .omp.sections.case1:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 0
|
|
|
|
// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 1
|
|
|
|
// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 2
|
|
|
|
// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4
|
|
|
|
// CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 3
|
|
|
|
// CHECK4-NEXT: store ptr @_block_invoke, ptr [[BLOCK_INVOKE]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 4
|
|
|
|
// CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[BLOCK]], i32 0, i32 5
|
|
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load volatile double, ptr [[G]], align 8
|
|
|
|
// CHECK4-NEXT: store volatile double [[TMP9]], ptr [[BLOCK_CAPTURED]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
|
|
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP11]], align 8
|
|
|
|
// CHECK4-NEXT: call void [[TMP13]](ptr noundef [[BLOCK]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]]
|
|
|
|
// CHECK4: .omp.sections.exit:
|
|
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
|
|
// CHECK4: omp.inner.for.inc:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP15]], 1
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: store i32 [[INC]], ptr [[DOTOMP_SECTIONS_IV_]], align 4
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
|
|
// CHECK4: omp.inner.for.end:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0
|
|
|
|
// CHECK4-NEXT: store ptr [[G]], ptr [[TMP16]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var)
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK4-NEXT: switch i32 [[TMP19]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
|
|
|
|
// CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
|
|
|
|
// CHECK4-NEXT: ]
|
|
|
|
// CHECK4: .omp.reduction.case1:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = load double, ptr @g, align 8
|
|
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = load double, ptr [[G]], align 8
|
2022-09-15 03:08:46 +00:00
|
|
|
// CHECK4-NEXT: [[ADD:%.*]] = fadd double [[TMP20]], [[TMP21]]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: store double [[ADD]], ptr @g, align 8
|
|
|
|
// CHECK4-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP1]], ptr @.gomp_critical_user_.reduction.var)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
|
|
|
|
// CHECK4: .omp.reduction.case2:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = load double, ptr [[G]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = atomicrmw fadd ptr @g, double [[TMP22]] monotonic, align 8
|
|
|
|
// CHECK4-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP1]], ptr @.gomp_critical_user_.reduction.var)
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]]
|
|
|
|
// CHECK4: .omp.reduction.default:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP1]])
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@_block_invoke
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5
|
|
|
|
// CHECK4-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: entry:
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
|
|
|
|
// CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
|
|
|
|
// CHECK4-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0
|
|
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0
|
|
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load double, ptr [[TMP10]], align 8
|
|
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load double, ptr [[TMP7]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: [[ADD:%.*]] = fadd double [[TMP12]], [[TMP13]]
|
2022-10-07 14:56:02 +02:00
|
|
|
// CHECK4-NEXT: store double [[ADD]], ptr [[TMP10]], align 8
|
2021-05-05 15:13:14 -07:00
|
|
|
// CHECK4-NEXT: ret void
|
|
|
|
//
|