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llvm-project/llvm/docs/AMDGPU/gfx7_vsrc_ba3116.rst

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[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-17 17:38:11 +00:00
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[AMDGPU][GFX7][DOC][NFC] Update assembler syntax description Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable abs and neg modifiers for v_cndmask_b32_e64. - Minor corrections and improvements.
2022-12-13 13:46:56 +03:00
.. _amdgpu_synid_gfx7_vsrc_ba3116:
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-17 17:38:11 +00:00
vsrc
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
2021-08-27 17:16:22 +03:00
====
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-17 17:38:11 +00:00
Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
[AMDGPU][GFX7][DOC][NFC] Update assembler syntax description Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable abs and neg modifiers for v_cndmask_b32_e64. - Minor corrections and improvements.
2022-12-13 13:46:56 +03:00
The :ref:`compr<amdgpu_synid_compr>` modifier indicates the use of compressed (16-bit) data, thus decreasing the number of source operands from 4 to 2:
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-17 17:38:11 +00:00
* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
An example:
[AMDGPU][MC][DOC] A fix for build failure in r349370 llvm-svn: 349375
2018-12-17 18:53:10 +00:00
.. parsed-literal::
[AMDGPU][MC][DOC] Updated AMD GPU assembler description Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
2018-12-17 17:38:11 +00:00
exp mrtz v3, v3, off, off compr
*Size:* 1 dword.
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
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