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Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
//===- RISCV.cpp ----------------------------------------------------------===//
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 08:50:56 +00:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
//
//===----------------------------------------------------------------------===//
[ELF] Don't rely on Symbols.h's transitive inclusion of InputFiles.h. NFC
2022-02-23 20:44:34 -08:00
#include "InputFiles.h"
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
#include "OutputSections.h"
[ELF] writePlt, writeIplt: replace parameters gotPltEntryAddr and index with `const Symbol &`. NFC PPC::writeIplt (IPLT code sequence, D71621) needs to access `Symbol`. Reviewed By: grimar, ruiu Differential Revision: https://reviews.llvm.org/D71631
2019-12-17 13:43:04 -08:00
#include "Symbols.h"
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
#include "SyntheticSections.h"
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
#include "Target.h"
[ELF] Merge SHT_RISCV_ATTRIBUTES sections Currently we take the first SHT_RISCV_ATTRIBUTES (.riscv.attributes) as the output. If we link an object without an extension with an object with the extension, the output Tag_RISCV_arch may not contain the extension and some tools like objdump -d will not decode the related instructions. This patch implements Tag_RISCV_stack_align/Tag_RISCV_arch/Tag_RISCV_unaligned_access merge as specified by https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#attributes For the deprecated Tag_RISCV_priv_spec{,_minor,_revision}, dump the attribute to the output iff all input agree on the value. This is different from GNU ld but our simple approach should be ok for deprecated tags. `RISCVAttributeParser::handler` currently warns about unknown tags. This behavior is retained. In GNU ld arm, tags >= 64 (mod 128) are ignored with a warning. If RISC-V ever wants to do something similar (https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/352), consider documenting it in the psABI and changing RISCVAttributeParser. Like GNU ld, zero value integer attributes and empty string attributes are not dumped to the output. Reviewed By: asb, kito-cheng Differential Revision: https://reviews.llvm.org/D138550
2022-12-08 09:53:40 +00:00
#include "llvm/Support/ELFAttributes.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Support/RISCVAttributeParser.h"
#include "llvm/Support/RISCVAttributes.h"
#include "llvm/Support/RISCVISAInfo.h"
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
#include "llvm/Support/TimeProfiler.h"
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
using namespace llvm;
using namespace llvm::object;
using namespace llvm::support::endian;
using namespace llvm::ELF;
[ELF] Use namespace qualifiers (lld:: or elf::) instead of `namespace lld { namespace elf {` Similar to D74882. This reverts much code from commit bd8cfe65f5fee4ad573adc2172359c9552e8cdc0 (D68323) and fixes some problems before D68323. Sorry for the churn but D68323 was a mistake. Namespace qualifiers avoid bugs where the definition does not match the declaration from the header. See https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implement-previously-declared-functions (D74515) Differential Revision: https://reviews.llvm.org/D79982
2020-05-14 22:18:58 -07:00
using namespace lld;
using namespace lld::elf;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
namespace {
class RISCV final : public TargetInfo {
public:
[ELF] - Do not fail on R_*_NONE relocations when parsing the debug info. This is https://bugs.llvm.org//show_bug.cgi?id=38919. Currently, LLD may report "unsupported relocation target while parsing debug info" when parsing the debug information. At the same time LLD does that for zeroed R_X86_64_NONE relocations, which obviously has "invalid" targets. The nature of R_*_NONE relocation assumes them should be ignored. This patch teaches LLD to stop reporting the debug information parsing errors for them. Differential revision: https://reviews.llvm.org/D52408 llvm-svn: 343078
2018-09-26 08:11:34 +00:00
RISCV();
Omit "virtual" if overridden. llvm-svn: 345886
2018-11-01 20:08:39 +00:00
uint32_t calcEFlags() const override;
[ELF] Implement RISCV::getImplicitAddend() This allows checking dynamic relocation addends for -z rel and --apply-dynamic-relocs output. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D101455
2021-07-09 10:12:43 +01:00
int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
void writeGotHeader(uint8_t *buf) const override;
void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
[ELF] Write R_RISCV_IRELATIVE addends with -z rel I found this missing case with the new --check-dynamic-relocation flag while running the lld tests with --apply-dynamic-relocs enabled by default. This is the same as D101452 just for RISC-V Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D101454
2021-07-09 10:12:21 +01:00
void writeIgotPlt(uint8_t *buf, const Symbol &s) const override;
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
void writePltHeader(uint8_t *buf) const override;
[ELF] writePlt, writeIplt: replace parameters gotPltEntryAddr and index with `const Symbol &`. NFC PPC::writeIplt (IPLT code sequence, D71621) needs to access `Symbol`. Reviewed By: grimar, ruiu Differential Revision: https://reviews.llvm.org/D71631
2019-12-17 13:43:04 -08:00
void writePlt(uint8_t *buf, const Symbol &sym,
uint64_t pltEntryAddr) const override;
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
RelType getDynRel(RelType type) const override;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
void relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const override;
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
bool relaxOnce(int pass) const override;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
};
} // end anonymous namespace
[ELF][RISCV] Support GD/LD/IE/LE TLS models RISC-V psABI doesn't specify TLS relaxation. It can be handled the same way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use the same relocation type. Reviewed By: jrtc27, ruiu Differential Revision: https://reviews.llvm.org/D63220 llvm-svn: 364813
2019-07-01 17:12:26 +00:00
const uint64_t dtpOffset = 0x800;
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
enum Op {
ADDI = 0x13,
AUIPC = 0x17,
JALR = 0x67,
LD = 0x3003,
LW = 0x2003,
SRLI = 0x5013,
SUB = 0x40000033,
};
enum Reg {
X_RA = 1,
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
X_TP = 4,
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
X_T0 = 5,
X_T1 = 6,
X_T2 = 7,
X_T3 = 28,
};
static uint32_t hi20(uint32_t val) { return (val + 0x800) >> 12; }
static uint32_t lo12(uint32_t val) { return val & 4095; }
static uint32_t itype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t imm) {
return op | (rd << 7) | (rs1 << 15) | (imm << 20);
}
static uint32_t rtype(uint32_t op, uint32_t rd, uint32_t rs1, uint32_t rs2) {
return op | (rd << 7) | (rs1 << 15) | (rs2 << 20);
}
static uint32_t utype(uint32_t op, uint32_t rd, uint32_t imm) {
return op | (rd << 7) | (imm << 12);
}
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
// Extract bits v[begin:end], where range is inclusive, and begin must be < 63.
static uint32_t extractBits(uint64_t v, uint32_t begin, uint32_t end) {
return (v & ((1ULL << (begin + 1)) - 1)) >> end;
}
static uint32_t setLO12_I(uint32_t insn, uint32_t imm) {
return (insn & 0xfffff) | (imm << 20);
}
static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
return (insn & 0x1fff07f) | (extractBits(imm, 11, 5) << 25) |
(extractBits(imm, 4, 0) << 7);
}
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
RISCV::RISCV() {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
relativeRel = R_RISCV_RELATIVE;
[ELF][RISCV] Add R_RISCV_IRELATIVE https://github.com/riscv/riscv-elf-psabi-doc/pull/131 assigned 58 to R_RISCV_IRELATIVE. Differential Revision: https://reviews.llvm.org/D74022
2020-02-04 20:33:41 -08:00
iRelativeRel = R_RISCV_IRELATIVE;
[ELF][RISCV] Support GD/LD/IE/LE TLS models RISC-V psABI doesn't specify TLS relaxation. It can be handled the same way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use the same relocation type. Reviewed By: jrtc27, ruiu Differential Revision: https://reviews.llvm.org/D63220 llvm-svn: 364813
2019-07-01 17:12:26 +00:00
if (config->is64) {
symbolicRel = R_RISCV_64;
tlsModuleIndexRel = R_RISCV_TLS_DTPMOD64;
tlsOffsetRel = R_RISCV_TLS_DTPREL64;
tlsGotRel = R_RISCV_TLS_TPREL64;
} else {
symbolicRel = R_RISCV_32;
tlsModuleIndexRel = R_RISCV_TLS_DTPMOD32;
tlsOffsetRel = R_RISCV_TLS_DTPREL32;
tlsGotRel = R_RISCV_TLS_TPREL32;
}
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
gotRel = symbolicRel;
// .got[0] = _DYNAMIC
gotHeaderEntriesNum = 1;
// .got.plt[0] = _dl_runtime_resolve, .got.plt[1] = link_map
gotPltHeaderEntriesNum = 2;
pltHeaderSize = 32;
[ELF] Add IpltSection PltSection is used by both PLT and IPLT. The PLT section may have a header while the IPLT section does not. Split off IpltSection from PltSection to be clearer. Unlike other targets, PPC64 cannot use the same code sequence for PLT and IPLT. This helps make a future PPC64 patch (D71509) more isolated. On EM_386 and EM_X86_64, when PLT is empty while IPLT is not, currently we are inconsistent whether the PLT header is conceptually attached to in.plt or in.iplt . Consistently attach the header to in.plt can make the -z retpolineplt logic simpler. It also makes `jmp` point to an aesthetically better place for non-retpolineplt cases. Reviewed By: grimar, ruiu Differential Revision: https://reviews.llvm.org/D71519
2019-12-14 14:17:35 -08:00
pltEntrySize = 16;
ipltEntrySize = 16;
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
}
[ELF] - Do not fail on R_*_NONE relocations when parsing the debug info. This is https://bugs.llvm.org//show_bug.cgi?id=38919. Currently, LLD may report "unsupported relocation target while parsing debug info" when parsing the debug information. At the same time LLD does that for zeroed R_X86_64_NONE relocations, which obviously has "invalid" targets. The nature of R_*_NONE relocation assumes them should be ignored. This patch teaches LLD to stop reporting the debug information parsing errors for them. Differential revision: https://reviews.llvm.org/D52408 llvm-svn: 343078
2018-09-26 08:11:34 +00:00
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
static uint32_t getEFlags(InputFile *f) {
if (config->is64)
[lib/Object] - Refine interface of ELFFile<ELFT>. NFCI. `ELFFile<ELFT>` has many methods that take pointers, though they assume that arguments are never null and hence could take references instead. This patch performs such clean-up. Differential revision: https://reviews.llvm.org/D87385
2020-09-09 17:03:53 +03:00
return cast<ObjFile<ELF64LE>>(f)->getObj().getHeader().e_flags;
return cast<ObjFile<ELF32LE>>(f)->getObj().getHeader().e_flags;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
}
uint32_t RISCV::calcEFlags() const {
[lld][RISCV] Use an e_flags of 0 if there are only binary input files. Summary: If none of the input files are ELF object files (for example, when generating an object file from a single binary input file via "-b binary"), use a fallback value for the ELF header flags instead of crashing with an assertion failure. Reviewers: MaskRay, ruiu, espindola Reviewed By: MaskRay, ruiu Subscribers: kevans, grimar, emaste, arichardson, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits, jrtc27 Tags: #llvm Differential Revision: https://reviews.llvm.org/D71101
2019-12-21 17:59:37 +00:00
// If there are only binary input files (from -b binary), use a
// value of 0 for the ELF header flags.
[ELF] Remove ctx indirection. NFC Add LLVM_LIBRARY_VISIBILITY to remove unneeded GOT and unique_ptr indirection. We can move other global variables into ctx without indirection concern. In the long term we may consider passing Ctx as a parameter to various functions and eliminate global state as much as possible and then remove `Ctx::reset`.
2022-10-01 12:06:33 -07:00
if (ctx.objectFiles.empty())
[lld][RISCV] Use an e_flags of 0 if there are only binary input files. Summary: If none of the input files are ELF object files (for example, when generating an object file from a single binary input file via "-b binary"), use a fallback value for the ELF header flags instead of crashing with an assertion failure. Reviewers: MaskRay, ruiu, espindola Reviewed By: MaskRay, ruiu Subscribers: kevans, grimar, emaste, arichardson, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits, jrtc27 Tags: #llvm Differential Revision: https://reviews.llvm.org/D71101
2019-12-21 17:59:37 +00:00
return 0;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
[ELF] Remove ctx indirection. NFC Add LLVM_LIBRARY_VISIBILITY to remove unneeded GOT and unique_ptr indirection. We can move other global variables into ctx without indirection concern. In the long term we may consider passing Ctx as a parameter to various functions and eliminate global state as much as possible and then remove `Ctx::reset`.
2022-10-01 12:06:33 -07:00
uint32_t target = getEFlags(ctx.objectFiles.front());
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
[ELF] Remove ctx indirection. NFC Add LLVM_LIBRARY_VISIBILITY to remove unneeded GOT and unique_ptr indirection. We can move other global variables into ctx without indirection concern. In the long term we may consider passing Ctx as a parameter to various functions and eliminate global state as much as possible and then remove `Ctx::reset`.
2022-10-01 12:06:33 -07:00
for (InputFile *f : ctx.objectFiles) {
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
uint32_t eflags = getEFlags(f);
if (eflags & EF_RISCV_RVC)
target |= EF_RISCV_RVC;
if ((eflags & EF_RISCV_FLOAT_ABI) != (target & EF_RISCV_FLOAT_ABI))
[ELF] Name ctx->objectFiles[0] in the EF_RISCV_FLOAT_ABI mismatch error Reviewed By: compnerd Differential Revision: https://reviews.llvm.org/D134198
2022-09-20 11:14:04 -07:00
error(
toString(f) +
": cannot link object files with different floating-point ABI from " +
[ELF] Remove ctx indirection. NFC Add LLVM_LIBRARY_VISIBILITY to remove unneeded GOT and unique_ptr indirection. We can move other global variables into ctx without indirection concern. In the long term we may consider passing Ctx as a parameter to various functions and eliminate global state as much as possible and then remove `Ctx::reset`.
2022-10-01 12:06:33 -07:00
toString(ctx.objectFiles[0]));
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
if ((eflags & EF_RISCV_RVE) != (target & EF_RISCV_RVE))
error(toString(f) +
": cannot link object files with different EF_RISCV_RVE");
}
return target;
}
[ELF] Implement RISCV::getImplicitAddend() This allows checking dynamic relocation addends for -z rel and --apply-dynamic-relocs output. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D101455
2021-07-09 10:12:43 +01:00
int64_t RISCV::getImplicitAddend(const uint8_t *buf, RelType type) const {
switch (type) {
default:
internalLinkerError(getErrorLocation(buf),
"cannot read addend for relocation " + toString(type));
return 0;
case R_RISCV_32:
case R_RISCV_TLS_DTPMOD32:
case R_RISCV_TLS_DTPREL32:
[ELF] Support missing relocations in RISCV::getImplicitAddend()
2022-07-30 10:55:59 -07:00
case R_RISCV_TLS_TPREL32:
[ELF] Implement RISCV::getImplicitAddend() This allows checking dynamic relocation addends for -z rel and --apply-dynamic-relocs output. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D101455
2021-07-09 10:12:43 +01:00
return SignExtend64<32>(read32le(buf));
case R_RISCV_64:
[ELF] Support missing relocations in RISCV::getImplicitAddend()
2022-07-30 10:55:59 -07:00
case R_RISCV_TLS_DTPMOD64:
case R_RISCV_TLS_DTPREL64:
case R_RISCV_TLS_TPREL64:
[ELF] Implement RISCV::getImplicitAddend() This allows checking dynamic relocation addends for -z rel and --apply-dynamic-relocs output. Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D101455
2021-07-09 10:12:43 +01:00
return read64le(buf);
case R_RISCV_RELATIVE:
case R_RISCV_IRELATIVE:
return config->is64 ? read64le(buf) : read32le(buf);
case R_RISCV_NONE:
case R_RISCV_JUMP_SLOT:
// These relocations are defined as not having an implicit addend.
return 0;
}
}
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
void RISCV::writeGotHeader(uint8_t *buf) const {
if (config->is64)
write64le(buf, mainPart->dynamic->getVA());
else
write32le(buf, mainPart->dynamic->getVA());
}
void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const {
if (config->is64)
write64le(buf, in.plt->getVA());
else
write32le(buf, in.plt->getVA());
}
[ELF] Write R_RISCV_IRELATIVE addends with -z rel I found this missing case with the new --check-dynamic-relocation flag while running the lld tests with --apply-dynamic-relocs enabled by default. This is the same as D101452 just for RISC-V Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D101454
2021-07-09 10:12:21 +01:00
void RISCV::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
if (config->writeAddends) {
if (config->is64)
write64le(buf, s.getVA());
else
write32le(buf, s.getVA());
}
}
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
void RISCV::writePltHeader(uint8_t *buf) const {
// 1: auipc t2, %pcrel_hi(.got.plt)
// sub t1, t1, t3
// l[wd] t3, %pcrel_lo(1b)(t2); t3 = _dl_runtime_resolve
[ELF] Fix variable names in comments after VariableName -> variableName change Also fix some typos. llvm-svn: 366181
2019-07-16 05:50:45 +00:00
// addi t1, t1, -pltHeaderSize-12; t1 = &.plt[i] - &.plt[0]
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
// addi t0, t2, %pcrel_lo(1b)
// srli t1, t1, (rv64?1:2); t1 = &.got.plt[i] - &.got.plt[0]
// l[wd] t0, Wordsize(t0); t0 = link_map
// jr t3
uint32_t offset = in.gotPlt->getVA() - in.plt->getVA();
uint32_t load = config->is64 ? LD : LW;
write32le(buf + 0, utype(AUIPC, X_T2, hi20(offset)));
write32le(buf + 4, rtype(SUB, X_T1, X_T1, X_T3));
write32le(buf + 8, itype(load, X_T3, X_T2, lo12(offset)));
write32le(buf + 12, itype(ADDI, X_T1, X_T1, -target->pltHeaderSize - 12));
write32le(buf + 16, itype(ADDI, X_T0, X_T2, lo12(offset)));
write32le(buf + 20, itype(SRLI, X_T1, X_T1, config->is64 ? 1 : 2));
write32le(buf + 24, itype(load, X_T0, X_T0, config->wordsize));
write32le(buf + 28, itype(JALR, 0, X_T3, 0));
}
[ELF] writePlt, writeIplt: replace parameters gotPltEntryAddr and index with `const Symbol &`. NFC PPC::writeIplt (IPLT code sequence, D71621) needs to access `Symbol`. Reviewed By: grimar, ruiu Differential Revision: https://reviews.llvm.org/D71631
2019-12-17 13:43:04 -08:00
void RISCV::writePlt(uint8_t *buf, const Symbol &sym,
uint64_t pltEntryAddr) const {
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
// 1: auipc t3, %pcrel_hi(f@.got.plt)
// l[wd] t3, %pcrel_lo(1b)(t3)
// jalr t1, t3
// nop
[ELF] writePlt, writeIplt: replace parameters gotPltEntryAddr and index with `const Symbol &`. NFC PPC::writeIplt (IPLT code sequence, D71621) needs to access `Symbol`. Reviewed By: grimar, ruiu Differential Revision: https://reviews.llvm.org/D71631
2019-12-17 13:43:04 -08:00
uint32_t offset = sym.getGotPltVA() - pltEntryAddr;
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
write32le(buf + 0, utype(AUIPC, X_T3, hi20(offset)));
write32le(buf + 4, itype(config->is64 ? LD : LW, X_T3, X_T3, lo12(offset)));
write32le(buf + 8, itype(JALR, X_T1, X_T3, 0));
write32le(buf + 12, itype(ADDI, 0, 0, 0));
}
RelType RISCV::getDynRel(RelType type) const {
[LLD] NFC: Fixed GCC warning in ELF/Arch/RISCV.cpp GCC emits warning on this line: error: enumeral and non-enumeral type in conditional expression [-Werror=extra] Change-Id: I04969cc32e27e310968b88ebaa4e1c4894528d74 llvm-svn: 365434
2019-07-09 03:56:44 +00:00
return type == target->symbolicRel ? type
: static_cast<RelType>(R_RISCV_NONE);
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
}
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s,
const uint8_t *loc) const {
switch (type) {
[ELF][RISCV] Improve error message for unknown relocations Like rLLD354040.
2019-12-31 15:06:31 -08:00
case R_RISCV_NONE:
return R_NONE;
case R_RISCV_32:
case R_RISCV_64:
case R_RISCV_HI20:
case R_RISCV_LO12_I:
case R_RISCV_LO12_S:
case R_RISCV_RVC_LUI:
return R_ABS;
[ELF][RISCV] Treat R_RISCV_{ADD,SET,SUB}* as link-time constants R_RISCV_{ADD,SET,SUB}* are used for local label computation. Add a new RelExpr member R_RISCV_ADD to represent them. R_RISCV_ADD is treated as a link-time constant because otherwise R_RISCV_{ADD,SET,SUB}* are not allowed in -pie/-shared mode. In glibc Scrt1.o, .rela.eh_frame contains such relocations. Because .eh_frame is not writable, we get this error: ld.lld: error: can't create dynamic relocation R_RISCV_ADD32 against symbol: .L0 in readonly segment; recompil object files with -fPIC or pass '-Wl,-z,notext' to allow text relocations in the output >>> defined in ..../riscv64-linux-gnu/lib/Scrt1.o With D63076 and this patch, I can run -pie/-shared programs linked against glibc. Note llvm-mc cannot currently produce R_RISCV_SET* so they are not tested. Reviewed By: ruiu Differential Revision: https://reviews.llvm.org/D63183 llvm-svn: 363128
2019-06-12 07:53:06 +00:00
case R_RISCV_ADD8:
case R_RISCV_ADD16:
case R_RISCV_ADD32:
case R_RISCV_ADD64:
case R_RISCV_SET6:
case R_RISCV_SET8:
case R_RISCV_SET16:
case R_RISCV_SET32:
case R_RISCV_SUB6:
case R_RISCV_SUB8:
case R_RISCV_SUB16:
case R_RISCV_SUB32:
case R_RISCV_SUB64:
return R_RISCV_ADD;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
case R_RISCV_JAL:
case R_RISCV_BRANCH:
case R_RISCV_PCREL_HI20:
case R_RISCV_RVC_BRANCH:
case R_RISCV_RVC_JUMP:
case R_RISCV_32_PCREL:
return R_PC;
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
case R_RISCV_CALL:
case R_RISCV_CALL_PLT:
return R_PLT_PC;
case R_RISCV_GOT_HI20:
return R_GOT_PC;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
case R_RISCV_PCREL_LO12_I:
case R_RISCV_PCREL_LO12_S:
return R_RISCV_PC_INDIRECT;
[ELF][RISCV] Support GD/LD/IE/LE TLS models RISC-V psABI doesn't specify TLS relaxation. It can be handled the same way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use the same relocation type. Reviewed By: jrtc27, ruiu Differential Revision: https://reviews.llvm.org/D63220 llvm-svn: 364813
2019-07-01 17:12:26 +00:00
case R_RISCV_TLS_GD_HI20:
return R_TLSGD_PC;
case R_RISCV_TLS_GOT_HI20:
return R_GOT_PC;
case R_RISCV_TPREL_HI20:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_TPREL_LO12_S:
[ELF] Rename R_TLS to R_TPREL and R_NEG_TLS to R_TPREL_NEG. NFC The scope of R_TLS (TP offset relocation types (TPREL/TPOFF) used for the local-exec TLS model) is actually narrower than its name may imply. R_TLS_NEG is only used by Solaris R_386_TLS_LE_32. Rename them so that they will be less confusing. Reviewed By: grimar, psmith, rprichard Differential Revision: https://reviews.llvm.org/D93467
2020-12-18 08:24:42 -08:00
return R_TPREL;
[lld][RISCV] Print error when encountering R_RISCV_ALIGN Summary: Unlike R_RISCV_RELAX, which is a linker hint, R_RISCV_ALIGN requires the support of the linker even when ignoring all R_RISCV_RELAX relocations. This is because the compiler emits as many NOPs as may be required for the requested alignment, more than may be required pre-relaxation, to allow for the target becoming more unaligned after relaxing earlier sequences. This means that the target is often not initially aligned in the object files, and so the R_RISCV_ALIGN relocations cannot just be ignored. Since we do not support linker relaxation, we must turn these into errors. Reviewers: ruiu, MaskRay, espindola Reviewed By: MaskRay Subscribers: grimar, Jim, emaste, arichardson, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71820
2020-01-21 02:49:42 +00:00
case R_RISCV_ALIGN:
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
return R_RELAX_HINT;
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
case R_RISCV_TPREL_ADD:
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
case R_RISCV_RELAX:
return config->relax ? R_RELAX_HINT : R_NONE;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
default:
[ELF][RISCV] Improve error message for unknown relocations Like rLLD354040.
2019-12-31 15:06:31 -08:00
error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
") against symbol " + toString(s));
return R_NONE;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
}
}
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 11:39:23 +00:00
const unsigned bits = config->wordsize * 8;
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
switch (rel.type) {
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
case R_RISCV_32:
write32le(loc, val);
return;
case R_RISCV_64:
write64le(loc, val);
return;
case R_RISCV_RVC_BRANCH: {
[ELF][RISCV] Use unshifted value for overflow check The unshifted value indicates an displacement in bytes which is more meaningful.
2022-07-13 00:28:29 -07:00
checkInt(loc, val, 9, rel);
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
checkAlignment(loc, val, 2, rel);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
uint16_t insn = read16le(loc) & 0xE383;
uint16_t imm8 = extractBits(val, 8, 8) << 12;
uint16_t imm4_3 = extractBits(val, 4, 3) << 10;
uint16_t imm7_6 = extractBits(val, 7, 6) << 5;
uint16_t imm2_1 = extractBits(val, 2, 1) << 3;
uint16_t imm5 = extractBits(val, 5, 5) << 2;
insn |= imm8 | imm4_3 | imm7_6 | imm2_1 | imm5;
[Coding style change] Rename variables so that they start with a lowercase letter This patch is mechanically generated by clang-llvm-rename tool that I wrote using Clang Refactoring Engine just for creating this patch. You can see the source code of the tool at https://reviews.llvm.org/D64123. There's no manual post-processing; you can generate the same patch by re-running the tool against lld's code base. Here is the main discussion thread to change the LLVM coding style: https://lists.llvm.org/pipermail/llvm-dev/2019-February/130083.html In the discussion thread, I proposed we use lld as a testbed for variable naming scheme change, and this patch does that. I chose to rename variables so that they are in camelCase, just because that is a minimal change to make variables to start with a lowercase letter. Note to downstream patch maintainers: if you are maintaining a downstream lld repo, just rebasing ahead of this commit would cause massive merge conflicts because this patch essentially changes every line in the lld subdirectory. But there's a remedy. clang-llvm-rename tool is a batch tool, so you can rename variables in your downstream repo with the tool. Given that, here is how to rebase your repo to a commit after the mass renaming: 1. rebase to the commit just before the mass variable renaming, 2. apply the tool to your downstream repo to mass-rename variables locally, and 3. rebase again to the head. Most changes made by the tool should be identical for a downstream repo and for the head, so at the step 3, almost all changes should be merged and disappear. I'd expect that there would be some lines that you need to merge by hand, but that shouldn't be too many. Differential Revision: https://reviews.llvm.org/D64121 llvm-svn: 365595
2019-07-10 05:00:37 +00:00
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
write16le(loc, insn);
return;
}
case R_RISCV_RVC_JUMP: {
[ELF][RISCV] Use unshifted value for overflow check The unshifted value indicates an displacement in bytes which is more meaningful.
2022-07-13 00:28:29 -07:00
checkInt(loc, val, 12, rel);
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
checkAlignment(loc, val, 2, rel);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
uint16_t insn = read16le(loc) & 0xE003;
uint16_t imm11 = extractBits(val, 11, 11) << 12;
uint16_t imm4 = extractBits(val, 4, 4) << 11;
uint16_t imm9_8 = extractBits(val, 9, 8) << 9;
uint16_t imm10 = extractBits(val, 10, 10) << 8;
uint16_t imm6 = extractBits(val, 6, 6) << 7;
uint16_t imm7 = extractBits(val, 7, 7) << 6;
uint16_t imm3_1 = extractBits(val, 3, 1) << 3;
uint16_t imm5 = extractBits(val, 5, 5) << 2;
insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5;
[Coding style change] Rename variables so that they start with a lowercase letter This patch is mechanically generated by clang-llvm-rename tool that I wrote using Clang Refactoring Engine just for creating this patch. You can see the source code of the tool at https://reviews.llvm.org/D64123. There's no manual post-processing; you can generate the same patch by re-running the tool against lld's code base. Here is the main discussion thread to change the LLVM coding style: https://lists.llvm.org/pipermail/llvm-dev/2019-February/130083.html In the discussion thread, I proposed we use lld as a testbed for variable naming scheme change, and this patch does that. I chose to rename variables so that they are in camelCase, just because that is a minimal change to make variables to start with a lowercase letter. Note to downstream patch maintainers: if you are maintaining a downstream lld repo, just rebasing ahead of this commit would cause massive merge conflicts because this patch essentially changes every line in the lld subdirectory. But there's a remedy. clang-llvm-rename tool is a batch tool, so you can rename variables in your downstream repo with the tool. Given that, here is how to rebase your repo to a commit after the mass renaming: 1. rebase to the commit just before the mass variable renaming, 2. apply the tool to your downstream repo to mass-rename variables locally, and 3. rebase again to the head. Most changes made by the tool should be identical for a downstream repo and for the head, so at the step 3, almost all changes should be merged and disappear. I'd expect that there would be some lines that you need to merge by hand, but that shouldn't be too many. Differential Revision: https://reviews.llvm.org/D64121 llvm-svn: 365595
2019-07-10 05:00:37 +00:00
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
write16le(loc, insn);
return;
}
case R_RISCV_RVC_LUI: {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 11:39:23 +00:00
int64_t imm = SignExtend64(val + 0x800, bits) >> 12;
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
checkInt(loc, imm, 6, rel);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
if (imm == 0) { // `c.lui rd, 0` is illegal, convert to `c.li rd, 0`
write16le(loc, (read16le(loc) & 0x0F83) | 0x4000);
} else {
uint16_t imm17 = extractBits(val + 0x800, 17, 17) << 12;
uint16_t imm16_12 = extractBits(val + 0x800, 16, 12) << 2;
write16le(loc, (read16le(loc) & 0xEF83) | imm17 | imm16_12);
}
return;
}
case R_RISCV_JAL: {
[ELF][RISCV] Use unshifted value for overflow check The unshifted value indicates an displacement in bytes which is more meaningful.
2022-07-13 00:28:29 -07:00
checkInt(loc, val, 21, rel);
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
checkAlignment(loc, val, 2, rel);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
uint32_t insn = read32le(loc) & 0xFFF;
uint32_t imm20 = extractBits(val, 20, 20) << 31;
uint32_t imm10_1 = extractBits(val, 10, 1) << 21;
uint32_t imm11 = extractBits(val, 11, 11) << 20;
uint32_t imm19_12 = extractBits(val, 19, 12) << 12;
insn |= imm20 | imm10_1 | imm11 | imm19_12;
write32le(loc, insn);
return;
}
case R_RISCV_BRANCH: {
[ELF][RISCV] Use unshifted value for overflow check The unshifted value indicates an displacement in bytes which is more meaningful.
2022-07-13 00:28:29 -07:00
checkInt(loc, val, 13, rel);
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
checkAlignment(loc, val, 2, rel);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
uint32_t insn = read32le(loc) & 0x1FFF07F;
uint32_t imm12 = extractBits(val, 12, 12) << 31;
uint32_t imm10_5 = extractBits(val, 10, 5) << 25;
uint32_t imm4_1 = extractBits(val, 4, 1) << 8;
uint32_t imm11 = extractBits(val, 11, 11) << 7;
insn |= imm12 | imm10_5 | imm4_1 | imm11;
write32le(loc, insn);
return;
}
// auipc + jalr pair
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
case R_RISCV_CALL:
case R_RISCV_CALL_PLT: {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 11:39:23 +00:00
int64_t hi = SignExtend64(val + 0x800, bits) >> 12;
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
checkInt(loc, hi, 20, rel);
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 11:39:23 +00:00
if (isInt<20>(hi)) {
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
relocateNoSym(loc, R_RISCV_PCREL_HI20, val);
relocateNoSym(loc + 4, R_RISCV_PCREL_LO12_I, val);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
}
return;
}
[ELF][RISCV] Support PLT, GOT, copy and relative relocations * Handle initial relocation types: R_RISCV_CALL_PLT and R_RISCV_GOT_HI20. * Produce dynamic relocation types: R_RISCV_COPY, R_RISCV_RELATIVE, R_RISCV_JUMP_SLOT. * Define SymbolRel as R_RISCV_{32,64} * Generate PLT header: it is used by lazy binding PLT in glibc. * R_RISCV_CALL is changed from R_PC to R_PC_PLT. If the target symbol is preemptable, this will suppress an unnecessary "canonical PLT". This behavior is different from ld.bfd but it is agreed the current lld behavior is favored. I have received positive responses from the binutils maintainer that the ABI/binutils implementation can be improved, see: https://github.com/riscv/riscv-elf-psabi-doc/issues/98 https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Many -no-pie/-pie/-shared programs linked against musl or glibc should work with this patch. Reviewed By: jrtc27 Differential Revision: https://reviews.llvm.org/D63076 llvm-svn: 364812
2019-07-01 17:12:18 +00:00
case R_RISCV_GOT_HI20:
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
case R_RISCV_PCREL_HI20:
[ELF][RISCV] Support GD/LD/IE/LE TLS models RISC-V psABI doesn't specify TLS relaxation. It can be handled the same way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use the same relocation type. Reviewed By: jrtc27, ruiu Differential Revision: https://reviews.llvm.org/D63220 llvm-svn: 364813
2019-07-01 17:12:26 +00:00
case R_RISCV_TLS_GD_HI20:
case R_RISCV_TLS_GOT_HI20:
case R_RISCV_TPREL_HI20:
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
case R_RISCV_HI20: {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 11:39:23 +00:00
uint64_t hi = val + 0x800;
[ELF] Rename relocateOne() to relocate() and pass `Relocation` to it Symbol information can be used to improve out-of-range/misalignment diagnostics. It also helps R_ARM_CALL/R_ARM_THM_CALL which has different behaviors with different symbol types. There are many (67) relocateOne() call sites used in thunks, {Arm,AArch64}errata, PLT, etc. Rename them to `relocateNoSym()` to be clearer that there is no symbol information. Reviewed By: grimar, peter.smith Differential Revision: https://reviews.llvm.org/D73254
2020-01-22 21:39:16 -08:00
checkInt(loc, SignExtend64(hi, bits) >> 12, 20, rel);
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
write32le(loc, (read32le(loc) & 0xFFF) | (hi & 0xFFFFF000));
return;
}
case R_RISCV_PCREL_LO12_I:
[ELF][RISCV] Support GD/LD/IE/LE TLS models RISC-V psABI doesn't specify TLS relaxation. It can be handled the same way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use the same relocation type. Reviewed By: jrtc27, ruiu Differential Revision: https://reviews.llvm.org/D63220 llvm-svn: 364813
2019-07-01 17:12:26 +00:00
case R_RISCV_TPREL_LO12_I:
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
case R_RISCV_LO12_I: {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 11:39:23 +00:00
uint64_t hi = (val + 0x800) >> 12;
uint64_t lo = val - (hi << 12);
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
write32le(loc, setLO12_I(read32le(loc), lo & 0xfff));
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
return;
}
case R_RISCV_PCREL_LO12_S:
[ELF][RISCV] Support GD/LD/IE/LE TLS models RISC-V psABI doesn't specify TLS relaxation. It can be handled the same way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use the same relocation type. Reviewed By: jrtc27, ruiu Differential Revision: https://reviews.llvm.org/D63220 llvm-svn: 364813
2019-07-01 17:12:26 +00:00
case R_RISCV_TPREL_LO12_S:
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
case R_RISCV_LO12_S: {
[RISCV] Fix range check for HI20/LO12/RVC_LUI relocations The code previously specified a 32-bit range for R_RISCV_HI20 and R_RISCV_LO12_[IS], however this is incorrect as the maximum offset on RV64 that can be formed from the immediate of lui and the displacement of an I-type or S-type instruction is -0x80000800 to 0x7ffff7ff. There is also the same issue with a c.lui and LO12 pair, whose actual addressable range should be -0x20800 to 0x1f7ff. The tests will be included in the next patch that converts all RISC-V tests to use llvm-mc instead of yaml2obj, as assembler support has matured enough to write tests in them. Differential Revision: https://reviews.llvm.org/D60414 llvm-svn: 357995
2019-04-09 11:39:23 +00:00
uint64_t hi = (val + 0x800) >> 12;
uint64_t lo = val - (hi << 12);
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
write32le(loc, setLO12_S(read32le(loc), lo));
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
return;
}
case R_RISCV_ADD8:
*loc += val;
return;
case R_RISCV_ADD16:
write16le(loc, read16le(loc) + val);
return;
case R_RISCV_ADD32:
write32le(loc, read32le(loc) + val);
return;
case R_RISCV_ADD64:
write64le(loc, read64le(loc) + val);
return;
case R_RISCV_SUB6:
*loc = (*loc & 0xc0) | (((*loc & 0x3f) - val) & 0x3f);
return;
case R_RISCV_SUB8:
*loc -= val;
return;
case R_RISCV_SUB16:
write16le(loc, read16le(loc) - val);
return;
case R_RISCV_SUB32:
write32le(loc, read32le(loc) - val);
return;
case R_RISCV_SUB64:
write64le(loc, read64le(loc) - val);
return;
case R_RISCV_SET6:
*loc = (*loc & 0xc0) | (val & 0x3f);
return;
case R_RISCV_SET8:
*loc = val;
return;
case R_RISCV_SET16:
write16le(loc, val);
return;
case R_RISCV_SET32:
case R_RISCV_32_PCREL:
write32le(loc, val);
return;
[ELF][RISCV] Support GD/LD/IE/LE TLS models RISC-V psABI doesn't specify TLS relaxation. It can be handled the same way as we handle ARM TLS. RISC-V TLS is even simpler because GD/LD use the same relocation type. Reviewed By: jrtc27, ruiu Differential Revision: https://reviews.llvm.org/D63220 llvm-svn: 364813
2019-07-01 17:12:26 +00:00
case R_RISCV_TLS_DTPREL32:
write32le(loc, val - dtpOffset);
break;
case R_RISCV_TLS_DTPREL64:
write64le(loc, val - dtpOffset);
break;
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
case R_RISCV_RELAX:
return; // Ignored (for now)
[ELF][RISCV] Improve error message for unknown relocations Like rLLD354040.
2019-12-31 15:06:31 -08:00
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
default:
[ELF][RISCV] Improve error message for unknown relocations Like rLLD354040.
2019-12-31 15:06:31 -08:00
llvm_unreachable("unknown relocation");
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
}
}
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
namespace {
struct SymbolAnchor {
uint64_t offset;
Defined *d;
bool end; // true for the anchor of st_value+st_size
};
} // namespace
struct elf::RISCVRelaxAux {
// This records symbol start and end offsets which will be adjusted according
// to the nearest relocDeltas element.
SmallVector<SymbolAnchor, 0> anchors;
// For relocations[i], the actual offset is r_offset - (i ? relocDeltas[i-1] :
// 0).
std::unique_ptr<uint32_t[]> relocDeltas;
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
// For relocations[i], the actual type is relocTypes[i].
std::unique_ptr<RelType[]> relocTypes;
SmallVector<uint32_t, 0> writes;
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
};
static void initSymbolAnchors() {
SmallVector<InputSection *, 0> storage;
for (OutputSection *osec : outputSections) {
if (!(osec->flags & SHF_EXECINSTR))
continue;
for (InputSection *sec : getInputSections(*osec, storage)) {
sec->relaxAux = make<RISCVRelaxAux>();
[ELF] Add InputSectionBase::{addRelocs,relocs} and GotSection::addConstant to add/access relocations to prepare for changing `relocations` from a SmallVector to a pointer. Also change the `isec` parameter in `addAddendOnlyRelocIfNonPreemptible` to `GotSection &`.
2022-11-21 04:12:03 +00:00
if (sec->relocs().size()) {
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
sec->relaxAux->relocDeltas =
[ELF] Add InputSectionBase::{addRelocs,relocs} and GotSection::addConstant to add/access relocations to prepare for changing `relocations` from a SmallVector to a pointer. Also change the `isec` parameter in `addAddendOnlyRelocIfNonPreemptible` to `GotSection &`.
2022-11-21 04:12:03 +00:00
std::make_unique<uint32_t[]>(sec->relocs().size());
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
sec->relaxAux->relocTypes =
[ELF] Add InputSectionBase::{addRelocs,relocs} and GotSection::addConstant to add/access relocations to prepare for changing `relocations` from a SmallVector to a pointer. Also change the `isec` parameter in `addAddendOnlyRelocIfNonPreemptible` to `GotSection &`.
2022-11-21 04:12:03 +00:00
std::make_unique<RelType[]>(sec->relocs().size());
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
}
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
}
}
// Store anchors (st_value and st_value+st_size) for symbols relative to text
// sections.
[ELF] Remove ctx indirection. NFC Add LLVM_LIBRARY_VISIBILITY to remove unneeded GOT and unique_ptr indirection. We can move other global variables into ctx without indirection concern. In the long term we may consider passing Ctx as a parameter to various functions and eliminate global state as much as possible and then remove `Ctx::reset`.
2022-10-01 12:06:33 -07:00
for (InputFile *file : ctx.objectFiles)
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
for (Symbol *sym : file->getSymbols()) {
auto *d = dyn_cast<Defined>(sym);
if (!d || d->file != file)
continue;
if (auto *sec = dyn_cast_or_null<InputSection>(d->section))
if (sec->flags & SHF_EXECINSTR && sec->relaxAux) {
// If sec is discarded, relaxAux will be nullptr.
sec->relaxAux->anchors.push_back({d->value, d, false});
sec->relaxAux->anchors.push_back({d->value + d->size, d, true});
}
}
// Sort anchors by offset so that we can find the closest relocation
// efficiently. For a zero size symbol, ensure that its start anchor precedes
// its end anchor. For two symbols with anchors at the same offset, their
// order does not matter.
for (OutputSection *osec : outputSections) {
if (!(osec->flags & SHF_EXECINSTR))
continue;
for (InputSection *sec : getInputSections(*osec, storage)) {
llvm::sort(sec->relaxAux->anchors, [](auto &a, auto &b) {
return std::make_pair(a.offset, a.end) <
std::make_pair(b.offset, b.end);
});
}
}
}
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
// Relax R_RISCV_CALL/R_RISCV_CALL_PLT auipc+jalr to c.j, c.jal, or jal.
static void relaxCall(const InputSection &sec, size_t i, uint64_t loc,
Relocation &r, uint32_t &remove) {
const bool rvc = config->eflags & EF_RISCV_RVC;
const Symbol &sym = *r.sym;
[ELF] Change rawData to content() and data() to contentMaybeDecompress() Clarify data() which may trigger decompression and make it feasible to refactor the member variable rawData.
2022-11-20 22:43:22 +00:00
const uint64_t insnPair = read64le(sec.content().data() + r.offset);
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
const uint32_t rd = extractBits(insnPair, 32 + 11, 32 + 7);
const uint64_t dest =
(r.expr == R_PLT_PC ? sym.getPltVA() : sym.getVA()) + r.addend;
const int64_t displace = dest - loc;
if (rvc && isInt<12>(displace) && rd == 0) {
sec.relaxAux->relocTypes[i] = R_RISCV_RVC_JUMP;
sec.relaxAux->writes.push_back(0xa001); // c.j
remove = 6;
} else if (rvc && isInt<12>(displace) && rd == X_RA &&
!config->is64) { // RV32C only
sec.relaxAux->relocTypes[i] = R_RISCV_RVC_JUMP;
sec.relaxAux->writes.push_back(0x2001); // c.jal
remove = 6;
} else if (isInt<21>(displace)) {
sec.relaxAux->relocTypes[i] = R_RISCV_JAL;
sec.relaxAux->writes.push_back(0x6f | rd << 7); // jal
remove = 4;
}
}
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
// Relax local-exec TLS when hi20 is zero.
static void relaxTlsLe(const InputSection &sec, size_t i, uint64_t loc,
Relocation &r, uint32_t &remove) {
uint64_t val = r.sym->getVA(r.addend);
if (hi20(val) != 0)
return;
[ELF] Change rawData to content() and data() to contentMaybeDecompress() Clarify data() which may trigger decompression and make it feasible to refactor the member variable rawData.
2022-11-20 22:43:22 +00:00
uint32_t insn = read32le(sec.content().data() + r.offset);
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
switch (r.type) {
case R_RISCV_TPREL_HI20:
case R_RISCV_TPREL_ADD:
// Remove lui rd, %tprel_hi(x) and add rd, rd, tp, %tprel_add(x).
sec.relaxAux->relocTypes[i] = R_RISCV_RELAX;
remove = 4;
break;
case R_RISCV_TPREL_LO12_I:
// addi rd, rd, %tprel_lo(x) => addi rd, tp, st_value(x)
sec.relaxAux->relocTypes[i] = R_RISCV_32;
insn = (insn & ~(31 << 15)) | (X_TP << 15);
sec.relaxAux->writes.push_back(setLO12_I(insn, val));
break;
case R_RISCV_TPREL_LO12_S:
// sw rs, %tprel_lo(x)(rd) => sw rs, st_value(x)(rd)
sec.relaxAux->relocTypes[i] = R_RISCV_32;
insn = (insn & ~(31 << 15)) | (X_TP << 15);
sec.relaxAux->writes.push_back(setLO12_S(insn, val));
break;
}
}
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
static bool relax(InputSection &sec) {
const uint64_t secAddr = sec.getVA();
auto &aux = *sec.relaxAux;
bool changed = false;
[ELF] Fix displacement computation for intra-section branch after D127611 D127611 computed st_value is inaccurate: * For a backward branch, the destination address may be wrong if there is no relaxable relocation between it and the current location due to `if (remove)`. We may incorrectly relax a branch to c.j which ends up an overflow. * For a forward branch, the destination address may be overestimated and lose relaxation opportunities. To fix the issues, * Don't reset st_value to the original value. * Save the st_value delta from the previous iteration into valueDelta, and use `sa[0].d->value -= delta - valueDelta.find(sa[0].d)->second`.
2022-07-13 00:17:17 -07:00
// Get st_value delta for symbols relative to this section from the previous
// iteration.
DenseMap<const Defined *, uint64_t> valueDelta;
Move from llvm::makeArrayRef to ArrayRef deduction guides - last part This is a follow-up to https://reviews.llvm.org/D140896, split into several parts as it touches a lot of files. Differential Revision: https://reviews.llvm.org/D141298
2023-01-09 18:11:07 +01:00
ArrayRef<SymbolAnchor> sa = ArrayRef(aux.anchors);
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
uint32_t delta = 0;
[ELF] Add InputSectionBase::{addRelocs,relocs} and GotSection::addConstant to add/access relocations to prepare for changing `relocations` from a SmallVector to a pointer. Also change the `isec` parameter in `addAddendOnlyRelocIfNonPreemptible` to `GotSection &`.
2022-11-21 04:12:03 +00:00
for (auto [i, r] : llvm::enumerate(sec.relocs())) {
[ELF] Simplify llvm::enumerate with structured binding. NFC
2022-08-09 21:52:08 -07:00
for (; sa.size() && sa[0].offset <= r.offset; sa = sa.slice(1))
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
if (!sa[0].end)
[ELF] Fix displacement computation for intra-section branch after D127611 D127611 computed st_value is inaccurate: * For a backward branch, the destination address may be wrong if there is no relaxable relocation between it and the current location due to `if (remove)`. We may incorrectly relax a branch to c.j which ends up an overflow. * For a forward branch, the destination address may be overestimated and lose relaxation opportunities. To fix the issues, * Don't reset st_value to the original value. * Save the st_value delta from the previous iteration into valueDelta, and use `sa[0].d->value -= delta - valueDelta.find(sa[0].d)->second`.
2022-07-13 00:17:17 -07:00
valueDelta[sa[0].d] = delta;
[ELF] Simplify llvm::enumerate with structured binding. NFC
2022-08-09 21:52:08 -07:00
delta = aux.relocDeltas[i];
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
}
for (const SymbolAnchor &sa : sa)
if (!sa.end)
[ELF] Fix displacement computation for intra-section branch after D127611 D127611 computed st_value is inaccurate: * For a backward branch, the destination address may be wrong if there is no relaxable relocation between it and the current location due to `if (remove)`. We may incorrectly relax a branch to c.j which ends up an overflow. * For a forward branch, the destination address may be overestimated and lose relaxation opportunities. To fix the issues, * Don't reset st_value to the original value. * Save the st_value delta from the previous iteration into valueDelta, and use `sa[0].d->value -= delta - valueDelta.find(sa[0].d)->second`.
2022-07-13 00:17:17 -07:00
valueDelta[sa.d] = delta;
Move from llvm::makeArrayRef to ArrayRef deduction guides - last part This is a follow-up to https://reviews.llvm.org/D140896, split into several parts as it touches a lot of files. Differential Revision: https://reviews.llvm.org/D141298
2023-01-09 18:11:07 +01:00
sa = ArrayRef(aux.anchors);
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
delta = 0;
[ELF] Add InputSectionBase::{addRelocs,relocs} and GotSection::addConstant to add/access relocations to prepare for changing `relocations` from a SmallVector to a pointer. Also change the `isec` parameter in `addAddendOnlyRelocIfNonPreemptible` to `GotSection &`.
2022-11-21 04:12:03 +00:00
std::fill_n(aux.relocTypes.get(), sec.relocs().size(), R_RISCV_NONE);
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
aux.writes.clear();
[ELF] Add InputSectionBase::{addRelocs,relocs} and GotSection::addConstant to add/access relocations to prepare for changing `relocations` from a SmallVector to a pointer. Also change the `isec` parameter in `addAddendOnlyRelocIfNonPreemptible` to `GotSection &`.
2022-11-21 04:12:03 +00:00
for (auto [i, r] : llvm::enumerate(sec.relocs())) {
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
const uint64_t loc = secAddr + r.offset - delta;
uint32_t &cur = aux.relocDeltas[i], remove = 0;
switch (r.type) {
case R_RISCV_ALIGN: {
const uint64_t nextLoc = loc + r.addend;
const uint64_t align = PowerOf2Ceil(r.addend + 2);
// All bytes beyond the alignment boundary should be removed.
remove = nextLoc - ((loc + align - 1) & -align);
assert(static_cast<int32_t>(remove) >= 0 &&
"R_RISCV_ALIGN needs expanding the content");
break;
}
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
case R_RISCV_CALL:
case R_RISCV_CALL_PLT:
[ELF] Add InputSectionBase::{addRelocs,relocs} and GotSection::addConstant to add/access relocations to prepare for changing `relocations` from a SmallVector to a pointer. Also change the `isec` parameter in `addAddendOnlyRelocIfNonPreemptible` to `GotSection &`.
2022-11-21 04:12:03 +00:00
if (i + 1 != sec.relocs().size() &&
sec.relocs()[i + 1].type == R_RISCV_RELAX)
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
relaxCall(sec, i, loc, r, remove);
break;
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
case R_RISCV_TPREL_HI20:
case R_RISCV_TPREL_ADD:
case R_RISCV_TPREL_LO12_I:
case R_RISCV_TPREL_LO12_S:
[ELF] Add InputSectionBase::{addRelocs,relocs} and GotSection::addConstant to add/access relocations to prepare for changing `relocations` from a SmallVector to a pointer. Also change the `isec` parameter in `addAddendOnlyRelocIfNonPreemptible` to `GotSection &`.
2022-11-21 04:12:03 +00:00
if (i + 1 != sec.relocs().size() &&
sec.relocs()[i + 1].type == R_RISCV_RELAX)
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
relaxTlsLe(sec, i, loc, r, remove);
break;
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
}
// For all anchors whose offsets are <= r.offset, they are preceded by
// the previous relocation whose `relocDeltas` value equals `delta`.
// Decrease their st_value and update their st_size.
[ELF] Fix displacement computation for intra-section branch after D127611 D127611 computed st_value is inaccurate: * For a backward branch, the destination address may be wrong if there is no relaxable relocation between it and the current location due to `if (remove)`. We may incorrectly relax a branch to c.j which ends up an overflow. * For a forward branch, the destination address may be overestimated and lose relaxation opportunities. To fix the issues, * Don't reset st_value to the original value. * Save the st_value delta from the previous iteration into valueDelta, and use `sa[0].d->value -= delta - valueDelta.find(sa[0].d)->second`.
2022-07-13 00:17:17 -07:00
for (; sa.size() && sa[0].offset <= r.offset; sa = sa.slice(1)) {
if (sa[0].end)
sa[0].d->size = sa[0].offset - delta - sa[0].d->value;
else
sa[0].d->value -= delta - valueDelta.find(sa[0].d)->second;
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
}
delta += remove;
if (delta != cur) {
cur = delta;
changed = true;
}
}
for (const SymbolAnchor &a : sa) {
if (a.end)
a.d->size = a.offset - delta - a.d->value;
else
[ELF] Fix displacement computation for intra-section branch after D127611 D127611 computed st_value is inaccurate: * For a backward branch, the destination address may be wrong if there is no relaxable relocation between it and the current location due to `if (remove)`. We may incorrectly relax a branch to c.j which ends up an overflow. * For a forward branch, the destination address may be overestimated and lose relaxation opportunities. To fix the issues, * Don't reset st_value to the original value. * Save the st_value delta from the previous iteration into valueDelta, and use `sa[0].d->value -= delta - valueDelta.find(sa[0].d)->second`.
2022-07-13 00:17:17 -07:00
a.d->value -= delta - valueDelta.find(a.d)->second;
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
}
// Inform assignAddresses that the size has changed.
if (!isUInt<16>(delta))
fatal("section size decrease is too large");
sec.bytesDropped = delta;
return changed;
}
// When relaxing just R_RISCV_ALIGN, relocDeltas is usually changed only once in
// the absence of a linker script. For call and load/store R_RISCV_RELAX, code
// shrinkage may reduce displacement and make more relocations eligible for
// relaxation. Code shrinkage may increase displacement to a call/load/store
// target at a higher fixed address, invalidating an earlier relaxation. Any
// change in section sizes can have cascading effect and require another
// relaxation pass.
bool RISCV::relaxOnce(int pass) const {
llvm::TimeTraceScope timeScope("RISC-V relaxOnce");
if (config->relocatable)
return false;
if (pass == 0)
initSymbolAnchors();
SmallVector<InputSection *, 0> storage;
bool changed = false;
for (OutputSection *osec : outputSections) {
if (!(osec->flags & SHF_EXECINSTR))
continue;
for (InputSection *sec : getInputSections(*osec, storage))
changed |= relax(*sec);
}
return changed;
}
void elf::riscvFinalizeRelax(int passes) {
llvm::TimeTraceScope timeScope("Finalize RISC-V relaxation");
log("relaxation passes: " + Twine(passes));
SmallVector<InputSection *, 0> storage;
for (OutputSection *osec : outputSections) {
if (!(osec->flags & SHF_EXECINSTR))
continue;
for (InputSection *sec : getInputSections(*osec, storage)) {
RISCVRelaxAux &aux = *sec->relaxAux;
if (!aux.relocDeltas)
continue;
[ELF] Add InputSectionBase::{addRelocs,relocs} and GotSection::addConstant to add/access relocations to prepare for changing `relocations` from a SmallVector to a pointer. Also change the `isec` parameter in `addAddendOnlyRelocIfNonPreemptible` to `GotSection &`.
2022-11-21 04:12:03 +00:00
MutableArrayRef<Relocation> rels = sec->relocs();
[ELF] Change rawData to content() and data() to contentMaybeDecompress() Clarify data() which may trigger decompression and make it feasible to refactor the member variable rawData.
2022-11-20 22:43:22 +00:00
ArrayRef<uint8_t> old = sec->content();
[ELF] Add InputSectionBase::{addRelocs,relocs} and GotSection::addConstant to add/access relocations to prepare for changing `relocations` from a SmallVector to a pointer. Also change the `isec` parameter in `addAddendOnlyRelocIfNonPreemptible` to `GotSection &`.
2022-11-21 04:12:03 +00:00
size_t newSize = old.size() - aux.relocDeltas[rels.size() - 1];
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
size_t writesIdx = 0;
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
uint8_t *p = context().bAlloc.Allocate<uint8_t>(newSize);
uint64_t offset = 0;
int64_t delta = 0;
[ELF] Replace rawData+size with content_+size+compressedSize compressedSize resides in an existing union. sizeof(InputSection) decreases from 160 to 152 on ELF64 systems.
2022-11-20 23:22:32 +00:00
sec->content_ = p;
sec->size = newSize;
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
sec->bytesDropped = 0;
// Update section content: remove NOPs for R_RISCV_ALIGN and rewrite
// instructions for relaxed relocations.
for (size_t i = 0, e = rels.size(); i != e; ++i) {
uint32_t remove = aux.relocDeltas[i] - delta;
delta = aux.relocDeltas[i];
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
if (remove == 0 && aux.relocTypes[i] == R_RISCV_NONE)
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
continue;
// Copy from last location to the current relocated location.
const Relocation &r = rels[i];
uint64_t size = r.offset - offset;
memcpy(p, old.data() + offset, size);
p += size;
// For R_RISCV_ALIGN, we will place `offset` in a location (among NOPs)
[ELF] Rewrite R_RISCV_ALIGN nops when r.addend%4 != 0 For RVC, GNU assembler and LLVM integrated assembler add c.nop followed by a sequence of 4-byte nops. Even if remove % 4 == 0, we have to split one 4-byte nop and therefore need to write the code sequence, otherwise we create an incorrect c.unimp.
2022-09-26 14:20:27 -07:00
// to satisfy the alignment requirement. If both `remove` and r.addend
// are multiples of 4, it is as if we have skipped some NOPs. Otherwise
// we are in the middle of a 4-byte NOP, and we need to rewrite the NOP
// sequence.
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
int64_t skip = 0;
if (r.type == R_RISCV_ALIGN) {
[ELF] Rewrite R_RISCV_ALIGN nops when r.addend%4 != 0 For RVC, GNU assembler and LLVM integrated assembler add c.nop followed by a sequence of 4-byte nops. Even if remove % 4 == 0, we have to split one 4-byte nop and therefore need to write the code sequence, otherwise we create an incorrect c.unimp.
2022-09-26 14:20:27 -07:00
if (remove % 4 || r.addend % 4) {
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
skip = r.addend - remove;
int64_t j = 0;
for (; j + 4 <= skip; j += 4)
write32le(p + j, 0x00000013); // nop
if (j != skip) {
assert(j + 2 == skip);
write16le(p + j, 0x0001); // c.nop
}
}
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
} else if (RelType newType = aux.relocTypes[i]) {
switch (newType) {
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
case R_RISCV_RELAX:
// Used by relaxTlsLe to indicate the relocation is ignored.
break;
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
case R_RISCV_RVC_JUMP:
skip = 2;
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
write16le(p, aux.writes[writesIdx++]);
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
break;
case R_RISCV_JAL:
skip = 4;
[ELF][RISCV] Relax local-exec TLS model In -mrelax mode, GCC/Clang may generate a local-exec TLS code sequence like: ``` # R_RISCV_TPREL_HI20, R_RISCV_RELAX lui rd, %tprel_hi(x) # R_RISCV_TPREL_ADD, R_RISCV_RELAX add rd, rd, tp, %tprel_add(x) # (R_RISCV_TPREL_LO12_I || R_RISCV_TPREL_LO12_S), R_RISCV_RELAX addi rd, rd, %tprel_lo(x) || sw rs, %tprel(x)(rd) ``` Note: st_value(x) for TLS should be in the range [0,p_memsz(PT_TLS)). When st_value(x) < 2048 (i.e. hi20(x) == 0), the linker can relax the code sequence to: ``` addi rd, tp, st_value(x) || sw rs, st_value(x)(rd) ``` Differential Revision: https://reviews.llvm.org/D129425
2022-07-15 10:08:08 -07:00
write32le(p, aux.writes[writesIdx++]);
break;
case R_RISCV_32:
// Used by relaxTlsLe to write a uint32_t then suppress the handling
// in relocateAlloc.
skip = 4;
write32le(p, aux.writes[writesIdx++]);
aux.relocTypes[i] = R_RISCV_NONE;
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
break;
default:
llvm_unreachable("unsupported type");
}
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
}
p += skip;
offset = r.offset + skip + remove;
}
memcpy(p, old.data() + offset, old.size() - offset);
fix comment typo to cycle bots
2022-07-09 22:41:58 +02:00
// Subtract the previous relocDeltas value from the relocation offset.
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
// For a pair of R_RISCV_CALL/R_RISCV_RELAX with the same offset, decrease
// their r_offset by the same delta.
delta = 0;
for (size_t i = 0, e = rels.size(); i != e;) {
uint64_t cur = rels[i].offset;
do {
rels[i].offset -= delta;
[ELF] Relax R_RISCV_CALL and R_RISCV_CALL_PLT A pair of auipc+jalr relocated by R_RISCV_CALL or R_RISCV_CALL_PLT can be converted to c.j, c.jal, or jal. * c.j: RVC and displacement is representable as an int12 * c.jal: RV32C and displacement is representable as an int12 * jal: displacement is representable as an int21 Use the D127581 relaxation framework to implement the relaxation. If a shorter sequence is satisfied, we record the new relocation type in `relocTypes` and saves the new instruction into `writes`. Finally let `riscvFinalizeRelax` rewrite the instruction by setting `skip`. Differential Revision: https://reviews.llvm.org/D127611
2022-07-07 10:18:45 -07:00
if (aux.relocTypes[i] != R_RISCV_NONE)
rels[i].type = aux.relocTypes[i];
[ELF] Relax R_RISCV_ALIGN Alternative to D125036. Implement R_RISCV_ALIGN relaxation so that we can handle -mrelax object files (i.e. -mno-relax is no longer needed) and creates a framework for future relaxation. `relaxAux` is placed in a union with InputSectionBase::jumpInstrMod, storing auxiliary information for relaxation. In the first pass, `relaxAux` is allocated. The main data structure is `relocDeltas`: when referencing `relocations[i]`, the actual offset is `r_offset - (i ? relocDeltas[i-1] : 0)`. `relaxOnce` performs one relaxation pass. It computes `relocDeltas` for all text section. Then, adjust st_value/st_size for symbols relative to this section based on `SymbolAnchor`. `bytesDropped` is set so that `assignAddresses` knows that the size has changed. Run `relaxOnce` in the `finalizeAddressDependentContent` loop to wait for convergence of text sections and other address dependent sections (e.g. SHT_RELR). Note: extrating `relaxOnce` into a separate loop works for many cases but has issues in some linker script edge cases. After convergence, compute section contents: shrink the NOP sequence of each R_RISCV_ALIGN as appropriate. Instead of deleting bytes, we run a sequence of memcpy on the content delimitered by relocation locations. For R_RISCV_ALIGN let the next memcpy skip the desired number of bytes. Section content computation is parallelizable, but let's ensure the implementation is mature before optimizations. Technically we can save a copy if we interleave some code with `OutputSection::writeTo`, but let's not pollute the generic code (we don't have templated relocation resolving, so using conditions can impose overhead to non-RISCV.) Tested: `make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- LLVM=1 defconfig all` built Linux kernel using -mrelax is bootable. FreeBSD RISCV64 system using -mrelax is bootable. bash/curl/firefox/libevent/vim/tmux using -mrelax works. Differential Revision: https://reviews.llvm.org/D127581
2022-07-07 10:16:09 -07:00
} while (++i != e && rels[i].offset == cur);
delta = aux.relocDeltas[i - 1];
}
}
}
}
[ELF] Merge SHT_RISCV_ATTRIBUTES sections Currently we take the first SHT_RISCV_ATTRIBUTES (.riscv.attributes) as the output. If we link an object without an extension with an object with the extension, the output Tag_RISCV_arch may not contain the extension and some tools like objdump -d will not decode the related instructions. This patch implements Tag_RISCV_stack_align/Tag_RISCV_arch/Tag_RISCV_unaligned_access merge as specified by https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#attributes For the deprecated Tag_RISCV_priv_spec{,_minor,_revision}, dump the attribute to the output iff all input agree on the value. This is different from GNU ld but our simple approach should be ok for deprecated tags. `RISCVAttributeParser::handler` currently warns about unknown tags. This behavior is retained. In GNU ld arm, tags >= 64 (mod 128) are ignored with a warning. If RISC-V ever wants to do something similar (https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/352), consider documenting it in the psABI and changing RISCVAttributeParser. Like GNU ld, zero value integer attributes and empty string attributes are not dumped to the output. Reviewed By: asb, kito-cheng Differential Revision: https://reviews.llvm.org/D138550
2022-12-08 09:53:40 +00:00
namespace {
// Representation of the merged .riscv.attributes input sections. The psABI
// specifies merge policy for attributes. E.g. if we link an object without an
// extension with an object with the extension, the output Tag_RISCV_arch shall
// contain the extension. Some tools like objdump parse .riscv.attributes and
// disabling some instructions if the first Tag_RISCV_arch does not contain an
// extension.
class RISCVAttributesSection final : public SyntheticSection {
public:
RISCVAttributesSection()
: SyntheticSection(0, SHT_RISCV_ATTRIBUTES, 1, ".riscv.attributes") {}
size_t getSize() const override { return size; }
void writeTo(uint8_t *buf) override;
static constexpr StringRef vendor = "riscv";
DenseMap<unsigned, unsigned> intAttr;
DenseMap<unsigned, StringRef> strAttr;
size_t size = 0;
};
} // namespace
static void mergeArch(RISCVISAInfo::OrderedExtensionMap &mergedExts,
unsigned &mergedXlen, const InputSectionBase *sec,
StringRef s) {
auto maybeInfo =
RISCVISAInfo::parseArchString(s, /*EnableExperimentalExtension=*/true,
/*ExperimentalExtensionVersionCheck=*/true);
if (!maybeInfo) {
errorOrWarn(toString(sec) + ": " + s + ": " +
llvm::toString(maybeInfo.takeError()));
return;
}
// Merge extensions.
RISCVISAInfo &info = **maybeInfo;
if (mergedExts.empty()) {
mergedExts = info.getExtensions();
mergedXlen = info.getXLen();
} else {
for (const auto &ext : info.getExtensions()) {
if (auto it = mergedExts.find(ext.first); it != mergedExts.end()) {
// TODO This is untested because RISCVISAInfo::parseArchString does not
// accept unsupported versions yet.
if (std::tie(it->second.MajorVersion, it->second.MinorVersion) >=
std::tie(ext.second.MajorVersion, ext.second.MinorVersion))
continue;
}
mergedExts[ext.first] = ext.second;
}
}
}
static RISCVAttributesSection *
mergeAttributesSection(const SmallVector<InputSectionBase *, 0> &sections) {
RISCVISAInfo::OrderedExtensionMap exts;
const InputSectionBase *firstStackAlign = nullptr;
unsigned firstStackAlignValue = 0, xlen = 0;
bool hasArch = false;
in.riscvAttributes = std::make_unique<RISCVAttributesSection>();
auto &merged = static_cast<RISCVAttributesSection &>(*in.riscvAttributes);
// Collect all tags values from attributes section.
const auto &attributesTags = RISCVAttrs::getRISCVAttributeTags();
for (const InputSectionBase *sec : sections) {
RISCVAttributeParser parser;
if (Error e = parser.parse(sec->content(), support::little))
warn(toString(sec) + ": " + llvm::toString(std::move(e)));
for (const auto &tag : attributesTags) {
switch (RISCVAttrs::AttrType(tag.attr)) {
// Integer attributes.
case RISCVAttrs::STACK_ALIGN:
if (auto i = parser.getAttributeValue(tag.attr)) {
auto r = merged.intAttr.try_emplace(tag.attr, *i);
if (r.second) {
firstStackAlign = sec;
firstStackAlignValue = *i;
} else if (r.first->second != *i) {
errorOrWarn(toString(sec) + " has stack_align=" + Twine(*i) +
" but " + toString(firstStackAlign) +
" has stack_align=" + Twine(firstStackAlignValue));
}
}
continue;
case RISCVAttrs::UNALIGNED_ACCESS:
if (auto i = parser.getAttributeValue(tag.attr))
merged.intAttr[tag.attr] |= *i;
continue;
// String attributes.
case RISCVAttrs::ARCH:
if (auto s = parser.getAttributeString(tag.attr)) {
hasArch = true;
mergeArch(exts, xlen, sec, *s);
}
continue;
// Attributes which use the default handling.
case RISCVAttrs::PRIV_SPEC:
case RISCVAttrs::PRIV_SPEC_MINOR:
case RISCVAttrs::PRIV_SPEC_REVISION:
break;
}
// Fallback for deprecated priv_spec* and other unknown attributes: retain
// the attribute if all input sections agree on the value. GNU ld uses 0
// and empty strings as default values which are not dumped to the output.
// TODO Adjust after resolution to
// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/352
if (tag.attr % 2 == 0) {
if (auto i = parser.getAttributeValue(tag.attr)) {
auto r = merged.intAttr.try_emplace(tag.attr, *i);
if (!r.second && r.first->second != *i)
r.first->second = 0;
}
} else if (auto s = parser.getAttributeString(tag.attr)) {
auto r = merged.strAttr.try_emplace(tag.attr, *s);
if (!r.second && r.first->second != *s)
r.first->second = {};
}
}
}
if (hasArch) {
if (auto result = RISCVISAInfo::postProcessAndChecking(
std::make_unique<RISCVISAInfo>(xlen, exts))) {
merged.strAttr.try_emplace(RISCVAttrs::ARCH,
saver().save((*result)->toString()));
} else {
errorOrWarn(llvm::toString(result.takeError()));
}
}
// The total size of headers: format-version [ <section-length> "vendor-name"
// [ <file-tag> <size>.
size_t size = 5 + merged.vendor.size() + 1 + 5;
for (auto &attr : merged.intAttr)
if (attr.second != 0)
size += getULEB128Size(attr.first) + getULEB128Size(attr.second);
for (auto &attr : merged.strAttr)
if (!attr.second.empty())
size += getULEB128Size(attr.first) + attr.second.size() + 1;
merged.size = size;
return &merged;
}
void RISCVAttributesSection::writeTo(uint8_t *buf) {
const size_t size = getSize();
uint8_t *const end = buf + size;
*buf = ELFAttrs::Format_Version;
write32(buf + 1, size - 1);
buf += 5;
memcpy(buf, vendor.data(), vendor.size());
buf += vendor.size() + 1;
*buf = ELFAttrs::File;
write32(buf + 1, end - buf);
buf += 5;
for (auto &attr : intAttr) {
if (attr.second == 0)
continue;
buf += encodeULEB128(attr.first, buf);
buf += encodeULEB128(attr.second, buf);
}
for (auto &attr : strAttr) {
if (attr.second.empty())
continue;
buf += encodeULEB128(attr.first, buf);
memcpy(buf, attr.second.data(), attr.second.size());
buf += attr.second.size() + 1;
}
}
void elf::mergeRISCVAttributesSections() {
// Find the first input SHT_RISCV_ATTRIBUTES; return if not found.
size_t place =
llvm::find_if(ctx.inputSections,
[](auto *s) { return s->type == SHT_RISCV_ATTRIBUTES; }) -
ctx.inputSections.begin();
if (place == ctx.inputSections.size())
return;
// Extract all SHT_RISCV_ATTRIBUTES sections into `sections`.
SmallVector<InputSectionBase *, 0> sections;
llvm::erase_if(ctx.inputSections, [&](InputSectionBase *s) {
if (s->type != SHT_RISCV_ATTRIBUTES)
return false;
sections.push_back(s);
return true;
});
// Add the merged section.
ctx.inputSections.insert(ctx.inputSections.begin() + place,
mergeAttributesSection(sections));
}
[ELF] Use namespace qualifiers (lld:: or elf::) instead of `namespace lld { namespace elf {` Similar to D74882. This reverts much code from commit bd8cfe65f5fee4ad573adc2172359c9552e8cdc0 (D68323) and fixes some problems before D68323. Sorry for the churn but D68323 was a mistake. Namespace qualifiers avoid bugs where the definition does not match the declaration from the header. See https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implement-previously-declared-functions (D74515) Differential Revision: https://reviews.llvm.org/D79982
2020-05-14 22:18:58 -07:00
TargetInfo *elf::getRISCVTargetInfo() {
Support RISC-V Patch by PkmX. This patch makes lld recognize RISC-V target and implements basic relocation for RV32/RV64 (and RVC). This should be necessary for static linking ELF applications. The ABI documentation for RISC-V can be found at: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md. Note that the documentation is far from complete so we had to figure out some details from bfd. The patch should be pretty straightforward. Some highlights: - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as the low part of a PC-relative relocation is linked to the corresponding high part (auipc), see: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses - LLVM's MC support for RISC-V is very incomplete (we are working on this), so tests are given in objectyaml format with the original assembly included in the comments. Once we have complete support for RISC-V in MC, we can switch to llvm-as/llvm-objdump. - We don't support linker relaxation for now as it requires greater changes to lld that is beyond the scope of this patch. Once this is accepted we can start to work on adding relaxation to lld. Differential Revision: https://reviews.llvm.org/D39322 llvm-svn: 339364
2018-08-09 17:59:56 +00:00
static RISCV target;
return &target;
}
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