llvm-project/llvm/docs/AMDGPU/gfx1030_vdata_84fab6.rst

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    *   Automatically generated file, do not edit!   *
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.. _amdgpu_synid_gfx1030_vdata_84fab6:

vdata
=====

Input data for an atomic instruction.

Optionally, this operand may be used to store output data:

* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.

*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:

* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.


  Note: the surface data format is indicated in the image resource constant, but not in the instruction.

*Operands:* :ref:`v<amdgpu_synid_v>`
[AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description 2022-03-25 17:52:13 +03:00			`..`
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			`* Automatically generated file, do not edit! *`
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[AMDGPU][GFX1030][DOC][NFC] Update assembler syntax description Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900). - Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements. 2022-12-13 14:48:36 +03:00			`.. _amdgpu_synid_gfx1030_vdata_84fab6:`
[AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description 2022-03-25 17:52:13 +03:00
			`vdata`
			`=====`

			`Input data for an atomic instruction.`

[AMDGPU][GFX1030][DOC][NFC] Update assembler syntax description Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900). - Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements. 2022-12-13 14:48:36 +03:00			`Optionally, this operand may be used to store output data:`
[AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description 2022-03-25 17:52:13 +03:00
			* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.

[AMDGPU][GFX1030][DOC][NFC] Update assembler syntax description Summary of changes: - Update MUBUF lds syntax (see https://reviews.llvm.org/D124485). - Add v_cvt_pkrtz_f16_f32_dpp, v_cvt_pkrtz_f16_f32_sdwa. - Update SMEM syntax (see https://reviews.llvm.org/D127314). - Enable op_sel for v_add_nc_u16, v_sub_nc_u16 (see https://reviews.llvm.org/D123594). - Minor bug fixing and improvements. 2022-06-27 19:55:07 +03:00			Size: depends on :ref:`dmask<amdgpu_synid_dmask>`:
[AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description 2022-03-25 17:52:13 +03:00
			* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
[AMDGPU][GFX1030][DOC][NFC] Update assembler syntax description Summary of changes: - Update MUBUF lds syntax (see https://reviews.llvm.org/D124485). - Add v_cvt_pkrtz_f16_f32_dpp, v_cvt_pkrtz_f16_f32_sdwa. - Update SMEM syntax (see https://reviews.llvm.org/D127314). - Enable op_sel for v_add_nc_u16, v_sub_nc_u16 (see https://reviews.llvm.org/D123594). - Minor bug fixing and improvements. 2022-06-27 19:55:07 +03:00
[AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description 2022-03-25 17:52:13 +03:00
[AMDGPU][GFX1030][DOC][NFC] Update assembler syntax description Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900). - Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements. 2022-12-13 14:48:36 +03:00			`Note: the surface data format is indicated in the image resource constant, but not in the instruction.`
[AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description 2022-03-25 17:52:13 +03:00
			Operands: :ref:`v<amdgpu_synid_v>`