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llvm-project/llvm/test/CodeGen/WebAssembly/load-ext.ll

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[WebAssembly] Remove unused FileCheck test prefixes This commit removes unused FileCheck prefixes from WebAssembly test files to avoid causing test failures once FileCheck disallows unused prefixes by default. See D90281 and the corresponding llvm-dev thread for context. Reviewed By: aardappel Differential Revision: https://reviews.llvm.org/D90416
2020-10-29 13:37:55 -07:00
; RUN: llc < %s --mtriple=wasm32-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; RUN: llc < %s --mtriple=wasm64-unknown-unknown -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
; Test that extending loads are assembled properly.
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 00:27:55 +00:00
; CHECK-LABEL: sext_i8_i32:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 00:26:39 +00:00
; CHECK: i32.load8_s $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-25 16:55:01 +00:00
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Convert some tests to opaque pointers (NFC)
2022-12-19 13:07:12 +01:00
define i32 @sext_i8_i32(ptr %p) {
%v = load i8, ptr %p
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
%e = sext i8 %v to i32
ret i32 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 00:27:55 +00:00
; CHECK-LABEL: zext_i8_i32:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 00:26:39 +00:00
; CHECK: i32.load8_u $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-25 16:55:01 +00:00
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Convert some tests to opaque pointers (NFC)
2022-12-19 13:07:12 +01:00
define i32 @zext_i8_i32(ptr %p) {
%v = load i8, ptr %p
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
%e = zext i8 %v to i32
ret i32 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 00:27:55 +00:00
; CHECK-LABEL: sext_i16_i32:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 00:26:39 +00:00
; CHECK: i32.load16_s $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-25 16:55:01 +00:00
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Convert some tests to opaque pointers (NFC)
2022-12-19 13:07:12 +01:00
define i32 @sext_i16_i32(ptr %p) {
%v = load i16, ptr %p
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
%e = sext i16 %v to i32
ret i32 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 00:27:55 +00:00
; CHECK-LABEL: zext_i16_i32:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 00:26:39 +00:00
; CHECK: i32.load16_u $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-25 16:55:01 +00:00
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Convert some tests to opaque pointers (NFC)
2022-12-19 13:07:12 +01:00
define i32 @zext_i16_i32(ptr %p) {
%v = load i16, ptr %p
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
%e = zext i16 %v to i32
ret i32 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 00:27:55 +00:00
; CHECK-LABEL: sext_i8_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 00:26:39 +00:00
; CHECK: i64.load8_s $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-25 16:55:01 +00:00
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Convert some tests to opaque pointers (NFC)
2022-12-19 13:07:12 +01:00
define i64 @sext_i8_i64(ptr %p) {
%v = load i8, ptr %p
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
%e = sext i8 %v to i64
ret i64 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 00:27:55 +00:00
; CHECK-LABEL: zext_i8_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 00:26:39 +00:00
; CHECK: i64.load8_u $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-25 16:55:01 +00:00
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Convert some tests to opaque pointers (NFC)
2022-12-19 13:07:12 +01:00
define i64 @zext_i8_i64(ptr %p) {
%v = load i8, ptr %p
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
%e = zext i8 %v to i64
ret i64 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 00:27:55 +00:00
; CHECK-LABEL: sext_i16_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 00:26:39 +00:00
; CHECK: i64.load16_s $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-25 16:55:01 +00:00
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Convert some tests to opaque pointers (NFC)
2022-12-19 13:07:12 +01:00
define i64 @sext_i16_i64(ptr %p) {
%v = load i16, ptr %p
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
%e = sext i16 %v to i64
ret i64 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 00:27:55 +00:00
; CHECK-LABEL: zext_i16_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 00:26:39 +00:00
; CHECK: i64.load16_u $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-25 16:55:01 +00:00
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Convert some tests to opaque pointers (NFC)
2022-12-19 13:07:12 +01:00
define i64 @zext_i16_i64(ptr %p) {
%v = load i16, ptr %p
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
%e = zext i16 %v to i64
ret i64 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 00:27:55 +00:00
; CHECK-LABEL: sext_i32_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 00:26:39 +00:00
; CHECK: i64.load32_s $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-25 16:55:01 +00:00
; CHECK-NEXT: return $pop0{{$}}
[WebAssembly] Convert some tests to opaque pointers (NFC)
2022-12-19 13:07:12 +01:00
define i64 @sext_i32_i64(ptr %p) {
%v = load i32, ptr %p
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
%e = sext i32 %v to i64
ret i64 %e
}
[WebAssembly] Switch to a more traditional assembly syntax This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
2015-10-06 00:27:55 +00:00
; CHECK-LABEL: zext_i32_i64:
[WebAssembly] Support constant offsets on loads and stores This is just prototype for load/store for i32 types. I'll add them to the rest of the types if we like this direction. Differential Revision: http://reviews.llvm.org/D15197 llvm-svn: 254807
2015-12-05 00:26:39 +00:00
; CHECK: i64.load32_u $push0=, 0($0){{$}}
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-25 16:55:01 +00:00
; CHECK: return $pop0{{$}}
[WebAssembly] Convert some tests to opaque pointers (NFC)
2022-12-19 13:07:12 +01:00
define i64 @zext_i32_i64(ptr %p) {
%v = load i32, ptr %p
WebAssembly: generate load/store Summary: This handles all load/store operations that WebAssembly defines, and handles those necessary for C++ such as i1. I left a FIXME for outstanding features which aren't required for now. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff llvm-svn: 246500
2015-08-31 22:24:11 +00:00
%e = zext i32 %v to i64
ret i64 %e
}
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