2019-01-16 00:40:37 +00:00
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//===-- llvm/CodeGen/GlobalISel/CSEMIRBuilder.cpp - MIBuilder--*- C++ -*-==//
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//
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2019-01-19 08:50:56 +00:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2019-01-16 00:40:37 +00:00
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the CSEMIRBuilder class which CSEs as it builds
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/// instructions.
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//===----------------------------------------------------------------------===//
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//
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#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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using namespace llvm;
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bool CSEMIRBuilder::dominates(MachineBasicBlock::const_iterator A,
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MachineBasicBlock::const_iterator B) const {
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auto MBBEnd = getMBB().end();
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if (B == MBBEnd)
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return true;
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assert(A->getParent() == B->getParent() &&
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"Iterators should be in same block");
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const MachineBasicBlock *BBA = A->getParent();
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MachineBasicBlock::const_iterator I = BBA->begin();
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for (; &*I != A && &*I != B; ++I)
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;
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return &*I == A;
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}
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MachineInstrBuilder
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CSEMIRBuilder::getDominatingInstrForID(FoldingSetNodeID &ID,
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void *&NodeInsertPos) {
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GISelCSEInfo *CSEInfo = getCSEInfo();
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assert(CSEInfo && "Can't get here without setting CSEInfo");
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MachineBasicBlock *CurMBB = &getMBB();
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MachineInstr *MI =
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CSEInfo->getMachineInstrIfExists(ID, CurMBB, NodeInsertPos);
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if (MI) {
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2019-02-08 23:34:11 +00:00
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CSEInfo->countOpcodeHit(MI->getOpcode());
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2019-01-16 00:40:37 +00:00
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auto CurrPos = getInsertPt();
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if (!dominates(MI, CurrPos))
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CurMBB->splice(CurrPos, CurMBB, MI);
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return MachineInstrBuilder(getMF(), MI);
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}
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return MachineInstrBuilder();
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}
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bool CSEMIRBuilder::canPerformCSEForOpc(unsigned Opc) const {
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const GISelCSEInfo *CSEInfo = getCSEInfo();
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if (!CSEInfo || !CSEInfo->shouldCSE(Opc))
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return false;
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return true;
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}
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void CSEMIRBuilder::profileDstOp(const DstOp &Op,
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GISelInstProfileBuilder &B) const {
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switch (Op.getDstOpKind()) {
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case DstOp::DstType::Ty_RC:
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B.addNodeIDRegType(Op.getRegClass());
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break;
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default:
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B.addNodeIDRegType(Op.getLLTTy(*getMRI()));
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break;
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}
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}
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void CSEMIRBuilder::profileSrcOp(const SrcOp &Op,
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GISelInstProfileBuilder &B) const {
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switch (Op.getSrcOpKind()) {
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2020-07-17 16:03:20 -07:00
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case SrcOp::SrcType::Ty_Imm:
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B.addNodeIDImmediate(static_cast<int64_t>(Op.getImm()));
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break;
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2019-01-16 00:40:37 +00:00
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case SrcOp::SrcType::Ty_Predicate:
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B.addNodeIDImmediate(static_cast<int64_t>(Op.getPredicate()));
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break;
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default:
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B.addNodeIDRegType(Op.getReg());
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break;
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}
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}
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void CSEMIRBuilder::profileMBBOpcode(GISelInstProfileBuilder &B,
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unsigned Opc) const {
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// First add the MBB (Local CSE).
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B.addNodeIDMBB(&getMBB());
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// Then add the opcode.
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B.addNodeIDOpcode(Opc);
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}
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void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps,
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ArrayRef<SrcOp> SrcOps,
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Optional<unsigned> Flags,
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GISelInstProfileBuilder &B) const {
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profileMBBOpcode(B, Opc);
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// Then add the DstOps.
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profileDstOps(DstOps, B);
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// Then add the SrcOps.
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profileSrcOps(SrcOps, B);
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// Add Flags if passed in.
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if (Flags)
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B.addNodeIDFlag(*Flags);
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}
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MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB,
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void *NodeInsertPos) {
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assert(canPerformCSEForOpc(MIB->getOpcode()) &&
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"Attempting to CSE illegal op");
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MachineInstr *MIBInstr = MIB;
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getCSEInfo()->insertInstr(MIBInstr, NodeInsertPos);
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return MIB;
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}
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bool CSEMIRBuilder::checkCopyToDefsPossible(ArrayRef<DstOp> DstOps) {
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if (DstOps.size() == 1)
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return true; // always possible to emit copy to just 1 vreg.
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return std::all_of(DstOps.begin(), DstOps.end(), [](const DstOp &Op) {
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DstOp::DstType DT = Op.getDstOpKind();
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return DT == DstOp::DstType::Ty_LLT || DT == DstOp::DstType::Ty_RC;
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});
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}
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MachineInstrBuilder
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CSEMIRBuilder::generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
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MachineInstrBuilder &MIB) {
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assert(checkCopyToDefsPossible(DstOps) &&
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"Impossible return a single MIB with copies to multiple defs");
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if (DstOps.size() == 1) {
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const DstOp &Op = DstOps[0];
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if (Op.getDstOpKind() == DstOp::DstType::Ty_Reg)
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2020-01-23 11:51:35 +00:00
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return buildCopy(Op.getReg(), MIB.getReg(0));
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2019-01-16 00:40:37 +00:00
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}
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return MIB;
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}
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MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
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ArrayRef<DstOp> DstOps,
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ArrayRef<SrcOp> SrcOps,
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Optional<unsigned> Flag) {
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switch (Opc) {
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default:
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break;
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case TargetOpcode::G_ADD:
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case TargetOpcode::G_AND:
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case TargetOpcode::G_ASHR:
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case TargetOpcode::G_LSHR:
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case TargetOpcode::G_MUL:
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case TargetOpcode::G_OR:
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case TargetOpcode::G_SHL:
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case TargetOpcode::G_SUB:
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case TargetOpcode::G_XOR:
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case TargetOpcode::G_UDIV:
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case TargetOpcode::G_SDIV:
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case TargetOpcode::G_UREM:
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case TargetOpcode::G_SREM: {
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// Try to constant fold these.
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assert(SrcOps.size() == 2 && "Invalid sources");
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assert(DstOps.size() == 1 && "Invalid dsts");
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if (Optional<APInt> Cst = ConstantFoldBinOp(Opc, SrcOps[0].getReg(),
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SrcOps[1].getReg(), *getMRI()))
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return buildConstant(DstOps[0], Cst->getSExtValue());
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break;
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}
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[globalisel] Add G_SEXT_INREG
Summary:
Targets often have instructions that can sign-extend certain cases faster
than the equivalent shift-left/arithmetic-shift-right. Such cases can be
identified by matching a shift-left/shift-right pair but there are some
issues with this in the context of combines. For example, suppose you can
sign-extend 8-bit up to 32-bit with a target extend instruction.
%1:_(s32) = G_SHL %0:_(s32), i32 24 # (I've inlined the G_CONSTANT for brevity)
%2:_(s32) = G_ASHR %1:_(s32), i32 24
%3:_(s32) = G_ASHR %2:_(s32), i32 1
would reasonably combine to:
%1:_(s32) = G_SHL %0:_(s32), i32 24
%2:_(s32) = G_ASHR %1:_(s32), i32 25
which no longer matches the special case. If your shifts and extend are
equal cost, this would break even as a pair of shifts but if your shift is
more expensive than the extend then it's cheaper as:
%2:_(s32) = G_SEXT_INREG %0:_(s32), i32 8
%3:_(s32) = G_ASHR %2:_(s32), i32 1
It's possible to match the shift-pair in ISel and emit an extend and ashr.
However, this is far from the only way to break this shift pair and make
it hard to match the extends. Another example is that with the right
known-zeros, this:
%1:_(s32) = G_SHL %0:_(s32), i32 24
%2:_(s32) = G_ASHR %1:_(s32), i32 24
%3:_(s32) = G_MUL %2:_(s32), i32 2
can become:
%1:_(s32) = G_SHL %0:_(s32), i32 24
%2:_(s32) = G_ASHR %1:_(s32), i32 23
All upstream targets have been configured to lower it to the current
G_SHL,G_ASHR pair but will likely want to make it legal in some cases to
handle their faster cases.
To follow-up: Provide a way to legalize based on the constant. At the
moment, I'm thinking that the best way to achieve this is to provide the
MI in LegalityQuery but that opens the door to breaking core principles
of the legalizer (legality is not context sensitive). That said, it's
worth noting that looking at other instructions and acting on that
information doesn't violate this principle in itself. It's only a
violation if, at the end of legalization, a pass that checks legality
without being able to see the context would say an instruction might not be
legal. That's a fairly subtle distinction so to give a concrete example,
saying %2 in:
%1 = G_CONSTANT 16
%2 = G_SEXT_INREG %0, %1
is legal is in violation of that principle if the legality of %2 depends
on %1 being constant and/or being 16. However, legalizing to either:
%2 = G_SEXT_INREG %0, 16
or:
%1 = G_CONSTANT 16
%2:_(s32) = G_SHL %0, %1
%3:_(s32) = G_ASHR %2, %1
depending on whether %1 is constant and 16 does not violate that principle
since both outputs are genuinely legal.
Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, arsenm
Subscribers: sdardis, jvesely, wdng, nhaehnle, rovka, kristof.beyls, javed.absar, hiraditya, jrtc27, atanasyan, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61289
llvm-svn: 368487
2019-08-09 21:11:20 +00:00
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case TargetOpcode::G_SEXT_INREG: {
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assert(DstOps.size() == 1 && "Invalid dst ops");
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assert(SrcOps.size() == 2 && "Invalid src ops");
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const DstOp &Dst = DstOps[0];
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const SrcOp &Src0 = SrcOps[0];
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const SrcOp &Src1 = SrcOps[1];
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if (auto MaybeCst =
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ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
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return buildConstant(Dst, MaybeCst->getSExtValue());
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break;
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}
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2019-01-16 00:40:37 +00:00
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}
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bool CanCopy = checkCopyToDefsPossible(DstOps);
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if (!canPerformCSEForOpc(Opc))
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return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
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// If we can CSE this instruction, but involves generating copies to multiple
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// regs, give up. This frequently happens to UNMERGEs.
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if (!CanCopy) {
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auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
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// CSEInfo would have tracked this instruction. Remove it from the temporary
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// insts.
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getCSEInfo()->handleRemoveInst(&*MIB);
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return MIB;
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}
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FoldingSetNodeID ID;
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GISelInstProfileBuilder ProfBuilder(ID, *getMRI());
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void *InsertPos = nullptr;
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profileEverything(Opc, DstOps, SrcOps, Flag, ProfBuilder);
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MachineInstrBuilder MIB = getDominatingInstrForID(ID, InsertPos);
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if (MIB) {
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// Handle generating copies here.
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return generateCopiesIfRequired(DstOps, MIB);
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}
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// This instruction does not exist in the CSEInfo. Build it and CSE it.
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MachineInstrBuilder NewMIB =
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MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
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return memoizeMI(NewMIB, InsertPos);
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}
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MachineInstrBuilder CSEMIRBuilder::buildConstant(const DstOp &Res,
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const ConstantInt &Val) {
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constexpr unsigned Opc = TargetOpcode::G_CONSTANT;
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if (!canPerformCSEForOpc(Opc))
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return MachineIRBuilder::buildConstant(Res, Val);
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2019-02-04 19:15:50 +00:00
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// For vectors, CSE the element only for now.
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LLT Ty = Res.getLLTTy(*getMRI());
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if (Ty.isVector())
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return buildSplatVector(Res, buildConstant(Ty.getElementType(), Val));
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2019-01-16 00:40:37 +00:00
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FoldingSetNodeID ID;
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GISelInstProfileBuilder ProfBuilder(ID, *getMRI());
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void *InsertPos = nullptr;
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profileMBBOpcode(ProfBuilder, Opc);
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profileDstOp(Res, ProfBuilder);
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ProfBuilder.addNodeIDMachineOperand(MachineOperand::CreateCImm(&Val));
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MachineInstrBuilder MIB = getDominatingInstrForID(ID, InsertPos);
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if (MIB) {
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// Handle generating copies here.
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return generateCopiesIfRequired({Res}, MIB);
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}
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2019-02-04 19:15:50 +00:00
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2019-01-16 00:40:37 +00:00
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MachineInstrBuilder NewMIB = MachineIRBuilder::buildConstant(Res, Val);
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return memoizeMI(NewMIB, InsertPos);
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}
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MachineInstrBuilder CSEMIRBuilder::buildFConstant(const DstOp &Res,
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const ConstantFP &Val) {
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constexpr unsigned Opc = TargetOpcode::G_FCONSTANT;
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if (!canPerformCSEForOpc(Opc))
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return MachineIRBuilder::buildFConstant(Res, Val);
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2019-02-04 19:15:50 +00:00
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// For vectors, CSE the element only for now.
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LLT Ty = Res.getLLTTy(*getMRI());
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if (Ty.isVector())
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return buildSplatVector(Res, buildFConstant(Ty.getElementType(), Val));
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2019-01-16 00:40:37 +00:00
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FoldingSetNodeID ID;
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GISelInstProfileBuilder ProfBuilder(ID, *getMRI());
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void *InsertPos = nullptr;
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profileMBBOpcode(ProfBuilder, Opc);
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profileDstOp(Res, ProfBuilder);
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ProfBuilder.addNodeIDMachineOperand(MachineOperand::CreateFPImm(&Val));
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MachineInstrBuilder MIB = getDominatingInstrForID(ID, InsertPos);
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if (MIB) {
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// Handle generating copies here.
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return generateCopiesIfRequired({Res}, MIB);
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}
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MachineInstrBuilder NewMIB = MachineIRBuilder::buildFConstant(Res, Val);
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return memoizeMI(NewMIB, InsertPos);
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}
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