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llvm-project/clang/test/CodeGen/bpf-inline-asm.c

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[BPF] add support for 32 bit registers in inline asm Add "w" constraint type which allows selecting 32 bit registers. 32 bit registers were added in https://reviews.llvm.org/rGca31c3bb3ff149850b664838fbbc7d40ce571879. Differential Revision: https://reviews.llvm.org/D102118
2021-05-16 09:32:36 -07:00
// REQUIRES: bpf-registered-target
[CodeGen] Convert tests to opaque pointers (NFC) Conversion performed using the script at: https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34 These are only tests where no manual fixup was required.
2022-10-07 14:09:44 +02:00
// RUN: %clang_cc1 -triple bpf -emit-llvm -target-feature +alu32 %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple bpf -emit-llvm -target-cpu v3 %s -o - | FileCheck %s
[BPF] add support for 32 bit registers in inline asm Add "w" constraint type which allows selecting 32 bit registers. 32 bit registers were added in https://reviews.llvm.org/rGca31c3bb3ff149850b664838fbbc7d40ce571879. Differential Revision: https://reviews.llvm.org/D102118
2021-05-16 09:32:36 -07:00
void test_generic_constraints(int var32, long var64) {
asm("%0 = %1"
: "=r"(var32)
: "0"(var32));
[CodeGen] Convert tests to opaque pointers (NFC) Conversion performed using the script at: https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34 These are only tests where no manual fixup was required.
2022-10-07 14:09:44 +02:00
// CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, ptr
[BPF] add support for 32 bit registers in inline asm Add "w" constraint type which allows selecting 32 bit registers. 32 bit registers were added in https://reviews.llvm.org/rGca31c3bb3ff149850b664838fbbc7d40ce571879. Differential Revision: https://reviews.llvm.org/D102118
2021-05-16 09:32:36 -07:00
// CHECK: call i32 asm "$0 = $1", "=r,0"(i32 [[R32_ARG]])
asm("%0 = %1"
: "=r"(var64)
: "0"(var64));
[CodeGen] Convert tests to opaque pointers (NFC) Conversion performed using the script at: https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34 These are only tests where no manual fixup was required.
2022-10-07 14:09:44 +02:00
// CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, ptr
[BPF] add support for 32 bit registers in inline asm Add "w" constraint type which allows selecting 32 bit registers. 32 bit registers were added in https://reviews.llvm.org/rGca31c3bb3ff149850b664838fbbc7d40ce571879. Differential Revision: https://reviews.llvm.org/D102118
2021-05-16 09:32:36 -07:00
// CHECK: call i64 asm "$0 = $1", "=r,0"(i64 [[R64_ARG]])
asm("%0 = %1"
: "=r"(var64)
: "r"(var64));
[CodeGen] Convert tests to opaque pointers (NFC) Conversion performed using the script at: https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34 These are only tests where no manual fixup was required.
2022-10-07 14:09:44 +02:00
// CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, ptr
[BPF] add support for 32 bit registers in inline asm Add "w" constraint type which allows selecting 32 bit registers. 32 bit registers were added in https://reviews.llvm.org/rGca31c3bb3ff149850b664838fbbc7d40ce571879. Differential Revision: https://reviews.llvm.org/D102118
2021-05-16 09:32:36 -07:00
// CHECK: call i64 asm "$0 = $1", "=r,r"(i64 [[R64_ARG]])
}
void test_constraint_w(int a) {
asm("%0 = %1"
: "=w"(a)
: "w"(a));
[CodeGen] Convert tests to opaque pointers (NFC) Conversion performed using the script at: https://gist.github.com/nikic/98357b71fd67756b0f064c9517b62a34 These are only tests where no manual fixup was required.
2022-10-07 14:09:44 +02:00
// CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, ptr
[BPF] add support for 32 bit registers in inline asm Add "w" constraint type which allows selecting 32 bit registers. 32 bit registers were added in https://reviews.llvm.org/rGca31c3bb3ff149850b664838fbbc7d40ce571879. Differential Revision: https://reviews.llvm.org/D102118
2021-05-16 09:32:36 -07:00
// CHECK: call i32 asm "$0 = $1", "=w,w"(i32 [[R32_ARG]])
}
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