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[RISCV] Overwrite cpu target features for full arch string in target attribute (#77426)
This patch reworks RISCVTargetInfo::initFeatureMap to fix the issue described in https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559 (and is an alternative to #75804) When a full arch string is specified, a "full" list of extensions is now passed after the __RISCV_TargetAttrNeedOverride marker feature, which includes any negative features that disable ISA extensions. In initFeatureMap, there are now two code paths: 1. If the arch string was overriden, use the "full" list of override features, only adding back any non-isa features that were specified. Using the full list of positive and negative features will mean that the target-cpu will have no effect on the final arch, e.g. __attribute__((target("arch=rv64i"))) with -mcpu=sifive-x280 will have the features for rv64i, not a mix of both. 2. Otherwise, parse and *append* the list of implied features. By appending, we turn back on any features that might have been disabled by a negative extension, i.e. this handles the case fixed in #74889.
This commit is contained in:
Luke Lau
GitHub
parent
00d6232d6b
commit
069e9b4495
@ -241,39 +241,6 @@ ArrayRef<Builtin::Info> RISCVTargetInfo::getTargetBuiltins() const {
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clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
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}
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static std::vector<std::string>
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collectNonISAExtFeature(ArrayRef<std::string> FeaturesNeedOverride, int XLen) {
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std::vector<std::string> NonISAExtFeatureVec;
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auto IsNonISAExtFeature = [](const std::string &Feature) {
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assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
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StringRef Ext = StringRef(Feature).drop_front(); // drop the +/-
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return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
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};
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llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
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IsNonISAExtFeature);
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return NonISAExtFeatureVec;
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}
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static std::vector<std::string>
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resolveTargetAttrOverride(const std::vector<std::string> &FeaturesVec,
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int XLen) {
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auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
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if (I == FeaturesVec.end())
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return FeaturesVec;
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ArrayRef<std::string> FeaturesNeedOverride(&*FeaturesVec.begin(), &*I);
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std::vector<std::string> NonISAExtFeature =
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collectNonISAExtFeature(FeaturesNeedOverride, XLen);
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std::vector<std::string> ResolvedFeature(++I, FeaturesVec.end());
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ResolvedFeature.insert(ResolvedFeature.end(), NonISAExtFeature.begin(),
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NonISAExtFeature.end());
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return ResolvedFeature;
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}
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bool RISCVTargetInfo::initFeatureMap(
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llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const {
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@ -287,10 +254,27 @@ bool RISCVTargetInfo::initFeatureMap(
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Features["32bit"] = true;
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}
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std::vector<std::string> NewFeaturesVec =
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resolveTargetAttrOverride(FeaturesVec, XLen);
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// If a target attribute specified a full arch string, override all the ISA
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// extension target features.
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const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
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if (I != FeaturesVec.end()) {
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std::vector<std::string> OverrideFeatures(std::next(I), FeaturesVec.end());
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auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
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// Add back any non ISA extension features, e.g. +relax.
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auto IsNonISAExtFeature = [](StringRef Feature) {
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assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
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StringRef Ext = Feature.substr(1); // drop the +/-
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return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
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};
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llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I),
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std::back_inserter(OverrideFeatures), IsNonISAExtFeature);
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return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);
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}
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// Otherwise, parse the features and add any implied extensions.
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std::vector<std::string> AllFeatures = FeaturesVec;
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auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
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if (!ParseResult) {
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std::string Buffer;
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llvm::raw_string_ostream OutputErrMsg(Buffer);
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@ -301,21 +285,9 @@ bool RISCVTargetInfo::initFeatureMap(
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return false;
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}
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// RISCVISAInfo makes implications for ISA features
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std::vector<std::string> ImpliedFeatures = (*ParseResult)->toFeatures();
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// parseFeatures normalizes the feature set by dropping any explicit
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// negatives, and non-extension features. We need to preserve the later
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// for correctness and want to preserve the former for consistency.
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for (auto &Feature : NewFeaturesVec) {
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StringRef ExtName = Feature;
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assert(ExtName.size() > 1 && (ExtName[0] == '+' || ExtName[0] == '-'));
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ExtName = ExtName.drop_front(1); // Drop '+' or '-'
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if (!llvm::is_contained(ImpliedFeatures, ("+" + ExtName).str()) &&
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!llvm::is_contained(ImpliedFeatures, ("-" + ExtName).str()))
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ImpliedFeatures.push_back(Feature);
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}
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return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures);
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// Append all features, not just new ones, so we override any negatives.
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llvm::append_range(AllFeatures, (*ParseResult)->toFeatures());
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return TargetInfo::initFeatureMap(Features, Diags, CPU, AllFeatures);
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}
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std::optional<std::pair<unsigned, unsigned>>
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@ -424,7 +396,10 @@ static void handleFullArchString(StringRef FullArchStr,
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// Forward the invalid FullArchStr.
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Features.push_back("+" + FullArchStr.str());
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} else {
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std::vector<std::string> FeatStrings = (*RII)->toFeatures();
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// Append a full list of features, including any negative extensions so that
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// we override the CPU's features.
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std::vector<std::string> FeatStrings =
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(*RII)->toFeatures(/* AddAllExtensions */ true);
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Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
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}
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}
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@ -40,8 +40,8 @@ __attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {}
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// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
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// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
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// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
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// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax" }
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// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,-relax" }
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// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zicond,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-h,-relax,-smaia,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
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// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zicond,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-relax,-smaia,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
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// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
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// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,-relax" }
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// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax" }
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// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zicond,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-relax,-smaia,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
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// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zicond,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-h,-relax,-smaia,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
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