[flang] build test fix/suppression (#118716)

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vdonaldson 2024-12-04 18:47:45 -05:00 committed by GitHub
parent 659834df0e
commit 17f99accf2
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3 changed files with 9 additions and 47 deletions

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@ -58,7 +58,7 @@ module m
logical, parameter :: test_sn_all = ieee_support_subnormal()
logical, parameter :: test_sn_4 = ieee_support_subnormal(1.)
logical, parameter :: test_sn_8 = ieee_support_subnormal(1.d0)
logical, parameter :: test_uc_all = .not. ieee_support_underflow_control()
! logical, parameter :: test_uc_all = .not. ieee_support_underflow_control() ! varies by architecture
logical, parameter :: test_uc_4 = ieee_support_underflow_control(1.)
logical, parameter :: test_uc_8 = ieee_support_underflow_control(1.d0)
end

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@ -65,11 +65,12 @@ module m
.and. ieee_support_subnormal(1.0_8) &
.and. ieee_support_subnormal(1.0_10) &
.and. ieee_support_subnormal(1.0_16)
logical, parameter :: test_ieee_support_underflow_control = .not. ieee_support_underflow_control() &
.and. .not. ieee_support_underflow_control(1.0_2) &
.and. ieee_support_underflow_control(1.0_3) &
.and. ieee_support_underflow_control(1.0_4) &
.and. ieee_support_underflow_control(1.0_8) &
.and. .not. ieee_support_underflow_control(1.0_10) &
.and. .not. ieee_support_underflow_control(1.0_16)
! varies by architecture
! logical, parameter :: test_ieee_support_underflow_control = .not. ieee_support_underflow_control() &
! .and. .not. ieee_support_underflow_control(1.0_2) &
! .and. ieee_support_underflow_control(1.0_3) &
! .and. ieee_support_underflow_control(1.0_4) &
! .and. ieee_support_underflow_control(1.0_8) &
! .and. .not. ieee_support_underflow_control(1.0_10) &
! .and. .not. ieee_support_underflow_control(1.0_16)
end module

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@ -1,39 +0,0 @@
! RUN: bbc -emit-hlfir -o - %s | FileCheck %s
! CHECK-LABEL: c.func @_QPs
subroutine s
! CHECK: %[[V_0:[0-9]+]] = fir.call @fetestexcept(%c-1{{.*}}) fastmath<contract> : (i32) -> i32
! CHECK: %[[V_1:[0-9]+]] = fir.call @feclearexcept(%[[V_0]]) fastmath<contract> : (i32) -> i32
! CHECK: %[[V_2:[0-9]+]] = fir.call @_FortranAGetUnderflowMode() fastmath<contract> : () -> i1
use ieee_arithmetic, only: ieee_get_underflow_mode, ieee_set_underflow_mode
! CHECK: %[[V_3:[0-9]+]] = fir.alloca !fir.logical<4> {bindc_name = "r", uniq_name = "_QFsEr"}
! CHECK: %[[V_4:[0-9]+]]:2 = hlfir.declare %[[V_3]] {uniq_name = "_QFsEr"} : (!fir.ref<!fir.logical<4>>) -> (!fir.ref<!fir.logical<4>>, !fir.ref<!fir.logical<4>>)
logical r
! CHECK: %[[V_5:[0-9]+]] = fir.convert %false{{[_0-9]*}} : (i1) -> i1
! CHECK: %[[V_6:[0-9]+]] = fir.call @_FortranASetUnderflowMode(%[[V_5]]) fastmath<contract> : (i1) -> none
call ieee_set_underflow_mode(.false.)
! CHECK: %[[V_7:[0-9]+]] = fir.call @_FortranAGetUnderflowMode() fastmath<contract> : () -> i1
! CHECK: %[[V_8:[0-9]+]] = fir.convert %[[V_7]] : (i1) -> !fir.logical<4>
! CHECK: fir.store %[[V_8]] to %[[V_4]]#1 : !fir.ref<!fir.logical<4>>
call ieee_get_underflow_mode(r)
! print*, r
! CHECK: %[[V_9:[0-9]+]] = fir.convert %true{{[_0-9]*}} : (i1) -> i1
! CHECK: %[[V_10:[0-9]+]] = fir.call @_FortranASetUnderflowMode(%[[V_9]]) fastmath<contract> : (i1) -> none
call ieee_set_underflow_mode(.true.)
! CHECK: %[[V_11:[0-9]+]] = fir.call @_FortranAGetUnderflowMode() fastmath<contract> : () -> i1
! CHECK: %[[V_12:[0-9]+]] = fir.convert %[[V_11]] : (i1) -> !fir.logical<4>
! CHECK: fir.store %[[V_12]] to %[[V_4]]#1 : !fir.ref<!fir.logical<4>>
call ieee_get_underflow_mode(r)
! print*, r
! CHECK: %[[V_13:[0-9]+]] = fir.call @_FortranASetUnderflowMode(%[[V_2]]) fastmath<contract> : (i1) -> none
! CHECK: %[[V_14:[0-9]+]] = fir.call @feraiseexcept(%[[V_0]]) fastmath<contract> : (i32) -> i32
end
call s
end