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[FMV] Remove useless features according the latest ACLE spec. (#88965)
As explained in https://github.com/ARM-software/acle/pull/315 we are deprecating features which aren't adding any value. These are: sha1, pmull, dit, dgh, ebf16, sve-bf16, sve-ebf16, sve-i8mm, sve2-pmull128, memtag2, memtag3, ssbs2, bti, ls64_v, ls64_accdata
This commit is contained in:
Alexandros Lamprineas
GitHub
parent
da70f2cdcd
commit
19c6a7feca
@ -1,15 +1,17 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals --version 2
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
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//.
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// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
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//.
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// CHECK-LABEL: define dso_local i32 @main
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// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 34359738368
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 34359738368
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
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// CHECK: if.then:
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@ -17,8 +19,8 @@
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// CHECK-NEXT: br label [[RETURN:%.*]]
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// CHECK: if.end:
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 9070970929152
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 9070970929152
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17716740096
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17716740096
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// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
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// CHECK-NEXT: br i1 [[TMP7]], label [[IF_THEN1:%.*]], label [[IF_END2:%.*]]
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// CHECK: if.then1:
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@ -26,8 +28,8 @@
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// CHECK-NEXT: br label [[RETURN]]
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// CHECK: if.end2:
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// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 166633186212708352
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// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 166633186212708352
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// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 5222680231936
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// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 5222680231936
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// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
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// CHECK-NEXT: br i1 [[TMP11]], label [[IF_THEN3:%.*]], label [[IF_END4:%.*]]
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// CHECK: if.then3:
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@ -49,10 +51,10 @@ int main(void) {
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if (__builtin_cpu_supports("sb"))
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return 1;
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if (__builtin_cpu_supports("sve2-pmull128+memtag"))
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if (__builtin_cpu_supports("sve2-aes+memtag"))
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return 2;
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if (__builtin_cpu_supports("sme2+ls64_v+wfxt"))
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if (__builtin_cpu_supports("sme2+ls64+wfxt"))
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return 3;
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if (__builtin_cpu_supports("avx2"))
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@ -60,3 +62,9 @@ int main(void) {
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return 0;
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}
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//.
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// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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//.
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// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
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// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
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//.
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@ -69,8 +69,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
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// CHECK-NEXT: resolver_entry:
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// CHECK-NEXT: call void @__init_cpu_features_resolver()
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 131072
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 131072
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
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// CHECK: resolver_return:
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@ -143,8 +143,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
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// CHECK-NEXT: resolver_entry:
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// CHECK-NEXT: call void @__init_cpu_features_resolver()
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 131072
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 131072
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
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// CHECK: resolver_return:
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@ -210,8 +210,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
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// CHECK-NEXT: resolver_entry:
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// CHECK-NEXT: call void @__init_cpu_features_resolver()
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 131072
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 131072
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
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// CHECK: resolver_return:
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@ -3,7 +3,7 @@
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -S -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV
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int __attribute__((target_clones("lse+aes", "sve2"))) ftc(void) { return 0; }
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int __attribute__((target_clones("sha2", "sha2+memtag2", " default "))) ftc_def(void) { return 1; }
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int __attribute__((target_clones("sha2", "sha2+memtag", " default "))) ftc_def(void) { return 1; }
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int __attribute__((target_clones("sha2", "default"))) ftc_dup1(void) { return 2; }
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int __attribute__((target_clones("fp", "crc+dotprod"))) ftc_dup2(void) { return 3; }
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int foo() {
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@ -12,7 +12,7 @@ int foo() {
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inline int __attribute__((target_clones("rng+simd", "rcpc+predres", "sve2-aes+wfxt"))) ftc_inline1(void) { return 1; }
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inline int __attribute__((target_clones("fp16", "fcma+sve2-bitperm", "default"))) ftc_inline2(void);
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inline int __attribute__((target_clones("bti", "sve+sb"))) ftc_inline3(void) { return 3; }
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inline int __attribute__((target_clones("mops", "sve+sb"))) ftc_inline3(void) { return 3; }
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int __attribute__((target_clones("default"))) ftc_direct(void) { return 4; }
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@ -56,16 +56,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
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// CHECK-NEXT: resolver_entry:
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// CHECK-NEXT: call void @__init_cpu_features_resolver()
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 16512
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16512
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 8320
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 8320
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
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// CHECK: resolver_return:
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// CHECK-NEXT: ret ptr @ftc._MaesMlse
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// CHECK: resolver_else:
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 68719476736
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 68719476736
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 268435456
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 268435456
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// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
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// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
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// CHECK: resolver_return1:
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@ -81,7 +81,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
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//
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//
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// CHECK: Function Attrs: noinline nounwind optnone
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// CHECK-LABEL: @ftc_def._Mmemtag2Msha2(
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// CHECK-LABEL: @ftc_def._MmemtagMsha2(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret i32 1
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//
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@ -90,16 +90,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
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// CHECK-NEXT: resolver_entry:
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// CHECK-NEXT: call void @__init_cpu_features_resolver()
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17592186048512
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17592186048512
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 17179871232
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 17179871232
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
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// CHECK: resolver_return:
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// CHECK-NEXT: ret ptr @ftc_def._Mmemtag2Msha2
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// CHECK-NEXT: ret ptr @ftc_def._MmemtagMsha2
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// CHECK: resolver_else:
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4096
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 2048
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2048
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// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
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// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
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// CHECK: resolver_return1:
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@ -118,8 +118,8 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
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// CHECK-NEXT: resolver_entry:
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// CHECK-NEXT: call void @__init_cpu_features_resolver()
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4096
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2048
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2048
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
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// CHECK: resolver_return:
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@ -198,16 +198,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
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// CHECK-NEXT: resolver_entry:
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// CHECK-NEXT: call void @__init_cpu_features_resolver()
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014535948435456
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014535948435456
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 550292684800
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 550292684800
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
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// CHECK: resolver_return:
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// CHECK-NEXT: ret ptr @ftc_inline1._Msve2-aesMwfxt
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// CHECK: resolver_else:
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 140737492549632
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 140737492549632
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 68720001024
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 68720001024
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// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
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// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
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// CHECK: resolver_return1:
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@ -228,16 +228,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
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// CHECK-NEXT: resolver_entry:
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// CHECK-NEXT: call void @__init_cpu_features_resolver()
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 549757911040
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 549757911040
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1074003968
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1074003968
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
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// CHECK: resolver_return:
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// CHECK-NEXT: ret ptr @ftc_inline2._MfcmaMsve2-bitperm
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// CHECK: resolver_else:
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 65536
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 65536
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 16384
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 16384
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// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
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// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
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// CHECK: resolver_return1:
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@ -250,20 +250,20 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
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// CHECK-NEXT: resolver_entry:
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// CHECK-NEXT: call void @__init_cpu_features_resolver()
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70369817919488
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70369817919488
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 34393292800
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 34393292800
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
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// CHECK: resolver_return:
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// CHECK-NEXT: ret ptr @ftc_inline3._MsbMsve
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// CHECK: resolver_else:
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1125899906842624
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 1125899906842624
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17592186044416
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17592186044416
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// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
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// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
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// CHECK: resolver_return1:
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// CHECK-NEXT: ret ptr @ftc_inline3._Mbti
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// CHECK-NEXT: ret ptr @ftc_inline3._Mmops
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// CHECK: resolver_else2:
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// CHECK-NEXT: ret ptr @ftc_inline3.default
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//
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@ -329,7 +329,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
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//
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//
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// CHECK: Function Attrs: noinline nounwind optnone
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// CHECK-LABEL: @ftc_inline3._Mbti(
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// CHECK-LABEL: @ftc_inline3._Mmops(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret i32 3
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//
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@ -407,17 +407,16 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
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// CHECK: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon" }
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// CHECK: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2" }
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// CHECK: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sha2" }
|
||||
// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+mte,+neon,+sha2" }
|
||||
// CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
|
||||
// CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+dotprod,+fp-armv8,+neon" }
|
||||
// CHECK: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
|
||||
// CHECK: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
|
||||
// CHECK: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm" }
|
||||
// CHECK: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rand" }
|
||||
// CHECK: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc" }
|
||||
// CHECK: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
|
||||
// CHECK: attributes #[[ATTR12:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti" }
|
||||
// CHECK: attributes #[[ATTR13:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sb,+sve" }
|
||||
// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
|
||||
// CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+dotprod,+fp-armv8,+neon" }
|
||||
// CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
|
||||
// CHECK: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
|
||||
// CHECK: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm" }
|
||||
// CHECK: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rand" }
|
||||
// CHECK: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc" }
|
||||
// CHECK: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
|
||||
// CHECK: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops" }
|
||||
// CHECK: attributes #[[ATTR12:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sb,+sve" }
|
||||
//.
|
||||
// CHECK-NOFMV: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
|
||||
// CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
|
||||
|
||||
@ -5,11 +5,11 @@
|
||||
int __attribute__((target_version("rng+flagm+fp16fml"))) fmv(void) { return 1; }
|
||||
int __attribute__((target_version("flagm2+sme-i16i64"))) fmv(void) { return 2; }
|
||||
int __attribute__((target_version("lse+sha2"))) fmv(void) { return 3; }
|
||||
int __attribute__((target_version("dotprod+ls64_accdata"))) fmv(void) { return 4; }
|
||||
int __attribute__((target_version("dotprod+ls64"))) fmv(void) { return 4; }
|
||||
int __attribute__((target_version("fp16fml+memtag"))) fmv(void) { return 5; }
|
||||
int __attribute__((target_version("fp+aes"))) fmv(void) { return 6; }
|
||||
int __attribute__((target_version("crc+ls64_v"))) fmv(void) { return 7; }
|
||||
int __attribute__((target_version("bti"))) fmv(void) { return 8; }
|
||||
int __attribute__((target_version("crc+ls64"))) fmv(void) { return 7; }
|
||||
int __attribute__((target_version("mops"))) fmv(void) { return 8; }
|
||||
int __attribute__((target_version("sme2"))) fmv(void) { return 9; }
|
||||
int __attribute__((target_version("default"))) fmv(void);
|
||||
int __attribute__((target_version("ls64+simd"))) fmv_one(void) { return 1; }
|
||||
@ -17,25 +17,25 @@ int __attribute__((target_version("dpb"))) fmv_one(void) { return 2; }
|
||||
int __attribute__((target_version("default"))) fmv_one(void);
|
||||
int __attribute__((target_version("fp"))) fmv_two(void) { return 1; }
|
||||
int __attribute__((target_version("simd"))) fmv_two(void) { return 2; }
|
||||
int __attribute__((target_version("dgh"))) fmv_two(void) { return 3; }
|
||||
int __attribute__((target_version("frintts"))) fmv_two(void) { return 3; }
|
||||
int __attribute__((target_version("fp16+simd"))) fmv_two(void) { return 4; }
|
||||
int __attribute__((target_version("default"))) fmv_two(void);
|
||||
int foo() {
|
||||
return fmv()+fmv_one()+fmv_two();
|
||||
}
|
||||
|
||||
inline int __attribute__((target_version("sha1+pmull+f64mm"))) fmv_inline(void) { return 1; }
|
||||
inline int __attribute__((target_version("crypto+f64mm"))) fmv_inline(void) { return 1; }
|
||||
inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; }
|
||||
inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; }
|
||||
inline int __attribute__((target_version("dit+sve-ebf16"))) fmv_inline(void) { return 8; }
|
||||
inline int __attribute__((target_version("sme2+ssbs"))) fmv_inline(void) { return 8; }
|
||||
inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; }
|
||||
inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; }
|
||||
inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; }
|
||||
inline int __attribute__((target_version("sve+sve-bf16"))) fmv_inline(void) { return 4; }
|
||||
inline int __attribute__((target_version("sve+sme"))) fmv_inline(void) { return 4; }
|
||||
inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; }
|
||||
inline int __attribute__((target_version("sve2+sve2-pmull128+sve2-bitperm"))) fmv_inline(void) { return 9; }
|
||||
inline int __attribute__((target_version("sve2-sm4+memtag2"))) fmv_inline(void) { return 10; }
|
||||
inline int __attribute__((target_version("memtag3+rcpc3+mops"))) fmv_inline(void) { return 11; }
|
||||
inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; }
|
||||
inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; }
|
||||
inline int __attribute__((target_version("memtag+rcpc3+mops"))) fmv_inline(void) { return 11; }
|
||||
inline int __attribute__((target_version("aes+dotprod"))) fmv_inline(void) { return 13; }
|
||||
inline int __attribute__((target_version("simd+fp16fml"))) fmv_inline(void) { return 14; }
|
||||
inline int __attribute__((target_version("fp+sm4"))) fmv_inline(void) { return 15; }
|
||||
@ -186,7 +186,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv._MdotprodMls64_accdata
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv._MdotprodMls64
|
||||
// CHECK-SAME: () #[[ATTR3:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 4
|
||||
@ -207,14 +207,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv._McrcMls64_v
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv._McrcMls64
|
||||
// CHECK-SAME: () #[[ATTR6:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 7
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv._Mbti
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv._Mmops
|
||||
// CHECK-SAME: () #[[ATTR7:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 8
|
||||
@ -256,7 +256,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mdgh
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfrintts
|
||||
// CHECK-SAME: () #[[ATTR11:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 3
|
||||
@ -271,7 +271,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@foo
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv()
|
||||
// CHECK-NEXT: [[CALL1:%.*]] = call i32 @fmv_one()
|
||||
@ -293,68 +293,68 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: ret ptr @fmv._MflagmMfp16fmlMrng
|
||||
// CHECK: resolver_else:
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 72057594037927940
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 72057594037927940
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 2199023255556
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2199023255556
|
||||
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
|
||||
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
|
||||
// CHECK: resolver_return1:
|
||||
// CHECK-NEXT: ret ptr @fmv._Mflagm2Msme-i16i64
|
||||
// CHECK: resolver_else2:
|
||||
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 9007199254741008
|
||||
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 9007199254741008
|
||||
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 274877906960
|
||||
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 274877906960
|
||||
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
|
||||
// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
|
||||
// CHECK: resolver_return3:
|
||||
// CHECK-NEXT: ret ptr @fmv._MdotprodMls64_accdata
|
||||
// CHECK-NEXT: ret ptr @fmv._MdotprodMls64
|
||||
// CHECK: resolver_else4:
|
||||
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 4503599627371520
|
||||
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 4503599627371520
|
||||
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 274877907968
|
||||
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 274877907968
|
||||
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
|
||||
// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
|
||||
// CHECK: resolver_return5:
|
||||
// CHECK-NEXT: ret ptr @fmv._McrcMls64_v
|
||||
// CHECK-NEXT: ret ptr @fmv._McrcMls64
|
||||
// CHECK: resolver_else6:
|
||||
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 8796093022216
|
||||
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 8796093022216
|
||||
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 17179869192
|
||||
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 17179869192
|
||||
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
|
||||
// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
|
||||
// CHECK: resolver_return7:
|
||||
// CHECK-NEXT: ret ptr @fmv._Mfp16fmlMmemtag
|
||||
// CHECK: resolver_else8:
|
||||
// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 16640
|
||||
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 16640
|
||||
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 8448
|
||||
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 8448
|
||||
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
|
||||
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
|
||||
// CHECK: resolver_return9:
|
||||
// CHECK-NEXT: ret ptr @fmv._MaesMfp
|
||||
// CHECK: resolver_else10:
|
||||
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 4224
|
||||
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 4224
|
||||
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 2176
|
||||
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 2176
|
||||
// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]]
|
||||
// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
|
||||
// CHECK: resolver_return11:
|
||||
// CHECK-NEXT: ret ptr @fmv._MlseMsha2
|
||||
// CHECK: resolver_else12:
|
||||
// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 144115188075855872
|
||||
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 144115188075855872
|
||||
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 17592186044416
|
||||
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 17592186044416
|
||||
// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]]
|
||||
// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
|
||||
// CHECK: resolver_return13:
|
||||
// CHECK-NEXT: ret ptr @fmv._Msme2
|
||||
// CHECK-NEXT: ret ptr @fmv._Mmops
|
||||
// CHECK: resolver_else14:
|
||||
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 1125899906842624
|
||||
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 1125899906842624
|
||||
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 4398046511104
|
||||
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 4398046511104
|
||||
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
|
||||
// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
|
||||
// CHECK: resolver_return15:
|
||||
// CHECK-NEXT: ret ptr @fmv._Mbti
|
||||
// CHECK-NEXT: ret ptr @fmv._Msme2
|
||||
// CHECK: resolver_else16:
|
||||
// CHECK-NEXT: ret ptr @fmv.default
|
||||
//
|
||||
@ -363,16 +363,16 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2251799813685760
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2251799813685760
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 274877907456
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 274877907456
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
// CHECK-NEXT: ret ptr @fmv_one._Mls64Msimd
|
||||
// CHECK: resolver_else:
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 262144
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 262144
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 32768
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 32768
|
||||
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
|
||||
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
|
||||
// CHECK: resolver_return1:
|
||||
@ -385,20 +385,20 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 66048
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66048
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 16896
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16896
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
// CHECK-NEXT: ret ptr @fmv_two._Mfp16Msimd
|
||||
// CHECK: resolver_else:
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33554432
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33554432
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 2097152
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2097152
|
||||
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
|
||||
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
|
||||
// CHECK: resolver_return1:
|
||||
// CHECK-NEXT: ret ptr @fmv_two._Mdgh
|
||||
// CHECK-NEXT: ret ptr @fmv_two._Mfrintts
|
||||
// CHECK: resolver_else2:
|
||||
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 512
|
||||
@ -421,49 +421,49 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_e.default
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 20
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_d._Msb
|
||||
// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR14:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_d.default
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 1
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_default
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 111
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_c._Mssbs
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_c.default
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret void
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@goo
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv_inline()
|
||||
// CHECK-NEXT: [[CALL1:%.*]] = call i32 @fmv_e()
|
||||
@ -477,96 +477,96 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4398048673856
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4398048673856
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 8590213184
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 8590213184
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16MrdmMsme
|
||||
// CHECK: resolver_else:
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 864726312827224064
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 864726312827224064
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 26405458935808
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 26405458935808
|
||||
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
|
||||
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
|
||||
// CHECK: resolver_return1:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Mmemtag3MmopsMrcpc3
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMmopsMrcpc3
|
||||
// CHECK: resolver_else2:
|
||||
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 893353197568
|
||||
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 893353197568
|
||||
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 1879048192
|
||||
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 1879048192
|
||||
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
|
||||
// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
|
||||
// CHECK: resolver_return3:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-bitpermMsve2-pmull128
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-aesMsve2-bitperm
|
||||
// CHECK: resolver_else4:
|
||||
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 34359773184
|
||||
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 34359773184
|
||||
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 71307264
|
||||
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 71307264
|
||||
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
|
||||
// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
|
||||
// CHECK: resolver_return5:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Mf64mmMpmullMsha1
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3
|
||||
// CHECK: resolver_else6:
|
||||
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 17246986240
|
||||
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 17246986240
|
||||
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 4535485464576
|
||||
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 4535485464576
|
||||
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
|
||||
// CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]]
|
||||
// CHECK: resolver_return7:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Msme2Mssbs
|
||||
// CHECK: resolver_else8:
|
||||
// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 19791209299968
|
||||
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 19791209299968
|
||||
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 21474836480
|
||||
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 21474836480
|
||||
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
|
||||
// CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]]
|
||||
// CHECK: resolver_return9:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Mmemtag2Msve2-sm4
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._MmemtagMsve2-sm4
|
||||
// CHECK: resolver_else10:
|
||||
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 1236950581248
|
||||
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 1236950581248
|
||||
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 8623489024
|
||||
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 8623489024
|
||||
// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]]
|
||||
// CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]]
|
||||
// CHECK: resolver_return11:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._MsmeMsve
|
||||
// CHECK: resolver_else12:
|
||||
// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 4295098368
|
||||
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 4295098368
|
||||
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 2684354560
|
||||
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 2684354560
|
||||
// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]]
|
||||
// CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]]
|
||||
// CHECK: resolver_return13:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._MditMsve-ebf16
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3
|
||||
// CHECK: resolver_else14:
|
||||
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 3221225472
|
||||
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 3221225472
|
||||
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 281475110928384
|
||||
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 281475110928384
|
||||
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
|
||||
// CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]]
|
||||
// CHECK: resolver_return15:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._MsveMsve-bf16
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._McryptoMf64mm
|
||||
// CHECK: resolver_else16:
|
||||
// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971520
|
||||
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 20971520
|
||||
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 2621440
|
||||
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 2621440
|
||||
// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]]
|
||||
// CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]]
|
||||
// CHECK: resolver_return17:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._MfrinttsMrcpc
|
||||
// CHECK: resolver_else18:
|
||||
// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 8650752
|
||||
// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 8650752
|
||||
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 1081344
|
||||
// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 1081344
|
||||
// CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]]
|
||||
// CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]]
|
||||
// CHECK: resolver_return19:
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._MdpbMrcpc2
|
||||
// CHECK: resolver_else20:
|
||||
// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 1572864
|
||||
// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 1572864
|
||||
// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 196608
|
||||
// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 196608
|
||||
// CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]]
|
||||
// CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]]
|
||||
// CHECK: resolver_return21:
|
||||
@ -581,8 +581,8 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd
|
||||
// CHECK: resolver_else24:
|
||||
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 16400
|
||||
// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 16400
|
||||
// CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 8208
|
||||
// CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 8208
|
||||
// CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]]
|
||||
// CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]]
|
||||
// CHECK: resolver_return25:
|
||||
@ -611,8 +611,8 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 2251799813685248
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 2251799813685248
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 274877906944
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 274877906944
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
@ -625,8 +625,8 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 34359738368
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 34359738368
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
@ -639,8 +639,8 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 281474976710656
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 281474976710656
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 137438953472
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 137438953472
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
@ -651,7 +651,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@recur
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: call void @reca()
|
||||
// CHECK-NEXT: ret void
|
||||
@ -659,7 +659,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@main
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
||||
// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
|
||||
@ -670,7 +670,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@hoo
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[FP1:%.*]] = alloca ptr, align 8
|
||||
// CHECK-NEXT: [[FP2:%.*]] = alloca ptr, align 8
|
||||
@ -687,14 +687,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@unused_with_forward_default_decl._Mmops
|
||||
// CHECK-SAME: () #[[ATTR14:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR7]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_extern_forward_default_decl._Mdotprod
|
||||
// CHECK-SAME: () #[[ATTR15:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR3]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 0
|
||||
//
|
||||
@ -708,14 +708,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@unused_with_default_def._Msve
|
||||
// CHECK-SAME: () #[[ATTR16:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR15:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.default
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 1
|
||||
//
|
||||
@ -729,56 +729,56 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.default
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 1
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.default
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def._Mlse
|
||||
// CHECK-SAME: () #[[ATTR17:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR16:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 1
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@unused_without_default._Mrdm
|
||||
// CHECK-SAME: () #[[ATTR18:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR17:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.default
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 0
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mjscvt
|
||||
// CHECK-SAME: () #[[ATTR21:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR20:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 1
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mrdm
|
||||
// CHECK-SAME: () #[[ATTR18]] {
|
||||
// CHECK-SAME: () #[[ATTR17]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 2
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@caller
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[CALL:%.*]] = call i32 @used_def_without_default_decl()
|
||||
// CHECK-NEXT: [[CALL1:%.*]] = call i32 @used_decl_without_default_decl()
|
||||
@ -790,8 +790,8 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 131072
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 131072
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
@ -812,8 +812,8 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 131072
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 131072
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
@ -831,92 +831,92 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf64mmMpmullMsha1
|
||||
// CHECK-SAME: () #[[ATTR22:[0-9]+]] {
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._McryptoMf64mm
|
||||
// CHECK-SAME: () #[[ATTR21:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 1
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfcmaMfp16MrdmMsme
|
||||
// CHECK-SAME: () #[[ATTR23:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR22:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 2
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf32mmMi8mmMsha3
|
||||
// CHECK-SAME: () #[[ATTR24:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR23:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 12
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMsve-ebf16
|
||||
// CHECK-SAME: () #[[ATTR25:[0-9]+]] {
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msme2Mssbs
|
||||
// CHECK-SAME: () #[[ATTR8]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 8
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MdpbMrcpc2
|
||||
// CHECK-SAME: () #[[ATTR26:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR24:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 6
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mdpb2Mjscvt
|
||||
// CHECK-SAME: () #[[ATTR27:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR25:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 7
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfrinttsMrcpc
|
||||
// CHECK-SAME: () #[[ATTR28:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR26:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 3
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsveMsve-bf16
|
||||
// CHECK-SAME: () #[[ATTR29:[0-9]+]] {
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsmeMsve
|
||||
// CHECK-SAME: () #[[ATTR27:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 4
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2-aesMsve2-sha3
|
||||
// CHECK-SAME: () #[[ATTR30:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR28:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 5
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-bitpermMsve2-pmull128
|
||||
// CHECK-SAME: () #[[ATTR31:[0-9]+]] {
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-aesMsve2-bitperm
|
||||
// CHECK-SAME: () #[[ATTR29:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 9
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag2Msve2-sm4
|
||||
// CHECK-SAME: () #[[ATTR32:[0-9]+]] {
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMsve2-sm4
|
||||
// CHECK-SAME: () #[[ATTR30:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 10
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag3MmopsMrcpc3
|
||||
// CHECK-SAME: () #[[ATTR33:[0-9]+]] {
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMmopsMrcpc3
|
||||
// CHECK-SAME: () #[[ATTR31:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 11
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMdotprod
|
||||
// CHECK-SAME: () #[[ATTR15]] {
|
||||
// CHECK-SAME: () #[[ATTR3]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 13
|
||||
//
|
||||
@ -930,21 +930,21 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4
|
||||
// CHECK-SAME: () #[[ATTR34:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR32:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 15
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm
|
||||
// CHECK-SAME: () #[[ATTR35:[0-9]+]] {
|
||||
// CHECK-SAME: () #[[ATTR33:[0-9]+]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 16
|
||||
//
|
||||
//
|
||||
// CHECK: Function Attrs: noinline nounwind optnone
|
||||
// CHECK-LABEL: define {{[^@]+}}@fmv_inline.default
|
||||
// CHECK-SAME: () #[[ATTR11]] {
|
||||
// CHECK-SAME: () #[[ATTR13]] {
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 3
|
||||
//
|
||||
@ -953,8 +953,8 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1073741824
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1073741824
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33554432
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33554432
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
@ -967,8 +967,8 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 65536
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 65536
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 16384
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16384
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
@ -995,8 +995,8 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 131072
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 131072
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
@ -1132,39 +1132,37 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
|
||||
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+flagm,+fp16fml,+fullfp16,+neon,+rand,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+altnzcv,+bf16,+flagm,+sme,+sme-i16i64,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,+neon,+sha2,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+ls64,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp16fml,+fullfp16,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme2,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR9:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccpp,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sb,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+rdm,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR19:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+jsconv,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR20:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+rdm,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR21]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+jsconv,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR22]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+fullfp16,+neon,+rdm,+sme,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+fullfp16,+i8mm,+neon,+sha2,+sha3,+sve,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+dit,+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR26]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccpp,+rcpc,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR27]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccdp,+ccpp,+jsconv,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR28]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint,+rcpc,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR29]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR30]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-sha3,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR31]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-bitperm,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR32]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+mte,+neon,+sve,+sve2,+sve2-sm4,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR33]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,+mte,+rcpc,+rcpc3,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR34]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+sm4,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR35]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,+neon,+rdm,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sb,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+rdm,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR18:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+jsconv,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR19:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+rdm,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR20]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+jsconv,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR21]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fullfp16,+neon,+sha2,+sve,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR22]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+fullfp16,+neon,+rdm,+sme,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+fullfp16,+i8mm,+neon,+sha2,+sha3,+sve,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccpp,+rcpc,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccdp,+ccpp,+jsconv,+neon,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR26]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint,+rcpc,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR27]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+fullfp16,+neon,+sme,+sve,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR28]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-sha3,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR29]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-bitperm,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR30]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16,+neon,+sve,+sve2,+sve2-sm4,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR31]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,+rcpc,+rcpc3,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR32]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+neon,+sm4,-fp-armv8,-v9.5a" }
|
||||
// CHECK: attributes #[[ATTR33]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse,+neon,+rdm,-fp-armv8,-v9.5a" }
|
||||
//.
|
||||
// CHECK-NOFMV: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
|
||||
// CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals --include-generated-funcs
|
||||
// RUN: %clang_cc1 -std=c++11 -triple aarch64-linux-gnu -emit-llvm %s -o - | FileCheck %s
|
||||
|
||||
int __attribute__((target_clones("ls64_v+fp16", "default"))) foo_ovl(int) { return 1; }
|
||||
int __attribute__((target_clones("ls64_accdata+ls64"))) foo_ovl(void) { return 2; }
|
||||
int __attribute__((target_clones("ls64+fp16", "default"))) foo_ovl(int) { return 1; }
|
||||
int __attribute__((target_clones("sme+ls64"))) foo_ovl(void) { return 2; }
|
||||
|
||||
int bar() {
|
||||
return foo_ovl(1) + foo_ovl();
|
||||
@ -35,9 +35,6 @@ void run_foo_tml() {
|
||||
Mc4.foo_tml();
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
//.
|
||||
// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
|
||||
// CHECK: @_Z7foo_ovli.ifunc = weak_odr alias i32 (i32), ptr @_Z7foo_ovli
|
||||
@ -49,7 +46,7 @@ void run_foo_tml() {
|
||||
// CHECK: @_ZN7MyClassIssE7foo_tmlEv = weak_odr ifunc i32 (ptr), ptr @_ZN7MyClassIssE7foo_tmlEv.resolver
|
||||
// CHECK: @_ZN7MyClassIisE7foo_tmlEv = weak_odr ifunc i32 (ptr), ptr @_ZN7MyClassIisE7foo_tmlEv.resolver
|
||||
//.
|
||||
// CHECK-LABEL: @_Z7foo_ovli._Mfp16Mls64_v(
|
||||
// CHECK-LABEL: @_Z7foo_ovli._Mfp16Mls64(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
||||
// CHECK-NEXT: store i32 [[TMP0:%.*]], ptr [[DOTADDR]], align 4
|
||||
@ -60,17 +57,17 @@ void run_foo_tml() {
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4503599627436032
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4503599627436032
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 274877923328
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 274877923328
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
// CHECK-NEXT: ret ptr @_Z7foo_ovli._Mfp16Mls64_v
|
||||
// CHECK-NEXT: ret ptr @_Z7foo_ovli._Mfp16Mls64
|
||||
// CHECK: resolver_else:
|
||||
// CHECK-NEXT: ret ptr @_Z7foo_ovli.default
|
||||
//
|
||||
//
|
||||
// CHECK-LABEL: @_Z7foo_ovlv._Mls64Mls64_accdata(
|
||||
// CHECK-LABEL: @_Z7foo_ovlv._Mls64Msme(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 2
|
||||
//
|
||||
@ -79,12 +76,12 @@ void run_foo_tml() {
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 11258999068426240
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 11258999068426240
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 283467841536
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 283467841536
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
// CHECK-NEXT: ret ptr @_Z7foo_ovlv._Mls64Mls64_accdata
|
||||
// CHECK-NEXT: ret ptr @_Z7foo_ovlv._Mls64Msme
|
||||
// CHECK: resolver_else:
|
||||
// CHECK-NEXT: ret ptr @_Z7foo_ovlv.default
|
||||
//
|
||||
@ -114,16 +111,16 @@ void run_foo_tml() {
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36310271995674624
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36310271995674624
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1236950581248
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1236950581248
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
// CHECK-NEXT: ret ptr @_ZN7MyClassIssE7foo_tmlEv._Msme-f64f64Mssbs
|
||||
// CHECK: resolver_else:
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 16777216
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 16777216
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 2097152
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2097152
|
||||
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
|
||||
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
|
||||
// CHECK: resolver_return1:
|
||||
@ -136,16 +133,16 @@ void run_foo_tml() {
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36310271995674624
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36310271995674624
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1236950581248
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1236950581248
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
// CHECK-NEXT: ret ptr @_ZN7MyClassIisE7foo_tmlEv._Msme-f64f64Mssbs
|
||||
// CHECK: resolver_else:
|
||||
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 16777216
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 16777216
|
||||
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 2097152
|
||||
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 2097152
|
||||
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
|
||||
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
|
||||
// CHECK: resolver_return1:
|
||||
@ -231,7 +228,7 @@ void run_foo_tml() {
|
||||
//
|
||||
//.
|
||||
// CHECK: attributes #[[ATTR0:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
|
||||
// CHECK: attributes #[[ATTR1:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ls64" }
|
||||
// CHECK: attributes #[[ATTR1:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme" }
|
||||
// CHECK: attributes #[[ATTR2:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
|
||||
// CHECK: attributes #[[ATTR3:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint" }
|
||||
// CHECK: attributes #[[ATTR4:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme-f64f64" }
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
|
||||
int __attribute__((target_version("sme-f64f64+bf16"))) foo(int) { return 1; }
|
||||
int __attribute__((target_version("default"))) foo(int) { return 2; }
|
||||
int __attribute__((target_version("sm4+ebf16"))) foo(void) { return 3; }
|
||||
int __attribute__((target_version("sm4+bf16"))) foo(void) { return 3; }
|
||||
int __attribute__((target_version("default"))) foo(void) { return 4; }
|
||||
|
||||
struct MyClass {
|
||||
@ -89,7 +89,7 @@ int bar() {
|
||||
// CHECK-NEXT: ret i32 2
|
||||
//
|
||||
//
|
||||
// CHECK-LABEL: @_Z3foov._Mebf16Msm4(
|
||||
// CHECK-LABEL: @_Z3foov._Mbf16Msm4(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: ret i32 3
|
||||
//
|
||||
@ -246,8 +246,8 @@ int bar() {
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 36028797153181696
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 36028797153181696
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1099520016384
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1099520016384
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
@ -260,12 +260,12 @@ int bar() {
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435488
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435488
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 8388640
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 8388640
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
// CHECK-NEXT: ret ptr @_Z3foov._Mebf16Msm4
|
||||
// CHECK-NEXT: ret ptr @_Z3foov._Mbf16Msm4
|
||||
// CHECK: resolver_else:
|
||||
// CHECK-NEXT: ret ptr @_Z3foov.default
|
||||
//
|
||||
@ -274,8 +274,8 @@ int bar() {
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1073741824
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1073741824
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 33554432
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 33554432
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
@ -288,8 +288,8 @@ int bar() {
|
||||
// CHECK-NEXT: resolver_entry:
|
||||
// CHECK-NEXT: call void @__init_cpu_features_resolver()
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 65536
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 65536
|
||||
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 16384
|
||||
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 16384
|
||||
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
|
||||
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
|
||||
// CHECK: resolver_return:
|
||||
|
||||
@ -20,7 +20,7 @@ int test_aarch64_features(void) {
|
||||
// expected-warning@+1 {{invalid cpu feature string}}
|
||||
if (__builtin_cpu_supports("default"))
|
||||
return 6;
|
||||
if (__builtin_cpu_supports(" ssbs + bti "))
|
||||
if (__builtin_cpu_supports(" ssbs + crc "))
|
||||
return 7;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -9,7 +9,7 @@ void __attribute__((target_clones("ssbs+ls64"))) warn2(void);
|
||||
|
||||
// expected-error@+2 {{'target_clones' and 'target_version' attributes are not compatible}}
|
||||
// expected-note@+1 {{conflicting attribute is here}}
|
||||
void __attribute__((target_version("sve-bf16"), target_clones("sme+memtag"))) not_compat(void);
|
||||
void __attribute__((target_version("bf16"), target_clones("sme+memtag"))) not_compat(void);
|
||||
|
||||
int redecl(void);
|
||||
int __attribute__((target_clones("frintts", "simd+fp", "default"))) redecl(void) { return 1; }
|
||||
@ -21,26 +21,25 @@ int __attribute__((target_clones("sve+dotprod"))) redecl3(void);
|
||||
int redecl3(void);
|
||||
|
||||
int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void);
|
||||
// expected-error@+3 {{'target_clones' attribute does not match previous declaration}}
|
||||
// expected-error@+2 {{'target_clones' attribute does not match previous declaration}}
|
||||
// expected-note@-2 {{previous declaration is here}}
|
||||
// expected-warning@+1 {{version list contains entries that don't impact code generation}}
|
||||
int __attribute__((target_clones("dgh+memtag+rpres+ls64_v", "ebf16+dpb+sha1", "default"))) redecl4(void) { return 1; }
|
||||
int __attribute__((target_clones("dpb2+memtag+rpres+ls64", "bf16+dpb+sha2", "default"))) redecl4(void) { return 1; }
|
||||
|
||||
int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
|
||||
// expected-error@+2 {{multiversioned function redeclarations require identical target attributes}}
|
||||
// expected-note@-2 {{previous declaration is here}}
|
||||
int __attribute__((target_clones("flagm2", "default"))) redef2(void) { return 1; }
|
||||
|
||||
int __attribute__((target_clones("f32mm", "f64mm", "sha1+fp"))) redef3(void) { return 1; }
|
||||
int __attribute__((target_clones("f32mm", "f64mm", "sha3+fp"))) redef3(void) { return 1; }
|
||||
// expected-error@+2 {{'target_clones' attribute does not match previous declaration}}
|
||||
// expected-note@-2 {{previous declaration is here}}
|
||||
int __attribute__((target_clones("f32mm", "sha1+fp", "f64mm"))) redef3(void) { return 1; }
|
||||
int __attribute__((target_clones("f32mm", "sha3+fp", "f64mm"))) redef3(void) { return 1; }
|
||||
|
||||
int __attribute__((target_clones("rdm+lse+rdm", "lse+rdm"))) dup1(void) { return 1; }
|
||||
// expected-warning@+1 {{version list contains duplicate entries}}
|
||||
int __attribute__((target_clones("rdm+lse+rdm", "rdm+lse+rdm"))) dup2(void) { return 2; }
|
||||
// expected-warning@+1 {{version list contains duplicate entries}}
|
||||
int __attribute__((target_clones("rcpc2+sve2-pmull128", "rcpc2+sve2-pmull128"))) dup3(void) { return 3; }
|
||||
int __attribute__((target_clones("rcpc2+sve2-aes", "rcpc2+sve2-aes"))) dup3(void) { return 3; }
|
||||
// expected-warning@+1 {{version list contains duplicate entries}}
|
||||
void __attribute__((target_clones("sha3", "default", "default"))) dup4(void);
|
||||
// expected-warning@+2 {{version list contains duplicate entries}}
|
||||
@ -49,7 +48,7 @@ int __attribute__((target_clones("fp", "fp", "crc+dotprod", "dotprod+crc"))) dup
|
||||
|
||||
// expected-warning@+1 {{version list contains duplicate entries}}
|
||||
int __attribute__((target_clones("fp16+memtag", "memtag+fp16"))) dup6(void) { return 6; }
|
||||
int __attribute__((target_clones("simd+ssbs2", "simd+dpb2"))) dup7(void) { return 7; }
|
||||
int __attribute__((target_clones("simd+ssbs", "simd+dpb2"))) dup7(void) { return 7; }
|
||||
|
||||
// expected-warning@+1 {{unsupported '' in the 'target_clones' attribute string;}}
|
||||
void __attribute__((target_clones(""))) empty_target_1(void);
|
||||
@ -72,13 +71,13 @@ empty_target_5(void);
|
||||
void __attribute__((target_clones("sve2-bitperm", "sve2-bitperm")))
|
||||
dupe_normal(void);
|
||||
|
||||
void __attribute__((target_clones("default"), target_clones("memtag3+bti"))) dupe_normal2(void);
|
||||
void __attribute__((target_clones("default"), target_clones("memtag+mops"))) dupe_normal2(void);
|
||||
|
||||
int mv_after_use(void);
|
||||
int useage(void) {
|
||||
return mv_after_use();
|
||||
}
|
||||
// expected-error@+1 {{function declaration cannot become a multiversioned function after first usage}}
|
||||
int __attribute__((target_clones("sve2-sha3+ssbs2", "sm4"))) mv_after_use(void) { return 1; }
|
||||
int __attribute__((target_clones("sve2-sha3+ssbs", "sm4"))) mv_after_use(void) { return 1; }
|
||||
// expected-error@+1 {{'main' cannot be a multiversioned function}}
|
||||
int __attribute__((target_clones("sve-i8mm"))) main() { return 1; }
|
||||
int __attribute__((target_clones("sve2-aes"))) main() { return 1; }
|
||||
|
||||
@ -16,7 +16,7 @@ int __attribute__((target_version("aes"))) foo(void) { return 1; }
|
||||
int __attribute__((target_version("default"))) foo(void) { return 2; }
|
||||
|
||||
//expected-note@+1 {{previous definition is here}}
|
||||
int __attribute__((target_version("sha3 + pmull "))) foo(void) { return 1; }
|
||||
int __attribute__((target_version("sha3 + aes "))) foo(void) { return 1; }
|
||||
//expected-note@-1 {{previous definition is here}}
|
||||
|
||||
//expected-error@+1 {{redefinition of 'foo'}}
|
||||
@ -32,11 +32,11 @@ __attribute__ ((target("bf16,sve,sve2,dotprod"))) int func(void) { return 1; }
|
||||
__attribute__ ((target("default"))) int func(void) { return 0; }
|
||||
|
||||
//expected-note@+1 {{previous declaration is here}}
|
||||
void __attribute__((target_version("bti+flagm2"))) one(void) {}
|
||||
void __attribute__((target_version("mops+flagm2"))) one(void) {}
|
||||
//expected-error@+1 {{multiversioned function redeclarations require identical target attributes}}
|
||||
void __attribute__((target_version("flagm2+bti"))) one(void) {}
|
||||
void __attribute__((target_version("flagm2+mops"))) one(void) {}
|
||||
|
||||
void __attribute__((target_version("ssbs+sha1"))) two(void) {}
|
||||
void __attribute__((target_version("ssbs+sha2"))) two(void) {}
|
||||
void __attribute__((target_version("ssbs+fp16fml"))) two(void) {}
|
||||
|
||||
//expected-error@+1 {{'main' cannot be a multiversioned function}}
|
||||
@ -44,7 +44,7 @@ int __attribute__((target_version("lse"))) main(void) { return 1; }
|
||||
|
||||
// It is ok for the default version to appear first.
|
||||
int default_first(void) { return 1; }
|
||||
int __attribute__((target_version("dit"))) default_first(void) { return 2; }
|
||||
int __attribute__((target_version("crc"))) default_first(void) { return 2; }
|
||||
int __attribute__((target_version("mops"))) default_first(void) { return 3; }
|
||||
|
||||
// It is ok if the default version is between other versions.
|
||||
@ -77,7 +77,7 @@ void __attribute__((target_version("rdm+rng+crc"))) redef(void) {}
|
||||
void __attribute__((target_version("rdm+rng+crc"))) redef(void) {}
|
||||
|
||||
int def(void);
|
||||
void __attribute__((target_version("dit"))) nodef(void);
|
||||
void __attribute__((target_version("crc"))) nodef(void);
|
||||
void __attribute__((target_version("ls64"))) nodef(void);
|
||||
void __attribute__((target_version("aes"))) ovl(void);
|
||||
void __attribute__((target_version("default"))) ovl(void);
|
||||
@ -89,12 +89,12 @@ int bar() {
|
||||
return def();
|
||||
}
|
||||
// expected-error@+1 {{function declaration cannot become a multiversioned function after first usage}}
|
||||
int __attribute__((target_version("sha1"))) def(void) { return 1; }
|
||||
int __attribute__((target_version("sha3"))) def(void) { return 1; }
|
||||
|
||||
int __attribute__((target_version("sve"))) prot();
|
||||
// expected-error@-1 {{multiversioned function must have a prototype}}
|
||||
|
||||
int __attribute__((target_version("pmull"))) rtype(int);
|
||||
int __attribute__((target_version("aes"))) rtype(int);
|
||||
// expected-error@+1 {{multiversioned function declaration has a different return type}}
|
||||
float __attribute__((target_version("rdm"))) rtype(int);
|
||||
|
||||
@ -102,7 +102,7 @@ int __attribute__((target_version("sha2"))) combine(void) { return 1; }
|
||||
// expected-error@+1 {{multiversioned function declaration has a different calling convention}}
|
||||
int __attribute__((aarch64_vector_pcs, target_version("sha3"))) combine(void) { return 2; }
|
||||
|
||||
int __attribute__((target_version("fp+aes+pmull+rcpc"))) unspec_args() { return -1; }
|
||||
int __attribute__((target_version("fp+aes+sha3+rcpc"))) unspec_args() { return -1; }
|
||||
// expected-error@-1 {{multiversioned function must have a prototype}}
|
||||
// expected-error@+1 {{multiversioned function must have a prototype}}
|
||||
int __attribute__((target_version("default"))) unspec_args() { return 0; }
|
||||
|
||||
@ -25,13 +25,13 @@ int __attribute__((target_version("dpb"))) diff_link(void);
|
||||
|
||||
int __attribute__((target_version("memtag"))) diff_link1(void) { return 1; }
|
||||
//expected-error@+1 {{multiversioned function declaration has a different linkage}}
|
||||
static int __attribute__((target_version("bti"))) diff_link1(void);
|
||||
static int __attribute__((target_version("mops"))) diff_link1(void);
|
||||
|
||||
int __attribute__((target_version("flagm2"))) diff_link2(void) { return 1; }
|
||||
extern int __attribute__((target_version("flagm"))) diff_link2(void);
|
||||
|
||||
namespace {
|
||||
static int __attribute__((target_version("memtag3"))) diff_link2(void) { return 2; }
|
||||
static int __attribute__((target_version("memtag"))) diff_link2(void) { return 2; }
|
||||
int __attribute__((target_version("sve2-bitperm"))) diff_link2(void) { return 1; }
|
||||
} // namespace
|
||||
|
||||
@ -49,7 +49,7 @@ double __attribute__((target_version("rcpc"))) diff_type1(void);
|
||||
|
||||
auto __attribute__((target_version("rcpc2"))) diff_type2(void) -> int { return 1; }
|
||||
//expected-error@+1 {{multiversioned function declaration has a different return type}}
|
||||
auto __attribute__((target_version("sve-bf16"))) diff_type2(void) -> long { return (long)1; }
|
||||
auto __attribute__((target_version("sve2-aes"))) diff_type2(void) -> long { return (long)1; }
|
||||
|
||||
int __attribute__((target_version("fp16fml"))) diff_type3(void) noexcept(false) { return 1; }
|
||||
//expected-error@+2 {{exception specification in declaration does not match previous declaration}}
|
||||
@ -75,7 +75,7 @@ auto __attribute__((target_version("dpb2"))) ret3(void) -> int { return 1; }
|
||||
class Cls {
|
||||
__attribute__((target_version("rng"))) Cls();
|
||||
// expected-error@-1 {{attribute 'target_version' multiversioned functions do not yet support constructors}}
|
||||
__attribute__((target_version("sve-i8mm"))) ~Cls();
|
||||
__attribute__((target_version("sve2-aes"))) ~Cls();
|
||||
// expected-error@-1 {{attribute 'target_version' multiversioned functions do not yet support destructors}}
|
||||
|
||||
Cls &__attribute__((target_version("f32mm"))) operator=(const Cls &) = default;
|
||||
@ -98,11 +98,11 @@ __attribute__((target_version("jscvt"))) void Decl();
|
||||
} // namespace Nms
|
||||
|
||||
class Out {
|
||||
int __attribute__((target_version("bti"))) func(void);
|
||||
int __attribute__((target_version("ssbs2"))) func(void);
|
||||
int __attribute__((target_version("mops"))) func(void);
|
||||
int __attribute__((target_version("ssbs"))) func(void);
|
||||
};
|
||||
int __attribute__((target_version("bti"))) Out::func(void) { return 1; }
|
||||
int __attribute__((target_version("ssbs2"))) Out::func(void) { return 2; }
|
||||
int __attribute__((target_version("mops"))) Out::func(void) { return 1; }
|
||||
int __attribute__((target_version("ssbs"))) Out::func(void) { return 2; }
|
||||
// expected-error@+3 {{out-of-line definition of 'func' does not match any declaration in 'Out'}}
|
||||
// expected-note@-3 {{member declaration nearly matches}}
|
||||
// expected-note@-3 {{member declaration nearly matches}}
|
||||
|
||||
@ -67,13 +67,10 @@ enum CPUFeatures {
|
||||
FEAT_FP,
|
||||
FEAT_SIMD,
|
||||
FEAT_CRC,
|
||||
FEAT_SHA1,
|
||||
FEAT_SHA2,
|
||||
FEAT_SHA3,
|
||||
FEAT_AES,
|
||||
FEAT_PMULL,
|
||||
FEAT_FP16,
|
||||
FEAT_DIT,
|
||||
FEAT_DPB,
|
||||
FEAT_DPB2,
|
||||
FEAT_JSCVT,
|
||||
@ -81,35 +78,23 @@ enum CPUFeatures {
|
||||
FEAT_RCPC,
|
||||
FEAT_RCPC2,
|
||||
FEAT_FRINTTS,
|
||||
FEAT_DGH,
|
||||
FEAT_I8MM,
|
||||
FEAT_BF16,
|
||||
FEAT_EBF16,
|
||||
FEAT_RPRES,
|
||||
FEAT_SVE,
|
||||
FEAT_SVE_BF16,
|
||||
FEAT_SVE_EBF16,
|
||||
FEAT_SVE_I8MM,
|
||||
FEAT_SVE_F32MM,
|
||||
FEAT_SVE_F64MM,
|
||||
FEAT_SVE2,
|
||||
FEAT_SVE_AES,
|
||||
FEAT_SVE_PMULL128,
|
||||
FEAT_SVE_BITPERM,
|
||||
FEAT_SVE_SHA3,
|
||||
FEAT_SVE_SM4,
|
||||
FEAT_SME,
|
||||
FEAT_MEMTAG,
|
||||
FEAT_MEMTAG2,
|
||||
FEAT_MEMTAG3,
|
||||
FEAT_SB,
|
||||
FEAT_PREDRES,
|
||||
FEAT_SSBS,
|
||||
FEAT_SSBS2,
|
||||
FEAT_BTI,
|
||||
FEAT_LS64,
|
||||
FEAT_LS64_V,
|
||||
FEAT_LS64_ACCDATA,
|
||||
FEAT_WFXT,
|
||||
FEAT_SME_F64,
|
||||
FEAT_SME_I64,
|
||||
@ -117,7 +102,7 @@ enum CPUFeatures {
|
||||
FEAT_RCPC3,
|
||||
FEAT_MOPS,
|
||||
FEAT_MAX,
|
||||
FEAT_EXT = 62, // Reserved to indicate presence of additional features field
|
||||
FEAT_EXT = 47, // Reserved to indicate presence of additional features field
|
||||
// in __aarch64_cpu_features
|
||||
FEAT_INIT // Used as flag of features initialization completion
|
||||
};
|
||||
|
||||
@ -35,13 +35,10 @@ void __init_cpu_features_resolver(void) {
|
||||
{"hw.optional.floatingpoint", FEAT_FP},
|
||||
{"hw.optional.AdvSIMD", FEAT_SIMD},
|
||||
{"hw.optional.armv8_crc32", FEAT_CRC},
|
||||
{"hw.optional.arm.FEAT_SHA1", FEAT_SHA1},
|
||||
{"hw.optional.arm.FEAT_SHA256", FEAT_SHA2},
|
||||
{"hw.optional.arm.FEAT_SHA3", FEAT_SHA3},
|
||||
{"hw.optional.arm.FEAT_AES", FEAT_AES},
|
||||
{"hw.optional.arm.FEAT_PMULL", FEAT_PMULL},
|
||||
{"hw.optional.arm.FEAT_FP16", FEAT_FP16},
|
||||
{"hw.optional.arm.FEAT_DIT", FEAT_DIT},
|
||||
{"hw.optional.arm.FEAT_DPB", FEAT_DPB},
|
||||
{"hw.optional.arm.FEAT_DPB2", FEAT_DPB2},
|
||||
{"hw.optional.arm.FEAT_JSCVT", FEAT_JSCVT},
|
||||
@ -53,8 +50,7 @@ void __init_cpu_features_resolver(void) {
|
||||
{"hw.optional.arm.FEAT_BF16", FEAT_BF16},
|
||||
{"hw.optional.arm.FEAT_SB", FEAT_SB},
|
||||
{"hw.optional.arm.FEAT_SPECRES", FEAT_PREDRES},
|
||||
{"hw.optional.arm.FEAT_SSBS", FEAT_SSBS2},
|
||||
{"hw.optional.arm.FEAT_BTI", FEAT_BTI},
|
||||
{"hw.optional.arm.FEAT_SSBS", FEAT_SSBS},
|
||||
};
|
||||
|
||||
for (size_t I = 0, E = sizeof(feature_checks) / sizeof(feature_checks[0]);
|
||||
|
||||
@ -22,10 +22,6 @@ void __init_cpu_features_resolver() {
|
||||
setCPUFeature(FEAT_SIMD);
|
||||
if (features & ZX_ARM64_FEATURE_ISA_AES)
|
||||
setCPUFeature(FEAT_AES);
|
||||
if (features & ZX_ARM64_FEATURE_ISA_PMULL)
|
||||
setCPUFeature(FEAT_PMULL);
|
||||
if (features & ZX_ARM64_FEATURE_ISA_SHA1)
|
||||
setCPUFeature(FEAT_SHA1);
|
||||
if (features & ZX_ARM64_FEATURE_ISA_SHA256)
|
||||
setCPUFeature(FEAT_SHA2);
|
||||
if (features & ZX_ARM64_FEATURE_ISA_CRC32)
|
||||
|
||||
@ -16,8 +16,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
|
||||
hwcap2 = arg->_hwcap2;
|
||||
if (hwcap & HWCAP_CRC32)
|
||||
setCPUFeature(FEAT_CRC);
|
||||
if (hwcap & HWCAP_PMULL)
|
||||
setCPUFeature(FEAT_PMULL);
|
||||
if (hwcap & HWCAP_FLAGM)
|
||||
setCPUFeature(FEAT_FLAGM);
|
||||
if (hwcap2 & HWCAP2_FLAGM2) {
|
||||
@ -34,16 +32,12 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
|
||||
setCPUFeature(FEAT_FP16);
|
||||
setCPUFeature(FEAT_FP);
|
||||
}
|
||||
if (hwcap & HWCAP_DIT)
|
||||
setCPUFeature(FEAT_DIT);
|
||||
if (hwcap & HWCAP_ASIMDRDM)
|
||||
setCPUFeature(FEAT_RDM);
|
||||
if (hwcap & HWCAP_ILRCPC)
|
||||
setCPUFeature(FEAT_RCPC2);
|
||||
if (hwcap & HWCAP_AES)
|
||||
setCPUFeature(FEAT_AES);
|
||||
if (hwcap & HWCAP_SHA1)
|
||||
setCPUFeature(FEAT_SHA1);
|
||||
if (hwcap & HWCAP_SHA2)
|
||||
setCPUFeature(FEAT_SHA2);
|
||||
if (hwcap & HWCAP_JSCVT)
|
||||
@ -53,22 +47,11 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
|
||||
if (hwcap & HWCAP_SB)
|
||||
setCPUFeature(FEAT_SB);
|
||||
if (hwcap & HWCAP_SSBS)
|
||||
setCPUFeature(FEAT_SSBS2);
|
||||
if (hwcap2 & HWCAP2_MTE) {
|
||||
setCPUFeature(FEAT_SSBS);
|
||||
if (hwcap2 & HWCAP2_MTE)
|
||||
setCPUFeature(FEAT_MEMTAG);
|
||||
setCPUFeature(FEAT_MEMTAG2);
|
||||
}
|
||||
if (hwcap2 & HWCAP2_MTE3) {
|
||||
setCPUFeature(FEAT_MEMTAG);
|
||||
setCPUFeature(FEAT_MEMTAG2);
|
||||
setCPUFeature(FEAT_MEMTAG3);
|
||||
}
|
||||
if (hwcap2 & HWCAP2_SVEAES)
|
||||
setCPUFeature(FEAT_SVE_AES);
|
||||
if (hwcap2 & HWCAP2_SVEPMULL) {
|
||||
setCPUFeature(FEAT_SVE_AES);
|
||||
setCPUFeature(FEAT_SVE_PMULL128);
|
||||
}
|
||||
if (hwcap2 & HWCAP2_SVEBITPERM)
|
||||
setCPUFeature(FEAT_SVE_BITPERM);
|
||||
if (hwcap2 & HWCAP2_SVESHA3)
|
||||
@ -83,22 +66,12 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
|
||||
setCPUFeature(FEAT_RNG);
|
||||
if (hwcap2 & HWCAP2_I8MM)
|
||||
setCPUFeature(FEAT_I8MM);
|
||||
if (hwcap2 & HWCAP2_EBF16)
|
||||
setCPUFeature(FEAT_EBF16);
|
||||
if (hwcap2 & HWCAP2_SVE_EBF16)
|
||||
setCPUFeature(FEAT_SVE_EBF16);
|
||||
if (hwcap2 & HWCAP2_DGH)
|
||||
setCPUFeature(FEAT_DGH);
|
||||
if (hwcap2 & HWCAP2_FRINT)
|
||||
setCPUFeature(FEAT_FRINTTS);
|
||||
if (hwcap2 & HWCAP2_SVEI8MM)
|
||||
setCPUFeature(FEAT_SVE_I8MM);
|
||||
if (hwcap2 & HWCAP2_SVEF32MM)
|
||||
setCPUFeature(FEAT_SVE_F32MM);
|
||||
if (hwcap2 & HWCAP2_SVEF64MM)
|
||||
setCPUFeature(FEAT_SVE_F64MM);
|
||||
if (hwcap2 & HWCAP2_BTI)
|
||||
setCPUFeature(FEAT_BTI);
|
||||
if (hwcap2 & HWCAP2_RPRES)
|
||||
setCPUFeature(FEAT_RPRES);
|
||||
if (hwcap2 & HWCAP2_WFXT)
|
||||
@ -141,9 +114,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
|
||||
// ID_AA64ZFR0_EL1.SVEver == 0b0001
|
||||
if (extractBits(ftr, 0, 4) == 0x1)
|
||||
setCPUFeature(FEAT_SVE2);
|
||||
// ID_AA64ZFR0_EL1.BF16 != 0b0000
|
||||
if (extractBits(ftr, 20, 4) != 0x0)
|
||||
setCPUFeature(FEAT_SVE_BF16);
|
||||
}
|
||||
getCPUFeature(ID_AA64ISAR0_EL1, ftr);
|
||||
// ID_AA64ISAR0_EL1.SHA3 != 0b0000
|
||||
@ -168,12 +138,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
|
||||
// ID_AA64ISAR1_EL1.LS64 >= 0b0001
|
||||
if (extractBits(ftr, 60, 4) >= 0x1)
|
||||
setCPUFeature(FEAT_LS64);
|
||||
// ID_AA64ISAR1_EL1.LS64 >= 0b0010
|
||||
if (extractBits(ftr, 60, 4) >= 0x2)
|
||||
setCPUFeature(FEAT_LS64_V);
|
||||
// ID_AA64ISAR1_EL1.LS64 >= 0b0011
|
||||
if (extractBits(ftr, 60, 4) >= 0x3)
|
||||
setCPUFeature(FEAT_LS64_ACCDATA);
|
||||
} else {
|
||||
// Set some features in case of no CPUID support
|
||||
if (hwcap & (HWCAP_FP | HWCAP_FPHP)) {
|
||||
@ -187,8 +151,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
|
||||
setCPUFeature(FEAT_RCPC);
|
||||
if (hwcap2 & HWCAP2_BF16 || hwcap2 & HWCAP2_EBF16)
|
||||
setCPUFeature(FEAT_BF16);
|
||||
if (hwcap2 & HWCAP2_SVEBF16)
|
||||
setCPUFeature(FEAT_SVE_BF16);
|
||||
if (hwcap2 & HWCAP2_SVE2 && hwcap & HWCAP_SVE)
|
||||
setCPUFeature(FEAT_SVE2);
|
||||
if (hwcap & HWCAP_SHA3)
|
||||
|
||||
@ -46,13 +46,10 @@ enum CPUFeatures {
|
||||
FEAT_FP,
|
||||
FEAT_SIMD,
|
||||
FEAT_CRC,
|
||||
FEAT_SHA1,
|
||||
FEAT_SHA2,
|
||||
FEAT_SHA3,
|
||||
FEAT_AES,
|
||||
FEAT_PMULL,
|
||||
FEAT_FP16,
|
||||
FEAT_DIT,
|
||||
FEAT_DPB,
|
||||
FEAT_DPB2,
|
||||
FEAT_JSCVT,
|
||||
@ -60,35 +57,23 @@ enum CPUFeatures {
|
||||
FEAT_RCPC,
|
||||
FEAT_RCPC2,
|
||||
FEAT_FRINTTS,
|
||||
FEAT_DGH,
|
||||
FEAT_I8MM,
|
||||
FEAT_BF16,
|
||||
FEAT_EBF16,
|
||||
FEAT_RPRES,
|
||||
FEAT_SVE,
|
||||
FEAT_SVE_BF16,
|
||||
FEAT_SVE_EBF16,
|
||||
FEAT_SVE_I8MM,
|
||||
FEAT_SVE_F32MM,
|
||||
FEAT_SVE_F64MM,
|
||||
FEAT_SVE2,
|
||||
FEAT_SVE_AES,
|
||||
FEAT_SVE_PMULL128,
|
||||
FEAT_SVE_BITPERM,
|
||||
FEAT_SVE_SHA3,
|
||||
FEAT_SVE_SM4,
|
||||
FEAT_SME,
|
||||
FEAT_MEMTAG,
|
||||
FEAT_MEMTAG2,
|
||||
FEAT_MEMTAG3,
|
||||
FEAT_SB,
|
||||
FEAT_PREDRES,
|
||||
FEAT_SSBS,
|
||||
FEAT_SSBS2,
|
||||
FEAT_BTI,
|
||||
FEAT_LS64,
|
||||
FEAT_LS64_V,
|
||||
FEAT_LS64_ACCDATA,
|
||||
FEAT_WFXT,
|
||||
FEAT_SME_F64,
|
||||
FEAT_SME_I64,
|
||||
@ -96,12 +81,12 @@ enum CPUFeatures {
|
||||
FEAT_RCPC3,
|
||||
FEAT_MOPS,
|
||||
FEAT_MAX,
|
||||
FEAT_EXT = 62,
|
||||
FEAT_EXT = 47,
|
||||
FEAT_INIT
|
||||
};
|
||||
|
||||
static_assert(FEAT_MAX < 62,
|
||||
"Number of features in CPUFeatures are limited to 62 entries");
|
||||
static_assert(FEAT_MAX < 47,
|
||||
"Number of features in CPUFeatures are limited to 47 entries");
|
||||
|
||||
// Arch extension modifiers for CPUs. These are labelled with their Arm ARM
|
||||
// feature name (though the canonical reference for those is AArch64.td)
|
||||
@ -215,17 +200,13 @@ inline constexpr ExtensionInfo Extensions[] = {
|
||||
{"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_INIT, "", 0},
|
||||
{"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280},
|
||||
{"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_INIT, "", 0},
|
||||
{"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510},
|
||||
{"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110},
|
||||
{"crypto", AArch64::AEK_CRYPTO, "+crypto", "-crypto", FEAT_INIT, "+aes,+sha2", 0},
|
||||
{"cssc", AArch64::AEK_CSSC, "+cssc", "-cssc", FEAT_INIT, "", 0},
|
||||
{"d128", AArch64::AEK_D128, "+d128", "-d128", FEAT_INIT, "", 0},
|
||||
{"dgh", AArch64::AEK_NONE, {}, {}, FEAT_DGH, "", 260},
|
||||
{"dit", AArch64::AEK_NONE, {}, {}, FEAT_DIT, "+dit", 180},
|
||||
{"dotprod", AArch64::AEK_DOTPROD, "+dotprod", "-dotprod", FEAT_DOTPROD, "+dotprod,+fp-armv8,+neon", 104},
|
||||
{"dpb", AArch64::AEK_NONE, {}, {}, FEAT_DPB, "+ccpp", 190},
|
||||
{"dpb2", AArch64::AEK_NONE, {}, {}, FEAT_DPB2, "+ccpp,+ccdp", 200},
|
||||
{"ebf16", AArch64::AEK_NONE, {}, {}, FEAT_EBF16, "+bf16", 290},
|
||||
{"f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32mm", FEAT_SVE_F32MM, "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350},
|
||||
{"f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm", FEAT_SVE_F64MM, "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360},
|
||||
{"fcma", AArch64::AEK_FCMA, "+complxnum", "-complxnum", FEAT_FCMA, "+fp-armv8,+neon,+complxnum", 220},
|
||||
@ -239,17 +220,12 @@ inline constexpr ExtensionInfo Extensions[] = {
|
||||
{"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270},
|
||||
{"ite", AArch64::AEK_ITE, "+ite", "-ite", FEAT_INIT, "", 0},
|
||||
{"jscvt", AArch64::AEK_JSCVT, "+jsconv", "-jsconv", FEAT_JSCVT, "+fp-armv8,+neon,+jsconv", 210},
|
||||
{"ls64_accdata", AArch64::AEK_NONE, {}, {}, FEAT_LS64_ACCDATA, "+ls64", 540},
|
||||
{"ls64_v", AArch64::AEK_NONE, {}, {}, FEAT_LS64_V, "", 530},
|
||||
{"ls64", AArch64::AEK_LS64, "+ls64", "-ls64", FEAT_LS64, "", 520},
|
||||
{"lse", AArch64::AEK_LSE, "+lse", "-lse", FEAT_LSE, "+lse", 80},
|
||||
{"lse128", AArch64::AEK_LSE128, "+lse128", "-lse128", FEAT_INIT, "", 0},
|
||||
{"memtag", AArch64::AEK_MTE, "+mte", "-mte", FEAT_MEMTAG, "", 440},
|
||||
{"memtag2", AArch64::AEK_NONE, {}, {}, FEAT_MEMTAG2, "+mte", 450},
|
||||
{"memtag3", AArch64::AEK_NONE, {}, {}, FEAT_MEMTAG3, "+mte", 460},
|
||||
{"mops", AArch64::AEK_MOPS, "+mops", "-mops", FEAT_MOPS, "+mops", 650},
|
||||
{"pauth", AArch64::AEK_PAUTH, "+pauth", "-pauth", FEAT_INIT, "", 0},
|
||||
{"pmull", AArch64::AEK_NONE, {}, {}, FEAT_PMULL, "+aes,+fp-armv8,+neon", 160},
|
||||
{"pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon", FEAT_INIT, "", 0},
|
||||
{"predres", AArch64::AEK_PREDRES, "+predres", "-predres", FEAT_PREDRES, "+predres", 480},
|
||||
{"predres2", AArch64::AEK_SPECRES2, "+specres2", "-specres2", FEAT_INIT, "", 0},
|
||||
@ -263,7 +239,6 @@ inline constexpr ExtensionInfo Extensions[] = {
|
||||
{"rng", AArch64::AEK_RAND, "+rand", "-rand", FEAT_RNG, "+rand", 10},
|
||||
{"rpres", AArch64::AEK_NONE, {}, {}, FEAT_RPRES, "", 300},
|
||||
{"sb", AArch64::AEK_SB, "+sb", "-sb", FEAT_SB, "+sb", 470},
|
||||
{"sha1", AArch64::AEK_NONE, {}, {}, FEAT_SHA1, "+fp-armv8,+neon", 120},
|
||||
{"sha2", AArch64::AEK_SHA2, "+sha2", "-sha2", FEAT_SHA2, "+sha2,+fp-armv8,+neon", 130},
|
||||
{"sha3", AArch64::AEK_SHA3, "+sha3", "-sha3", FEAT_SHA3, "+sha3,+sha2,+fp-armv8,+neon", 140},
|
||||
{"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD, "+fp-armv8,+neon", 100},
|
||||
@ -275,14 +250,9 @@ inline constexpr ExtensionInfo Extensions[] = {
|
||||
{"sme2", AArch64::AEK_SME2, "+sme2", "-sme2", FEAT_SME2, "+sme2,+sme,+bf16", 580},
|
||||
{"sme2p1", AArch64::AEK_SME2p1, "+sme2p1", "-sme2p1", FEAT_INIT, "+sme2p1,+sme2,+sme,+bf16", 0},
|
||||
{"ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs", FEAT_SSBS, "", 490},
|
||||
{"ssbs2", AArch64::AEK_NONE, {}, {}, FEAT_SSBS2, "+ssbs", 500},
|
||||
{"sve-bf16", AArch64::AEK_NONE, {}, {}, FEAT_SVE_BF16, "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320},
|
||||
{"sve-ebf16", AArch64::AEK_NONE, {}, {}, FEAT_SVE_EBF16, "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330},
|
||||
{"sve-i8mm", AArch64::AEK_NONE, {}, {}, FEAT_SVE_I8MM, "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340},
|
||||
{"sve", AArch64::AEK_SVE, "+sve", "-sve", FEAT_SVE, "+sve,+fullfp16,+fp-armv8,+neon", 310},
|
||||
{"sve2-aes", AArch64::AEK_SVE2AES, "+sve2-aes", "-sve2-aes", FEAT_SVE_AES, "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380},
|
||||
{"sve2-bitperm", AArch64::AEK_SVE2BITPERM, "+sve2-bitperm", "-sve2-bitperm", FEAT_SVE_BITPERM, "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400},
|
||||
{"sve2-pmull128", AArch64::AEK_NONE, {}, {}, FEAT_SVE_PMULL128, "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390},
|
||||
{"sve2-sha3", AArch64::AEK_SVE2SHA3, "+sve2-sha3", "-sve2-sha3", FEAT_SVE_SHA3, "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410},
|
||||
{"sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4", "-sve2-sm4", FEAT_SVE_SM4, "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420},
|
||||
{"sve2", AArch64::AEK_SVE2, "+sve2", "-sve2", FEAT_SVE2, "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370},
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user