mirrors/llvm-project
0
0
Fork 0
mirror of https://github.com/llvm/llvm-project.git synced 2025-04-27 14:46:10 +00:00
Code Issues Projects Releases Wiki Activity

[TII] remove overrides of isUnpredicatedTerminator

Browse Source 
Summary:
They all match the base implementation in
TargetInstrInfo::isUnpredicatedTerminator.

Follow up to D62749.

Reviewers: echristo, MaskRay, hfinkel

Reviewed By: echristo

Subscribers: wuzish, nemanjai, hiraditya, kbarton, llvm-commits, srhines

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78976
This commit is contained in:
Nick Desaulniers 2020-04-28 08:34:01 -07:00
parent 43d1d52ad2
commit 1b9fdec1f6
5 changed files with 1 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/include/llvm/CodeGen/TargetInstrInfo.h
View File

@ -1316,7 +1316,7 @@ public:
/// Returns true if the instruction is a
/// terminator instruction that has not been predicated.
virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
bool isUnpredicatedTerminator(const MachineInstr &MI) const;
/// Returns true if MI is an unconditional tail call.
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {

12
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -160,18 +160,6 @@ reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
return false;
}
bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
if (!MI.isTerminator())
return false;
// Conditional branch is a special case.
if (MI.isBranch() && !MI.isBarrier())
return true;
if (!MI.isPredicable())
return true;
return !isPredicated(MI);
}
bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,

1
llvm/lib/Target/MSP430/MSP430InstrInfo.h
View File

@ -56,7 +56,6 @@ public:
// Branch folding goodness
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,

11
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -1452,17 +1452,6 @@ bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const {
return false;
}
bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
if (!MI.isTerminator())
return false;
// Conditional branch is a special case.
if (MI.isBranch() && !MI.isBarrier())
return true;
return !isPredicated(MI);
}
bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const {
unsigned OpC = MI.getOpcode();

2
llvm/lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -364,8 +364,6 @@ public:
// Predication support.
bool isPredicated(const MachineInstr &MI) const override;
bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
bool PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const override;