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Reapply "[AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bits=128." (#135177)
Reapplies #134068. The first patch was missing a check to prevent attempts to pair SVE fill/spill with other Neon load/store instructions, which could happen specifically if the Neon instruction was unscaled.
This commit is contained in:
Ricardo Jesus
GitHub
parent
53cd5cfc67
commit
1df4af6cbc
@ -2760,6 +2760,9 @@ bool AArch64InstrInfo::isPairableLdStInst(const MachineInstr &MI) {
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case AArch64::LDRXpre:
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case AArch64::LDURSWi:
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case AArch64::LDRSWpre:
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// SVE instructions.
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case AArch64::LDR_ZXI:
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case AArch64::STR_ZXI:
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return true;
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}
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}
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@ -2912,6 +2915,18 @@ bool AArch64InstrInfo::isCandidateToMergeOrPair(const MachineInstr &MI) const {
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return false;
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}
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// Pairing SVE fills/spills is only valid for little-endian targets that
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// implement VLS 128.
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switch (MI.getOpcode()) {
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default:
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break;
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case AArch64::LDR_ZXI:
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case AArch64::STR_ZXI:
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if (!Subtarget.isLittleEndian() ||
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Subtarget.getSVEVectorSizeInBits() != 128)
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return false;
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}
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// Check if this load/store has a hint to avoid pair formation.
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// MachineMemOperands hints are set by the AArch64StorePairSuppress pass.
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if (isLdStPairSuppressed(MI))
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@ -298,6 +298,7 @@ static unsigned getMatchingNonSExtOpcode(unsigned Opc,
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case AArch64::STRXui:
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case AArch64::STRXpre:
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case AArch64::STURXi:
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case AArch64::STR_ZXI:
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case AArch64::LDRDui:
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case AArch64::LDURDi:
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case AArch64::LDRDpre:
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@ -316,6 +317,7 @@ static unsigned getMatchingNonSExtOpcode(unsigned Opc,
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case AArch64::LDRSui:
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case AArch64::LDURSi:
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case AArch64::LDRSpre:
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case AArch64::LDR_ZXI:
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return Opc;
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case AArch64::LDRSWui:
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return AArch64::LDRWui;
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@ -361,6 +363,7 @@ static unsigned getMatchingPairOpcode(unsigned Opc) {
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return AArch64::STPDpre;
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case AArch64::STRQui:
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case AArch64::STURQi:
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case AArch64::STR_ZXI:
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return AArch64::STPQi;
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case AArch64::STRQpre:
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return AArch64::STPQpre;
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@ -386,6 +389,7 @@ static unsigned getMatchingPairOpcode(unsigned Opc) {
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return AArch64::LDPDpre;
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case AArch64::LDRQui:
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case AArch64::LDURQi:
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case AArch64::LDR_ZXI:
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return AArch64::LDPQi;
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case AArch64::LDRQpre:
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return AArch64::LDPQpre;
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@ -1225,6 +1229,16 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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(void)MIBSXTW;
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LLVM_DEBUG(dbgs() << " Extend operand:\n ");
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LLVM_DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
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} else if (Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI) {
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// We are combining SVE fill/spill to LDP/STP, so we need to use the Q
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// variant of the registers.
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MachineOperand &MOp0 = MIB->getOperand(0);
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MachineOperand &MOp1 = MIB->getOperand(1);
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assert(AArch64::ZPRRegClass.contains(MOp0.getReg()) &&
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AArch64::ZPRRegClass.contains(MOp1.getReg()) && "Invalid register.");
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MOp0.setReg(AArch64::Q0 + (MOp0.getReg() - AArch64::Z0));
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MOp1.setReg(AArch64::Q0 + (MOp1.getReg() - AArch64::Z0));
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LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs()));
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} else {
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LLVM_DEBUG(((MachineInstr *)MIB)->print(dbgs()));
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}
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@ -1499,6 +1513,12 @@ static bool areCandidatesToMergeOrPair(MachineInstr &FirstMI, MachineInstr &MI,
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if (OpcA == OpcB)
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return !AArch64InstrInfo::isPreLdSt(FirstMI);
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// Bail out if one of the opcodes is SVE fill/spill, as we currently don't
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// allow pairing them with other instructions.
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if (OpcA == AArch64::LDR_ZXI || OpcA == AArch64::STR_ZXI ||
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OpcB == AArch64::LDR_ZXI || OpcB == AArch64::STR_ZXI)
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return false;
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// Two pre ld/st of different opcodes cannot be merged either
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if (AArch64InstrInfo::isPreLdSt(FirstMI) && AArch64InstrInfo::isPreLdSt(MI))
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return false;
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@ -2659,7 +2679,8 @@ bool AArch64LoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
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// Get the needed alignments to check them if
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// ldp-aligned-only/stp-aligned-only features are opted.
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uint64_t MemAlignment = MemOp->getAlign().value();
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uint64_t TypeAlignment = Align(MemOp->getSize().getValue()).value();
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uint64_t TypeAlignment =
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Align(MemOp->getSize().getValue().getKnownMinValue()).value();
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if (MemAlignment < 2 * TypeAlignment) {
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NumFailedAlignmentCheck++;
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@ -2820,11 +2841,18 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
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}
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// 3) Find loads and stores that can be merged into a single load or store
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// pair instruction.
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// When compiling for SVE 128, also try to combine SVE fill/spill
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// instructions into LDP/STP.
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// e.g.,
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// ldr x0, [x2]
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// ldr x1, [x2, #8]
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// ; becomes
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// ldp x0, x1, [x2]
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// e.g.,
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// ldr z0, [x2]
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// ldr z1, [x2, #1, mul vl]
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// ; becomes
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// ldp q0, q1, [x2]
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if (MBB.getParent()->getRegInfo().tracksLiveness()) {
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DefinedInBB.clear();
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283
llvm/test/CodeGen/AArch64/aarch64-sve-fill-spill-pair.ll
Normal file
283
llvm/test/CodeGen/AArch64/aarch64-sve-fill-spill-pair.ll
Normal file
@ -0,0 +1,283 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=aarch64_be-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s --check-prefixes=CHECK-BE
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve,ldp-aligned-only -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s --check-prefixes=CHECK-LDPALIGNEDONLY
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve,stp-aligned-only -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s --check-prefixes=CHECK-STPALIGNEDONLY
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK-OFF
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=256 -aarch64-sve-vector-bits-max=256 < %s | FileCheck %s --check-prefixes=CHECK-OFF
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define void @nxv16i8(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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;
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; CHECK-BE-LABEL: nxv16i8:
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; CHECK-BE: // %bb.0:
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; CHECK-BE-NEXT: ptrue p0.b
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; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0]
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; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, #1, mul vl]
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; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1]
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; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, #1, mul vl]
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; CHECK-BE-NEXT: ret
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;
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; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8:
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; CHECK-LDPALIGNEDONLY: // %bb.0:
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0]
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #1, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: stp q0, q1, [x1]
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; CHECK-LDPALIGNEDONLY-NEXT: ret
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;
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; CHECK-STPALIGNEDONLY-LABEL: nxv16i8:
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; CHECK-STPALIGNEDONLY: // %bb.0:
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; CHECK-STPALIGNEDONLY-NEXT: ldp q0, q1, [x0]
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; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1]
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; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #1, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: ret
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;
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; CHECK-OFF-LABEL: nxv16i8:
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; CHECK-OFF: // %bb.0:
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; CHECK-OFF-NEXT: ldr z0, [x0]
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; CHECK-OFF-NEXT: ldr z1, [x0, #1, mul vl]
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; CHECK-OFF-NEXT: str z0, [x1]
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; CHECK-OFF-NEXT: str z1, [x1, #1, mul vl]
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; CHECK-OFF-NEXT: ret
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%vscale = tail call i64 @llvm.vscale()
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%vl = shl nuw nsw i64 %vscale, 4
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%ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %vl
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%stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %vl
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%ld1 = load <vscale x 16 x i8>, ptr %ldptr, align 1
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%ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1
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store <vscale x 16 x i8> %ld1, ptr %stptr, align 1
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store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1
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ret void
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}
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define void @nxv16i8_max_range(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv16i8_max_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0, #-1024]
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; CHECK-NEXT: stp q0, q1, [x1, #1008]
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; CHECK-NEXT: ret
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;
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; CHECK-BE-LABEL: nxv16i8_max_range:
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; CHECK-BE: // %bb.0:
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; CHECK-BE-NEXT: rdvl x8, #1
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; CHECK-BE-NEXT: mov x9, #-1008 // =0xfffffffffffffc10
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; CHECK-BE-NEXT: mov x10, #-1024 // =0xfffffffffffffc00
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; CHECK-BE-NEXT: lsr x8, x8, #4
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; CHECK-BE-NEXT: mov w11, #1008 // =0x3f0
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; CHECK-BE-NEXT: mov w12, #1024 // =0x400
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; CHECK-BE-NEXT: ptrue p0.b
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; CHECK-BE-NEXT: mul x9, x8, x9
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; CHECK-BE-NEXT: mul x10, x8, x10
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; CHECK-BE-NEXT: mul x11, x8, x11
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; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, x9]
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; CHECK-BE-NEXT: mul x8, x8, x12
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; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0, x10]
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; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1, x11]
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; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, x8]
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; CHECK-BE-NEXT: ret
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;
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; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8_max_range:
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; CHECK-LDPALIGNEDONLY: // %bb.0:
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0, #-64, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #-63, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: stp q0, q1, [x1, #1008]
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; CHECK-LDPALIGNEDONLY-NEXT: ret
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;
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; CHECK-STPALIGNEDONLY-LABEL: nxv16i8_max_range:
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; CHECK-STPALIGNEDONLY: // %bb.0:
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; CHECK-STPALIGNEDONLY-NEXT: ldp q0, q1, [x0, #-1024]
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; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1, #63, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #64, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: ret
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;
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; CHECK-OFF-LABEL: nxv16i8_max_range:
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; CHECK-OFF: // %bb.0:
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; CHECK-OFF-NEXT: ldr z0, [x0, #-64, mul vl]
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; CHECK-OFF-NEXT: ldr z1, [x0, #-63, mul vl]
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; CHECK-OFF-NEXT: str z0, [x1, #63, mul vl]
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; CHECK-OFF-NEXT: str z1, [x1, #64, mul vl]
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; CHECK-OFF-NEXT: ret
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%vscale = tail call i64 @llvm.vscale()
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%ldoff1 = mul i64 %vscale, -1024
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%ldoff2 = mul i64 %vscale, -1008
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%stoff1 = mul i64 %vscale, 1008
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%stoff2 = mul i64 %vscale, 1024
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%ldptr1 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff1
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%ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff2
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%stptr1 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff1
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%stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff2
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%ld1 = load <vscale x 16 x i8>, ptr %ldptr1, align 1
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%ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1
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store <vscale x 16 x i8> %ld1, ptr %stptr1, align 1
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store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1
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ret void
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}
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define void @nxv16i8_outside_range(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv16i8_outside_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0, #-65, mul vl]
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; CHECK-NEXT: ldr z1, [x0, #-64, mul vl]
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; CHECK-NEXT: str z0, [x1, #64, mul vl]
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; CHECK-NEXT: str z1, [x1, #65, mul vl]
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; CHECK-NEXT: ret
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;
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; CHECK-BE-LABEL: nxv16i8_outside_range:
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; CHECK-BE: // %bb.0:
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; CHECK-BE-NEXT: rdvl x8, #1
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; CHECK-BE-NEXT: mov x9, #-1040 // =0xfffffffffffffbf0
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; CHECK-BE-NEXT: mov x10, #-1024 // =0xfffffffffffffc00
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; CHECK-BE-NEXT: lsr x8, x8, #4
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; CHECK-BE-NEXT: mov w11, #1024 // =0x400
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; CHECK-BE-NEXT: mov w12, #1040 // =0x410
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; CHECK-BE-NEXT: ptrue p0.b
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; CHECK-BE-NEXT: mul x9, x8, x9
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; CHECK-BE-NEXT: mul x10, x8, x10
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; CHECK-BE-NEXT: mul x11, x8, x11
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; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0, x9]
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; CHECK-BE-NEXT: mul x8, x8, x12
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; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, x10]
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; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1, x11]
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; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, x8]
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; CHECK-BE-NEXT: ret
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;
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; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8_outside_range:
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; CHECK-LDPALIGNEDONLY: // %bb.0:
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0, #-65, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #-64, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: str z0, [x1, #64, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: str z1, [x1, #65, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: ret
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;
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; CHECK-STPALIGNEDONLY-LABEL: nxv16i8_outside_range:
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; CHECK-STPALIGNEDONLY: // %bb.0:
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; CHECK-STPALIGNEDONLY-NEXT: ldr z0, [x0, #-65, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: ldr z1, [x0, #-64, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1, #64, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #65, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: ret
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;
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; CHECK-OFF-LABEL: nxv16i8_outside_range:
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; CHECK-OFF: // %bb.0:
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; CHECK-OFF-NEXT: ldr z0, [x0, #-65, mul vl]
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; CHECK-OFF-NEXT: ldr z1, [x0, #-64, mul vl]
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; CHECK-OFF-NEXT: str z0, [x1, #64, mul vl]
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; CHECK-OFF-NEXT: str z1, [x1, #65, mul vl]
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; CHECK-OFF-NEXT: ret
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%vscale = tail call i64 @llvm.vscale()
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%ldoff1 = mul i64 %vscale, -1040
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%ldoff2 = mul i64 %vscale, -1024
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%stoff1 = mul i64 %vscale, 1024
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%stoff2 = mul i64 %vscale, 1040
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%ldptr1 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff1
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%ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff2
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%stptr1 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff1
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%stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff2
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%ld1 = load <vscale x 16 x i8>, ptr %ldptr1, align 1
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%ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1
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store <vscale x 16 x i8> %ld1, ptr %stptr1, align 1
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store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1
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ret void
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}
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define void @nxv16i8_2vl_stride(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv16i8_2vl_stride:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ldr z1, [x0, #2, mul vl]
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; CHECK-NEXT: str z0, [x1]
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; CHECK-NEXT: str z1, [x1, #2, mul vl]
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; CHECK-NEXT: ret
|
||||
;
|
||||
; CHECK-BE-LABEL: nxv16i8_2vl_stride:
|
||||
; CHECK-BE: // %bb.0:
|
||||
; CHECK-BE-NEXT: ptrue p0.b
|
||||
; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0]
|
||||
; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, #2, mul vl]
|
||||
; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1]
|
||||
; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, #2, mul vl]
|
||||
; CHECK-BE-NEXT: ret
|
||||
;
|
||||
; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8_2vl_stride:
|
||||
; CHECK-LDPALIGNEDONLY: // %bb.0:
|
||||
; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0]
|
||||
; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #2, mul vl]
|
||||
; CHECK-LDPALIGNEDONLY-NEXT: str z0, [x1]
|
||||
; CHECK-LDPALIGNEDONLY-NEXT: str z1, [x1, #2, mul vl]
|
||||
; CHECK-LDPALIGNEDONLY-NEXT: ret
|
||||
;
|
||||
; CHECK-STPALIGNEDONLY-LABEL: nxv16i8_2vl_stride:
|
||||
; CHECK-STPALIGNEDONLY: // %bb.0:
|
||||
; CHECK-STPALIGNEDONLY-NEXT: ldr z0, [x0]
|
||||
; CHECK-STPALIGNEDONLY-NEXT: ldr z1, [x0, #2, mul vl]
|
||||
; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1]
|
||||
; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #2, mul vl]
|
||||
; CHECK-STPALIGNEDONLY-NEXT: ret
|
||||
;
|
||||
; CHECK-OFF-LABEL: nxv16i8_2vl_stride:
|
||||
; CHECK-OFF: // %bb.0:
|
||||
; CHECK-OFF-NEXT: ldr z0, [x0]
|
||||
; CHECK-OFF-NEXT: ldr z1, [x0, #2, mul vl]
|
||||
; CHECK-OFF-NEXT: str z0, [x1]
|
||||
; CHECK-OFF-NEXT: str z1, [x1, #2, mul vl]
|
||||
; CHECK-OFF-NEXT: ret
|
||||
%vscale = tail call i64 @llvm.vscale()
|
||||
%vl = shl nuw nsw i64 %vscale, 5
|
||||
%ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %vl
|
||||
%stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %vl
|
||||
%ld1 = load <vscale x 16 x i8>, ptr %ldptr, align 1
|
||||
%ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1
|
||||
store <vscale x 16 x i8> %ld1, ptr %stptr, align 1
|
||||
store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @nxv2f64_32b_aligned(ptr %ldptr, ptr %stptr) {
|
||||
; CHECK-LABEL: nxv2f64_32b_aligned:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-NEXT: ret
|
||||
;
|
||||
; CHECK-BE-LABEL: nxv2f64_32b_aligned:
|
||||
; CHECK-BE: // %bb.0:
|
||||
; CHECK-BE-NEXT: ptrue p0.d
|
||||
; CHECK-BE-NEXT: ld1d { z0.d }, p0/z, [x0]
|
||||
; CHECK-BE-NEXT: ld1d { z1.d }, p0/z, [x0, #1, mul vl]
|
||||
; CHECK-BE-NEXT: st1d { z0.d }, p0, [x1]
|
||||
; CHECK-BE-NEXT: st1d { z1.d }, p0, [x1, #1, mul vl]
|
||||
; CHECK-BE-NEXT: ret
|
||||
;
|
||||
; CHECK-LDPALIGNEDONLY-LABEL: nxv2f64_32b_aligned:
|
||||
; CHECK-LDPALIGNEDONLY: // %bb.0:
|
||||
; CHECK-LDPALIGNEDONLY-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-LDPALIGNEDONLY-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-LDPALIGNEDONLY-NEXT: ret
|
||||
;
|
||||
; CHECK-STPALIGNEDONLY-LABEL: nxv2f64_32b_aligned:
|
||||
; CHECK-STPALIGNEDONLY: // %bb.0:
|
||||
; CHECK-STPALIGNEDONLY-NEXT: ldp q0, q1, [x0]
|
||||
; CHECK-STPALIGNEDONLY-NEXT: stp q0, q1, [x1]
|
||||
; CHECK-STPALIGNEDONLY-NEXT: ret
|
||||
;
|
||||
; CHECK-OFF-LABEL: nxv2f64_32b_aligned:
|
||||
; CHECK-OFF: // %bb.0:
|
||||
; CHECK-OFF-NEXT: ldr z0, [x0]
|
||||
; CHECK-OFF-NEXT: ldr z1, [x0, #1, mul vl]
|
||||
; CHECK-OFF-NEXT: str z0, [x1]
|
||||
; CHECK-OFF-NEXT: str z1, [x1, #1, mul vl]
|
||||
; CHECK-OFF-NEXT: ret
|
||||
%vscale = tail call i64 @llvm.vscale()
|
||||
%vl = shl nuw nsw i64 %vscale, 4
|
||||
%ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %vl
|
||||
%stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %vl
|
||||
%ld1 = load <vscale x 2 x double>, ptr %ldptr, align 32
|
||||
%ld2 = load <vscale x 2 x double>, ptr %ldptr2, align 32
|
||||
store <vscale x 2 x double> %ld1, ptr %stptr, align 32
|
||||
store <vscale x 2 x double> %ld2, ptr %stptr2, align 32
|
||||
ret void
|
||||
}
|
||||
74
llvm/test/CodeGen/AArch64/sve-vls-ldst-opt.mir
Normal file
74
llvm/test/CodeGen/AArch64/sve-vls-ldst-opt.mir
Normal file
@ -0,0 +1,74 @@
|
||||
# RUN: llc -mtriple=aarch64-unknown-linux -mattr=+sve -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 -run-pass=aarch64-ldst-opt -verify-machineinstrs %s -o - | FileCheck %s
|
||||
---
|
||||
name: pair-sve-fill-spill
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1
|
||||
renamable $z0 = LDR_ZXI renamable $x0, 0 :: (load (<vscale x 1 x s128>))
|
||||
renamable $z1 = LDR_ZXI killed renamable $x0, 1 :: (load (<vscale x 1 x s128>))
|
||||
STR_ZXI killed renamable $z0, renamable $x1, 0 :: (store (<vscale x 1 x s128>))
|
||||
STR_ZXI killed renamable $z1, killed renamable $x1, 1 :: (store (<vscale x 1 x s128>))
|
||||
RET_ReallyLR
|
||||
...
|
||||
# CHECK-LABEL: name: pair-sve-fill-spill
|
||||
# CHECK: $q0, $q1 = LDPQi renamable $x0, 0 :: (load (<vscale x 1 x s128>))
|
||||
# CHECK: STPQi killed $q0, killed $q1, renamable $x1, 0 :: (store (<vscale x 1 x s128>))
|
||||
---
|
||||
name: do-not-pair-sve-with-neon-scaled
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1
|
||||
; SVE LDR + Neon LDR
|
||||
renamable $z0 = LDR_ZXI renamable $x0, 0 :: (load (<vscale x 1 x s128>))
|
||||
renamable $q1 = LDRQui renamable $x0, 1 :: (load (s128))
|
||||
; Neon LDR + SVE LDR
|
||||
renamable $q2 = LDRQui renamable $x0, 3 :: (load (s128))
|
||||
renamable $z3 = LDR_ZXI renamable $x0, 4 :: (load (<vscale x 1 x s128>))
|
||||
; SVE STR + Neon STR
|
||||
STR_ZXI killed renamable $z0, renamable $x1, 0 :: (store (<vscale x 1 x s128>))
|
||||
STRQui killed renamable $q1, renamable $x1, 1 :: (store (s128))
|
||||
; Neon STR + SVE STR
|
||||
STRQui killed renamable $q2, renamable $x1, 3 :: (store (s128))
|
||||
STR_ZXI killed renamable $z3, renamable $x1, 4 :: (store (<vscale x 1 x s128>))
|
||||
RET_ReallyLR
|
||||
...
|
||||
# CHECK-LABEL: name: do-not-pair-sve-with-neon-scaled
|
||||
# CHECK: renamable $z0 = LDR_ZXI renamable $x0, 0 :: (load (<vscale x 1 x s128>))
|
||||
# CHECK: renamable $q1 = LDRQui renamable $x0, 1 :: (load (s128))
|
||||
# CHECK: renamable $q2 = LDRQui renamable $x0, 3 :: (load (s128))
|
||||
# CHECK: renamable $z3 = LDR_ZXI renamable $x0, 4 :: (load (<vscale x 1 x s128>))
|
||||
# CHECK: STR_ZXI killed renamable $z0, renamable $x1, 0 :: (store (<vscale x 1 x s128>))
|
||||
# CHECK: STRQui killed renamable $q1, renamable $x1, 1 :: (store (s128))
|
||||
# CHECK: STRQui killed renamable $q2, renamable $x1, 3 :: (store (s128))
|
||||
# CHECK: STR_ZXI killed renamable $z3, renamable $x1, 4 :: (store (<vscale x 1 x s128>))
|
||||
---
|
||||
name: do-not-pair-sve-with-neon-unscaled
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1
|
||||
; SVE LDR + Neon LDUR
|
||||
renamable $z0 = LDR_ZXI renamable $x0, 0 :: (load (<vscale x 1 x s128>))
|
||||
renamable $q1 = LDURQi renamable $x0, 16 :: (load (s128))
|
||||
; Neon LDUR + SVE LDR
|
||||
renamable $q2 = LDURQi renamable $x0, 48 :: (load (s128))
|
||||
renamable $z3 = LDR_ZXI renamable $x0, 4 :: (load (<vscale x 1 x s128>))
|
||||
; SVE STR + Neon STUR
|
||||
STR_ZXI killed renamable $z0, renamable $x1, 0 :: (store (<vscale x 1 x s128>))
|
||||
STURQi killed renamable $q1, renamable $x1, 16 :: (store (s128))
|
||||
; Neon STUR + SVE STR
|
||||
STURQi killed renamable $q2, renamable $x1, 48 :: (store (s128))
|
||||
STR_ZXI killed renamable $z3, renamable $x1, 4 :: (store (<vscale x 1 x s128>))
|
||||
RET_ReallyLR
|
||||
...
|
||||
# CHECK-LABEL: name: do-not-pair-sve-with-neon-unscaled
|
||||
# CHECK: renamable $z0 = LDR_ZXI renamable $x0, 0 :: (load (<vscale x 1 x s128>))
|
||||
# CHECK: renamable $q1 = LDURQi renamable $x0, 16 :: (load (s128))
|
||||
# CHECK: renamable $q2 = LDURQi renamable $x0, 48 :: (load (s128))
|
||||
# CHECK: renamable $z3 = LDR_ZXI renamable $x0, 4 :: (load (<vscale x 1 x s128>))
|
||||
# CHECK: STR_ZXI killed renamable $z0, renamable $x1, 0 :: (store (<vscale x 1 x s128>))
|
||||
# CHECK: STURQi killed renamable $q1, renamable $x1, 16 :: (store (s128))
|
||||
# CHECK: STURQi killed renamable $q2, renamable $x1, 48 :: (store (s128))
|
||||
# CHECK: STR_ZXI killed renamable $z3, renamable $x1, 4 :: (store (<vscale x 1 x s128>))
|
||||
Loading…
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Reference in New Issue
Block a user