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[AArch64][GlobalISel] Update and cleanup a number of gisel tests. NFC

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Mostly removing unnecessary -global-isel-abort=2 or adding fallback messages
This commit is contained in:
David Green 2024-11-23 18:58:55 +00:00
parent 5f9db0876a
commit 28064bfad1
34 changed files with 4172 additions and 1342 deletions
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2
llvm/test/CodeGen/AArch64/abs.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; ===== Legal Scalars =====

56
llvm/test/CodeGen/AArch64/arm64-clrsb.ll
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@ -1,78 +1,68 @@
; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -O0 -pass-remarks-missed=gisel* -global-isel-abort=2 | FileCheck %s --check-prefixes=GISEL,FALLBACK
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
; Function Attrs: nounwind readnone
declare i32 @llvm.ctlz.i32(i32, i1) #0
declare i64 @llvm.ctlz.i64(i64, i1) #1
; Function Attrs: nounwind ssp
; FALLBACK-NOT: remark{{.*}}clrsb32
define i32 @clrsb32(i32 %x) #2 {
; CHECK-LABEL: clrsb32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cls w0, w0
; CHECK-NEXT: ret
entry:
%shr = ashr i32 %x, 31
%xor = xor i32 %shr, %x
%mul = shl i32 %xor, 1
%add = or i32 %mul, 1
%0 = tail call i32 @llvm.ctlz.i32(i32 %add, i1 false)
ret i32 %0
; CHECK-LABEL: clrsb32
; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]]
; GISEL-LABEL: clrsb32
; GISEL: cls [[TEMP:w[0-9]+]], [[TEMP]]
}
; Function Attrs: nounwind ssp
; FALLBACK-NOT: remark{{.*}}clrsb64
define i64 @clrsb64(i64 %x) #3 {
; CHECK-LABEL: clrsb64:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cls x0, x0
; CHECK-NEXT: ret
entry:
%shr = ashr i64 %x, 63
%xor = xor i64 %shr, %x
%mul = shl nsw i64 %xor, 1
%add = or i64 %mul, 1
%0 = tail call i64 @llvm.ctlz.i64(i64 %add, i1 false)
ret i64 %0
; CHECK-LABEL: clrsb64
; CHECK: cls [[TEMP:x[0-9]+]], [[TEMP]]
; GISEL-LABEL: clrsb64
; GISEL: cls [[TEMP:x[0-9]+]], [[TEMP]]
}
; Function Attrs: nounwind ssp
; FALLBACK-NOT: remark{{.*}}clrsb32_zeroundef
define i32 @clrsb32_zeroundef(i32 %x) #2 {
; CHECK-LABEL: clrsb32_zeroundef:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cls w0, w0
; CHECK-NEXT: ret
entry:
%shr = ashr i32 %x, 31
%xor = xor i32 %shr, %x
%mul = shl i32 %xor, 1
%add = or i32 %mul, 1
%0 = tail call i32 @llvm.ctlz.i32(i32 %add, i1 true)
ret i32 %0
; CHECK-LABEL: clrsb32_zeroundef
; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]]
; GISEL-LABEL: clrsb32_zeroundef
; GISEL: cls [[TEMP:w[0-9]+]], [[TEMP]]
}
; Function Attrs: nounwind ssp
; FALLBACK-NOT: remark{{.*}}clrsb64
define i64 @clrsb64_zeroundef(i64 %x) #3 {
; CHECK-LABEL: clrsb64_zeroundef:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cls x0, x0
; CHECK-NEXT: ret
entry:
%shr = ashr i64 %x, 63
%xor = xor i64 %shr, %x
%mul = shl nsw i64 %xor, 1
%add = or i64 %mul, 1
%0 = tail call i64 @llvm.ctlz.i64(i64 %add, i1 true)
ret i64 %0
; CHECK-LABEL: clrsb64_zeroundef
; CHECK: cls [[TEMP:x[0-9]+]], [[TEMP]]
; GISEL-LABEL: clrsb64_zeroundef
; GISEL: cls [[TEMP:x[0-9]+]], [[TEMP]]
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-GI: {{.*}}
; CHECK-SD: {{.*}}

617
llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll
View File

@ -1,12 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define void @testLeftGood8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftGood8x8:
; CHECK: // %bb.0:
; CHECK-NEXT: sli.8b v0, v1, #3
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftGood8x8:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sli.8b v0, v1, #3
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftGood8x8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi.8b v2, #7
; CHECK-GI-NEXT: shl.8b v1, v1, #3
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <8 x i8> %src1, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%vshl_n = shl <8 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
%result = or <8 x i8> %and.i, %vshl_n
@ -15,14 +25,23 @@ define void @testLeftGood8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind
}
define void @testLeftBad8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftBad8x8:
; CHECK: // %bb.0:
; CHECK-NEXT: movi.8b v2, #165
; CHECK-NEXT: add.8b v1, v1, v1
; CHECK-NEXT: and.8b v0, v0, v2
; CHECK-NEXT: orr.8b v0, v0, v1
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftBad8x8:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: movi.8b v2, #165
; CHECK-SD-NEXT: add.8b v1, v1, v1
; CHECK-SD-NEXT: and.8b v0, v0, v2
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftBad8x8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi.8b v2, #165
; CHECK-GI-NEXT: shl.8b v1, v1, #1
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <8 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165>
%vshl_n = shl <8 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%result = or <8 x i8> %and.i, %vshl_n
@ -31,11 +50,20 @@ define void @testLeftBad8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind
}
define void @testRightGood8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightGood8x8:
; CHECK: // %bb.0:
; CHECK-NEXT: sri.8b v0, v1, #3
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightGood8x8:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sri.8b v0, v1, #3
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightGood8x8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi.8b v2, #224
; CHECK-GI-NEXT: ushr.8b v1, v1, #3
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <8 x i8> %src1, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
%vshl_n = lshr <8 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
%result = or <8 x i8> %and.i, %vshl_n
@ -60,11 +88,20 @@ define void @testRightBad8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind
}
define void @testLeftGood16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftGood16x8:
; CHECK: // %bb.0:
; CHECK-NEXT: sli.16b v0, v1, #3
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftGood16x8:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sli.16b v0, v1, #3
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftGood16x8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi.16b v2, #7
; CHECK-GI-NEXT: shl.16b v1, v1, #3
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <16 x i8> %src1, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%vshl_n = shl <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
%result = or <16 x i8> %and.i, %vshl_n
@ -73,14 +110,23 @@ define void @testLeftGood16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounw
}
define void @testLeftBad16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftBad16x8:
; CHECK: // %bb.0:
; CHECK-NEXT: movi.16b v2, #165
; CHECK-NEXT: add.16b v1, v1, v1
; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: orr.16b v0, v0, v1
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftBad16x8:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: movi.16b v2, #165
; CHECK-SD-NEXT: add.16b v1, v1, v1
; CHECK-SD-NEXT: and.16b v0, v0, v2
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftBad16x8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi.16b v2, #165
; CHECK-GI-NEXT: shl.16b v1, v1, #1
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <16 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165>
%vshl_n = shl <16 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%result = or <16 x i8> %and.i, %vshl_n
@ -89,11 +135,20 @@ define void @testLeftBad16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounwi
}
define void @testRightGood16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightGood16x8:
; CHECK: // %bb.0:
; CHECK-NEXT: sri.16b v0, v1, #3
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightGood16x8:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sri.16b v0, v1, #3
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightGood16x8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi.16b v2, #224
; CHECK-GI-NEXT: ushr.16b v1, v1, #3
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <16 x i8> %src1, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
%vshl_n = lshr <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
%result = or <16 x i8> %and.i, %vshl_n
@ -118,11 +173,20 @@ define void @testRightBad16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounw
}
define void @testLeftGood4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftGood4x16:
; CHECK: // %bb.0:
; CHECK-NEXT: sli.4h v0, v1, #14
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftGood4x16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sli.4h v0, v1, #14
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftGood4x16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mvni.4h v2, #192, lsl #8
; CHECK-GI-NEXT: shl.4h v1, v1, #14
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <4 x i16> %src1, <i16 16383, i16 16383, i16 16383, i16 16383>
%vshl_n = shl <4 x i16> %src2, <i16 14, i16 14, i16 14, i16 14>
%result = or <4 x i16> %and.i, %vshl_n
@ -131,15 +195,25 @@ define void @testLeftGood4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounw
}
define void @testLeftBad4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftBad4x16:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #16500
; CHECK-NEXT: shl.4h v1, v1, #14
; CHECK-NEXT: dup.4h v2, w8
; CHECK-NEXT: and.8b v0, v0, v2
; CHECK-NEXT: orr.8b v0, v0, v1
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftBad4x16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #16500 // =0x4074
; CHECK-SD-NEXT: shl.4h v1, v1, #14
; CHECK-SD-NEXT: dup.4h v2, w8
; CHECK-SD-NEXT: and.8b v0, v0, v2
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftBad4x16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI9_0
; CHECK-GI-NEXT: shl.4h v1, v1, #14
; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI9_0]
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <4 x i16> %src1, <i16 16500, i16 16500, i16 16500, i16 16500>
%vshl_n = shl <4 x i16> %src2, <i16 14, i16 14, i16 14, i16 14>
%result = or <4 x i16> %and.i, %vshl_n
@ -148,11 +222,20 @@ define void @testLeftBad4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounwi
}
define void @testRightGood4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightGood4x16:
; CHECK: // %bb.0:
; CHECK-NEXT: sri.4h v0, v1, #14
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightGood4x16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sri.4h v0, v1, #14
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightGood4x16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mvni.4h v2, #3
; CHECK-GI-NEXT: ushr.4h v1, v1, #14
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <4 x i16> %src1, <i16 65532, i16 65532, i16 65532, i16 65532>
%vshl_n = lshr <4 x i16> %src2, <i16 14, i16 14, i16 14, i16 14>
%result = or <4 x i16> %and.i, %vshl_n
@ -161,14 +244,24 @@ define void @testRightGood4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) noun
}
define void @testRightBad4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightBad4x16:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #16500
; CHECK-NEXT: dup.4h v2, w8
; CHECK-NEXT: and.8b v0, v0, v2
; CHECK-NEXT: usra.4h v0, v1, #14
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightBad4x16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #16500 // =0x4074
; CHECK-SD-NEXT: dup.4h v2, w8
; CHECK-SD-NEXT: and.8b v0, v0, v2
; CHECK-SD-NEXT: usra.4h v0, v1, #14
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightBad4x16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI11_0
; CHECK-GI-NEXT: ushr.4h v1, v1, #14
; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI11_0]
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <4 x i16> %src1, <i16 16500, i16 16500, i16 16500, i16 16500>
%vshl_n = lshr <4 x i16> %src2, <i16 14, i16 14, i16 14, i16 14>
%result = or <4 x i16> %and.i, %vshl_n
@ -177,11 +270,20 @@ define void @testRightBad4x16(<4 x i16> %src1, <4 x i16> %src2, ptr %dest) nounw
}
define void @testLeftGood8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftGood8x16:
; CHECK: // %bb.0:
; CHECK-NEXT: sli.8h v0, v1, #14
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftGood8x16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sli.8h v0, v1, #14
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftGood8x16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mvni.8h v2, #192, lsl #8
; CHECK-GI-NEXT: shl.8h v1, v1, #14
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <8 x i16> %src1, <i16 16383, i16 16383, i16 16383, i16 16383, i16 16383, i16 16383, i16 16383, i16 16383>
%vshl_n = shl <8 x i16> %src2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
%result = or <8 x i16> %and.i, %vshl_n
@ -190,15 +292,25 @@ define void @testLeftGood8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounw
}
define void @testLeftBad8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftBad8x16:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #16500
; CHECK-NEXT: shl.8h v1, v1, #14
; CHECK-NEXT: dup.8h v2, w8
; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: orr.16b v0, v0, v1
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftBad8x16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #16500 // =0x4074
; CHECK-SD-NEXT: shl.8h v1, v1, #14
; CHECK-SD-NEXT: dup.8h v2, w8
; CHECK-SD-NEXT: and.16b v0, v0, v2
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftBad8x16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI13_0
; CHECK-GI-NEXT: shl.8h v1, v1, #14
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <8 x i16> %src1, <i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500>
%vshl_n = shl <8 x i16> %src2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
%result = or <8 x i16> %and.i, %vshl_n
@ -207,11 +319,20 @@ define void @testLeftBad8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounwi
}
define void @testRightGood8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightGood8x16:
; CHECK: // %bb.0:
; CHECK-NEXT: sri.8h v0, v1, #14
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightGood8x16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sri.8h v0, v1, #14
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightGood8x16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mvni.8h v2, #3
; CHECK-GI-NEXT: ushr.8h v1, v1, #14
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <8 x i16> %src1, <i16 65532, i16 65532, i16 65532, i16 65532, i16 65532, i16 65532, i16 65532, i16 65532>
%vshl_n = lshr <8 x i16> %src2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
%result = or <8 x i16> %and.i, %vshl_n
@ -220,14 +341,24 @@ define void @testRightGood8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) noun
}
define void @testRightBad8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightBad8x16:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #16500
; CHECK-NEXT: dup.8h v2, w8
; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: usra.8h v0, v1, #14
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightBad8x16:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #16500 // =0x4074
; CHECK-SD-NEXT: dup.8h v2, w8
; CHECK-SD-NEXT: and.16b v0, v0, v2
; CHECK-SD-NEXT: usra.8h v0, v1, #14
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightBad8x16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI15_0
; CHECK-GI-NEXT: ushr.8h v1, v1, #14
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI15_0]
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <8 x i16> %src1, <i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500, i16 16500>
%vshl_n = lshr <8 x i16> %src2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14>
%result = or <8 x i16> %and.i, %vshl_n
@ -236,11 +367,20 @@ define void @testRightBad8x16(<8 x i16> %src1, <8 x i16> %src2, ptr %dest) nounw
}
define void @testLeftGood2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftGood2x32:
; CHECK: // %bb.0:
; CHECK-NEXT: sli.2s v0, v1, #22
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftGood2x32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sli.2s v0, v1, #22
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftGood2x32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi.2s v2, #63, msl #16
; CHECK-GI-NEXT: shl.2s v1, v1, #22
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <2 x i32> %src1, <i32 4194303, i32 4194303>
%vshl_n = shl <2 x i32> %src2, <i32 22, i32 22>
%result = or <2 x i32> %and.i, %vshl_n
@ -249,15 +389,25 @@ define void @testLeftGood2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounw
}
define void @testLeftBad2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftBad2x32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #4194300
; CHECK-NEXT: shl.2s v1, v1, #22
; CHECK-NEXT: dup.2s v2, w8
; CHECK-NEXT: and.8b v0, v0, v2
; CHECK-NEXT: orr.8b v0, v0, v1
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftBad2x32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #4194300 // =0x3ffffc
; CHECK-SD-NEXT: shl.2s v1, v1, #22
; CHECK-SD-NEXT: dup.2s v2, w8
; CHECK-SD-NEXT: and.8b v0, v0, v2
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftBad2x32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI17_0
; CHECK-GI-NEXT: shl.2s v1, v1, #22
; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI17_0]
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <2 x i32> %src1, <i32 4194300, i32 4194300>
%vshl_n = shl <2 x i32> %src2, <i32 22, i32 22>
%result = or <2 x i32> %and.i, %vshl_n
@ -266,11 +416,20 @@ define void @testLeftBad2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounwi
}
define void @testRightGood2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightGood2x32:
; CHECK: // %bb.0:
; CHECK-NEXT: sri.2s v0, v1, #22
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightGood2x32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sri.2s v0, v1, #22
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightGood2x32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mvni.2s v2, #3, msl #8
; CHECK-GI-NEXT: ushr.2s v1, v1, #22
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <2 x i32> %src1, <i32 4294966272, i32 4294966272>
%vshl_n = lshr <2 x i32> %src2, <i32 22, i32 22>
%result = or <2 x i32> %and.i, %vshl_n
@ -279,15 +438,25 @@ define void @testRightGood2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) noun
}
define void @testRightBad2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightBad2x32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #4194300
; CHECK-NEXT: ushr.2s v1, v1, #22
; CHECK-NEXT: dup.2s v2, w8
; CHECK-NEXT: and.8b v0, v0, v2
; CHECK-NEXT: orr.8b v0, v0, v1
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightBad2x32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #4194300 // =0x3ffffc
; CHECK-SD-NEXT: ushr.2s v1, v1, #22
; CHECK-SD-NEXT: dup.2s v2, w8
; CHECK-SD-NEXT: and.8b v0, v0, v2
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: str d0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightBad2x32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI19_0
; CHECK-GI-NEXT: ushr.2s v1, v1, #22
; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI19_0]
; CHECK-GI-NEXT: and.8b v0, v0, v2
; CHECK-GI-NEXT: orr.8b v0, v0, v1
; CHECK-GI-NEXT: str d0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <2 x i32> %src1, <i32 4194300, i32 4194300>
%vshl_n = lshr <2 x i32> %src2, <i32 22, i32 22>
%result = or <2 x i32> %and.i, %vshl_n
@ -296,11 +465,20 @@ define void @testRightBad2x32(<2 x i32> %src1, <2 x i32> %src2, ptr %dest) nounw
}
define void @testLeftGood4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftGood4x32:
; CHECK: // %bb.0:
; CHECK-NEXT: sli.4s v0, v1, #22
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftGood4x32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sli.4s v0, v1, #22
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftGood4x32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi.4s v2, #63, msl #16
; CHECK-GI-NEXT: shl.4s v1, v1, #22
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <4 x i32> %src1, <i32 4194303, i32 4194303, i32 4194303, i32 4194303>
%vshl_n = shl <4 x i32> %src2, <i32 22, i32 22, i32 22, i32 22>
%result = or <4 x i32> %and.i, %vshl_n
@ -309,15 +487,25 @@ define void @testLeftGood4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounw
}
define void @testLeftBad4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftBad4x32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #4194300
; CHECK-NEXT: shl.4s v1, v1, #22
; CHECK-NEXT: dup.4s v2, w8
; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: orr.16b v0, v0, v1
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftBad4x32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #4194300 // =0x3ffffc
; CHECK-SD-NEXT: shl.4s v1, v1, #22
; CHECK-SD-NEXT: dup.4s v2, w8
; CHECK-SD-NEXT: and.16b v0, v0, v2
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftBad4x32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI21_0
; CHECK-GI-NEXT: shl.4s v1, v1, #22
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI21_0]
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <4 x i32> %src1, <i32 4194300, i32 4194300, i32 4194300, i32 4194300>
%vshl_n = shl <4 x i32> %src2, <i32 22, i32 22, i32 22, i32 22>
%result = or <4 x i32> %and.i, %vshl_n
@ -326,11 +514,20 @@ define void @testLeftBad4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounwi
}
define void @testRightGood4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightGood4x32:
; CHECK: // %bb.0:
; CHECK-NEXT: sri.4s v0, v1, #22
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightGood4x32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sri.4s v0, v1, #22
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightGood4x32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mvni.4s v2, #3, msl #8
; CHECK-GI-NEXT: ushr.4s v1, v1, #22
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <4 x i32> %src1, <i32 4294966272, i32 4294966272, i32 4294966272, i32 4294966272>
%vshl_n = lshr <4 x i32> %src2, <i32 22, i32 22, i32 22, i32 22>
%result = or <4 x i32> %and.i, %vshl_n
@ -339,15 +536,25 @@ define void @testRightGood4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) noun
}
define void @testRightBad4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightBad4x32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #4194300
; CHECK-NEXT: ushr.4s v1, v1, #22
; CHECK-NEXT: dup.4s v2, w8
; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: orr.16b v0, v0, v1
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightBad4x32:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov w8, #4194300 // =0x3ffffc
; CHECK-SD-NEXT: ushr.4s v1, v1, #22
; CHECK-SD-NEXT: dup.4s v2, w8
; CHECK-SD-NEXT: and.16b v0, v0, v2
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightBad4x32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI23_0
; CHECK-GI-NEXT: ushr.4s v1, v1, #22
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI23_0]
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <4 x i32> %src1, <i32 4194300, i32 4194300, i32 4194300, i32 4194300>
%vshl_n = lshr <4 x i32> %src2, <i32 22, i32 22, i32 22, i32 22>
%result = or <4 x i32> %and.i, %vshl_n
@ -356,11 +563,20 @@ define void @testRightBad4x32(<4 x i32> %src1, <4 x i32> %src2, ptr %dest) nounw
}
define void @testLeftGood2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftGood2x64:
; CHECK: // %bb.0:
; CHECK-NEXT: sli.2d v0, v1, #48
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftGood2x64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sli.2d v0, v1, #48
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftGood2x64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi.2d v2, #0x00ffffffffffff
; CHECK-GI-NEXT: shl.2d v1, v1, #48
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <2 x i64> %src1, <i64 281474976710655, i64 281474976710655>
%vshl_n = shl <2 x i64> %src2, <i64 48, i64 48>
%result = or <2 x i64> %and.i, %vshl_n
@ -369,16 +585,26 @@ define void @testLeftGood2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounw
}
define void @testLeftBad2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftBad2x64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #10
; CHECK-NEXT: shl.2d v1, v1, #48
; CHECK-NEXT: movk x8, #1, lsl #48
; CHECK-NEXT: dup.2d v2, x8
; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: orr.16b v0, v0, v1
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftBad2x64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov x8, #10 // =0xa
; CHECK-SD-NEXT: shl.2d v1, v1, #48
; CHECK-SD-NEXT: movk x8, #1, lsl #48
; CHECK-SD-NEXT: dup.2d v2, x8
; CHECK-SD-NEXT: and.16b v0, v0, v2
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftBad2x64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI25_0
; CHECK-GI-NEXT: shl.2d v1, v1, #48
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI25_0]
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <2 x i64> %src1, <i64 281474976710666, i64 281474976710666>
%vshl_n = shl <2 x i64> %src2, <i64 48, i64 48>
%result = or <2 x i64> %and.i, %vshl_n
@ -387,11 +613,20 @@ define void @testLeftBad2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounwi
}
define void @testRightGood2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightGood2x64:
; CHECK: // %bb.0:
; CHECK-NEXT: sri.2d v0, v1, #48
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightGood2x64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sri.2d v0, v1, #48
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightGood2x64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi.2d v2, #0xffffffffffff0000
; CHECK-GI-NEXT: ushr.2d v1, v1, #48
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <2 x i64> %src1, <i64 18446744073709486080, i64 18446744073709486080>
%vshl_n = lshr <2 x i64> %src2, <i64 48, i64 48>
%result = or <2 x i64> %and.i, %vshl_n
@ -400,16 +635,26 @@ define void @testRightGood2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) noun
}
define void @testRightBad2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testRightBad2x64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #10
; CHECK-NEXT: ushr.2d v1, v1, #48
; CHECK-NEXT: movk x8, #1, lsl #48
; CHECK-NEXT: dup.2d v2, x8
; CHECK-NEXT: and.16b v0, v0, v2
; CHECK-NEXT: orr.16b v0, v0, v1
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testRightBad2x64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: mov x8, #10 // =0xa
; CHECK-SD-NEXT: ushr.2d v1, v1, #48
; CHECK-SD-NEXT: movk x8, #1, lsl #48
; CHECK-SD-NEXT: dup.2d v2, x8
; CHECK-SD-NEXT: and.16b v0, v0, v2
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: str q0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testRightBad2x64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI27_0
; CHECK-GI-NEXT: ushr.2d v1, v1, #48
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI27_0]
; CHECK-GI-NEXT: and.16b v0, v0, v2
; CHECK-GI-NEXT: orr.16b v0, v0, v1
; CHECK-GI-NEXT: str q0, [x0]
; CHECK-GI-NEXT: ret
%and.i = and <2 x i64> %src1, <i64 281474976710666, i64 281474976710666>
%vshl_n = lshr <2 x i64> %src2, <i64 48, i64 48>
%result = or <2 x i64> %and.i, %vshl_n
@ -418,11 +663,19 @@ define void @testRightBad2x64(<2 x i64> %src1, <2 x i64> %src2, ptr %dest) nounw
}
define void @testLeftShouldNotCreateSLI1x128(<1 x i128> %src1, <1 x i128> %src2, ptr %dest) nounwind {
; CHECK-LABEL: testLeftShouldNotCreateSLI1x128:
; CHECK: // %bb.0:
; CHECK-NEXT: bfi x1, x2, #6, #58
; CHECK-NEXT: stp x0, x1, [x4]
; CHECK-NEXT: ret
; CHECK-SD-LABEL: testLeftShouldNotCreateSLI1x128:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: bfi x1, x2, #6, #58
; CHECK-SD-NEXT: stp x0, x1, [x4]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: testLeftShouldNotCreateSLI1x128:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov.d v0[0], x0
; CHECK-GI-NEXT: bfi x1, x2, #6, #58
; CHECK-GI-NEXT: mov.d v0[1], x1
; CHECK-GI-NEXT: str q0, [x4]
; CHECK-GI-NEXT: ret
%and.i = and <1 x i128> %src1, <i128 1180591620717411303423>
%vshl_n = shl <1 x i128> %src2, <i128 70>
%result = or <1 x i128> %and.i, %vshl_n

230
llvm/test/CodeGen/AArch64/arm64-vclz.ll
View File

@ -1,154 +1,254 @@
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; FALLBACK-NOT: remark{{.*}}test_vclz_u8
define <8 x i8> @test_vclz_u8(<8 x i8> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclz_u8:
; CHECK: clz.8b v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclz_u8:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.8b v0, v0
; CHECK-NEXT: ret
%vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
ret <8 x i8> %vclz.i
}
; FALLBACK-NOT: remark{{.*}}test_vclz_s8
define <8 x i8> @test_vclz_s8(<8 x i8> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclz_s8:
; CHECK: clz.8b v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclz_s8:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.8b v0, v0
; CHECK-NEXT: ret
%vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
ret <8 x i8> %vclz.i
}
; FALLBACK-NOT: remark{{.*}}test_vclz_u16
define <4 x i16> @test_vclz_u16(<4 x i16> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclz_u16:
; CHECK: clz.4h v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclz_u16:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.4h v0, v0
; CHECK-NEXT: ret
%vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
ret <4 x i16> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclz_s16
define <4 x i16> @test_vclz_s16(<4 x i16> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclz_s16:
; CHECK: clz.4h v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclz_s16:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.4h v0, v0
; CHECK-NEXT: ret
%vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
ret <4 x i16> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclz_u32
define <2 x i32> @test_vclz_u32(<2 x i32> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclz_u32:
; CHECK: clz.2s v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclz_u32:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.2s v0, v0
; CHECK-NEXT: ret
%vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
ret <2 x i32> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclz_s32
define <2 x i32> @test_vclz_s32(<2 x i32> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclz_s32:
; CHECK: clz.2s v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclz_s32:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.2s v0, v0
; CHECK-NEXT: ret
%vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
ret <2 x i32> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclz_u64
define <1 x i64> @test_vclz_u64(<1 x i64> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclz_u64:
; CHECK-SD-LABEL: test_vclz_u64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: ushr d1, d0, #1
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: ushr d1, d0, #2
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: ushr d1, d0, #4
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: ushr d1, d0, #8
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: ushr d1, d0, #16
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: ushr d1, d0, #32
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: mvn.8b v0, v0
; CHECK-SD-NEXT: cnt.8b v0, v0
; CHECK-SD-NEXT: uaddlp.4h v0, v0
; CHECK-SD-NEXT: uaddlp.2s v0, v0
; CHECK-SD-NEXT: uaddlp.1d v0, v0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vclz_u64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: clz x8, x8
; CHECK-GI-NEXT: fmov d0, x8
; CHECK-GI-NEXT: ret
%vclz1.i = tail call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %a, i1 false) nounwind
ret <1 x i64> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclz_s64
define <1 x i64> @test_vclz_s64(<1 x i64> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclz_s64:
; CHECK-SD-LABEL: test_vclz_s64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: ushr d1, d0, #1
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: ushr d1, d0, #2
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: ushr d1, d0, #4
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: ushr d1, d0, #8
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: ushr d1, d0, #16
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: ushr d1, d0, #32
; CHECK-SD-NEXT: orr.8b v0, v0, v1
; CHECK-SD-NEXT: mvn.8b v0, v0
; CHECK-SD-NEXT: cnt.8b v0, v0
; CHECK-SD-NEXT: uaddlp.4h v0, v0
; CHECK-SD-NEXT: uaddlp.2s v0, v0
; CHECK-SD-NEXT: uaddlp.1d v0, v0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vclz_s64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: clz x8, x8
; CHECK-GI-NEXT: fmov d0, x8
; CHECK-GI-NEXT: ret
%vclz1.i = tail call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %a, i1 false) nounwind
ret <1 x i64> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclzq_u8
define <16 x i8> @test_vclzq_u8(<16 x i8> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclzq_u8:
; CHECK: clz.16b v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclzq_u8:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.16b v0, v0
; CHECK-NEXT: ret
%vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
ret <16 x i8> %vclz.i
}
; FALLBACK-NOT: remark{{.*}}test_vclzq_s8
define <16 x i8> @test_vclzq_s8(<16 x i8> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclzq_s8:
; CHECK: clz.16b v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclzq_s8:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.16b v0, v0
; CHECK-NEXT: ret
%vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
ret <16 x i8> %vclz.i
}
; FALLBACK-NOT: remark{{.*}}test_vclzq_u16
define <8 x i16> @test_vclzq_u16(<8 x i16> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclzq_u16:
; CHECK: clz.8h v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclzq_u16:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.8h v0, v0
; CHECK-NEXT: ret
%vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) nounwind
ret <8 x i16> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclzq_s16
define <8 x i16> @test_vclzq_s16(<8 x i16> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclzq_s16:
; CHECK: clz.8h v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclzq_s16:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.8h v0, v0
; CHECK-NEXT: ret
%vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) nounwind
ret <8 x i16> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclzq_u32
define <4 x i32> @test_vclzq_u32(<4 x i32> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclzq_u32:
; CHECK: clz.4s v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclzq_u32:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.4s v0, v0
; CHECK-NEXT: ret
%vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) nounwind
ret <4 x i32> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclzq_s32
define <4 x i32> @test_vclzq_s32(<4 x i32> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclzq_s32:
; CHECK: clz.4s v0, v0
; CHECK-NEXT: ret
; CHECK-LABEL: test_vclzq_s32:
; CHECK: // %bb.0:
; CHECK-NEXT: clz.4s v0, v0
; CHECK-NEXT: ret
%vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) nounwind
ret <4 x i32> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclzq_u64
define <2 x i64> @test_vclzq_u64(<2 x i64> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclzq_u64:
; CHECK-SD-LABEL: test_vclzq_u64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: ushr.2d v1, v0, #1
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: ushr.2d v1, v0, #2
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: ushr.2d v1, v0, #4
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: ushr.2d v1, v0, #8
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: ushr.2d v1, v0, #16
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: ushr.2d v1, v0, #32
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: mvn.16b v0, v0
; CHECK-SD-NEXT: cnt.16b v0, v0
; CHECK-SD-NEXT: uaddlp.8h v0, v0
; CHECK-SD-NEXT: uaddlp.4s v0, v0
; CHECK-SD-NEXT: uaddlp.2d v0, v0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vclzq_u64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov.d x9, v0[1]
; CHECK-GI-NEXT: clz x8, x8
; CHECK-GI-NEXT: mov.d v0[0], x8
; CHECK-GI-NEXT: clz x8, x9
; CHECK-GI-NEXT: mov.d v0[1], x8
; CHECK-GI-NEXT: ret
%vclz1.i = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) nounwind
ret <2 x i64> %vclz1.i
}
; FALLBACK-NOT: remark{{.*}}test_vclzq_s64
define <2 x i64> @test_vclzq_s64(<2 x i64> %a) nounwind readnone ssp {
; CHECK-LABEL: test_vclzq_s64:
; CHECK-SD-LABEL: test_vclzq_s64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: ushr.2d v1, v0, #1
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: ushr.2d v1, v0, #2
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: ushr.2d v1, v0, #4
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: ushr.2d v1, v0, #8
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: ushr.2d v1, v0, #16
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: ushr.2d v1, v0, #32
; CHECK-SD-NEXT: orr.16b v0, v0, v1
; CHECK-SD-NEXT: mvn.16b v0, v0
; CHECK-SD-NEXT: cnt.16b v0, v0
; CHECK-SD-NEXT: uaddlp.8h v0, v0
; CHECK-SD-NEXT: uaddlp.4s v0, v0
; CHECK-SD-NEXT: uaddlp.2d v0, v0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vclzq_s64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: mov.d x9, v0[1]
; CHECK-GI-NEXT: clz x8, x8
; CHECK-GI-NEXT: mov.d v0[0], x8
; CHECK-GI-NEXT: clz x8, x9
; CHECK-GI-NEXT: mov.d v0[1], x8
; CHECK-GI-NEXT: ret
%vclz1.i = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) nounwind
ret <2 x i64> %vclz1.i
}
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
declare <1 x i64> @llvm.ctlz.v1i64(<1 x i64>, i1) nounwind readnone
declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone

2
llvm/test/CodeGen/AArch64/concat-vector.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64 -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <4 x i8> @concat1(<2 x i8> %A, <2 x i8> %B) {
; CHECK-SD-LABEL: concat1:

2
llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <2 x i32> @and_extract_zext_idx0(<4 x i16> %vec) nounwind {
; CHECK-SD-LABEL: and_extract_zext_idx0:

7
llvm/test/CodeGen/AArch64/extract-vector-elt-sve.ll
View File

@ -2,6 +2,13 @@
; RUN: llc -mtriple=aarch64 -mattr=+sve -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for insert_vscale_8_i16_zero
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_vscale_8_i16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_vscale_16_i8_zero
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_vscale_16_i8
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_vscale_16_i8
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_vscale_16_i8_zero
define <vscale x 2 x i64> @insert_vscale_2_i64_zero(<vscale x 2 x i64> %vec, i64 %elt) {
; CHECK-SD-LABEL: insert_vscale_2_i64_zero:
; CHECK-SD: // %bb.0: // %entry

1840
llvm/test/CodeGen/AArch64/fcvt-fixed.ll
View File

File diff suppressed because it is too large Load Diff

2
llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
; CHECK-SD-LABEL: vector_deinterleave_v2f16_v4f16:

77
llvm/test/CodeGen/AArch64/fp-intrinsics-fp16.ll
View File

@ -1,11 +1,84 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 -mattr=+fullfp16 %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; Check that constrained fp intrinsics are correctly lowered.
; CHECK-GI: warning: Instruction selection used fallback path for add_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sub_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for mul_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for div_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for frem_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fma_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i32_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sitofp_f16_i32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uitofp_f16_i32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sitofp_f16_i64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uitofp_f16_i64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sitofp_f16_i128
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uitofp_f16_i128
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrt_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for powi_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sin_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for cos_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for tan_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for asin_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for acos_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for atan_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for atan2_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sinh_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for cosh_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for tanh_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for pow_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for log_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for log10_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for log2_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for exp_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for exp2_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for rint_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for nearbyint_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for llrint_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for maxnum_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for minnum_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ceil_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for floor_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lround_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for llround_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for round_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for roundeven_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for trunc_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_olt_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_ole_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_ogt_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_oge_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_oeq_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_one_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_ult_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_ule_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_ugt_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_uge_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_ueq_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_une_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_olt_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_ole_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_ogt_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_oge_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_oeq_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_one_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_ult_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_ule_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_ugt_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_uge_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_ueq_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_une_f16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptrunc_f16_f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fpext_f32_f16
; Half-precision intrinsics

85
llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
View File

@ -1,9 +1,86 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 %s -disable-strictnode-mutation -o - | FileCheck %s
; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 -disable-strictnode-mutation %s -o - | FileCheck %s
; RUN: llc -mtriple=aarch64 %s -disable-strictnode-mutation -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -global-isel=true -global-isel-abort=2 -disable-strictnode-mutation %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; Check that constrained fp vector intrinsics are correctly lowered.
; CHECK-GI: warning: Instruction selection used fallback path for add_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sub_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for mul_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for div_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fma_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_v4i32_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_v4i32_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_v4i64_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_v4i64_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sitofp_v4f32_v4i32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uitofp_v4f32_v4i32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sitofp_v4f32_v4i64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uitofp_v4f32_v4i64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrt_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for rint_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for nearbyint_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for maxnum_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for minnum_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ceil_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for floor_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for round_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for roundeven_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for trunc_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_v4f32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for add_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sub_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for mul_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for div_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fma_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_v2i32_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_v2i32_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_v2i64_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_v2i64_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sitofp_v2f64_v2i32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uitofp_v2f64_v2i32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sitofp_v2f64_v2i64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uitofp_v2f64_v2i64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrt_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for rint_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for nearbyint_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for maxnum_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for minnum_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ceil_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for floor_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for round_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for roundeven_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for trunc_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for add_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sub_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for mul_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for div_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fma_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_v1i32_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_v1i32_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_v1i64_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_v1i64_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sitofp_v1f64_v1i32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uitofp_v1f64_v1i32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sitofp_v1f64_v1i64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uitofp_v1f64_v1i64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrt_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for rint_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for nearbyint_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for maxnum_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for minnum_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ceil_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for floor_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for round_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for roundeven_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for trunc_v1f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmp_v1f61
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcmps_v1f61
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptrunc_v2f32_v2f64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fpext_v2f64_v2f32
; Single-precision intrinsics
@ -882,3 +959,7 @@ declare <1 x i1> @llvm.experimental.constrained.fcmps.v1f64(<1 x double>, <1 x d
declare <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(<2 x float>, metadata)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-GI: {{.*}}
; CHECK-SD: {{.*}}

2340
llvm/test/CodeGen/AArch64/fp-intrinsics.ll
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File diff suppressed because it is too large Load Diff

4
llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
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@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-CVT
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-CVT
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-CVT
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
;
; 32-bit float to signed integer

4
llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
View File

@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-CVT
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP16
; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-CVT
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-CVT
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
;
; 32-bit float to unsigned integer

2
llvm/test/CodeGen/AArch64/funnel-shift.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i8 @llvm.fshl.i8(i8, i8, i8)
declare i16 @llvm.fshl.i16(i16, i16, i16)

57
llvm/test/CodeGen/AArch64/itofp-bf16.ll
View File

@ -4,6 +4,63 @@
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-NOFP16
; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP16
; CHECK-GI: warning: Instruction selection used fallback path for stofp_i64_bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_i64_bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_i32_bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_i32_bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_i16_bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_i16_bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_i8_bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_i8_bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v2i64_v2bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v2i64_v2bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v3i64_v3bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v3i64_v3bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v4i64_v4bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v4i64_v4bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v8i64_v8bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v8i64_v8bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v16i64_v16bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v16i64_v16bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v32i64_v32bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v32i64_v32bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v2i32_v2bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v2i32_v2bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v3i32_v3bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v3i32_v3bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v4i32_v4bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v4i32_v4bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v8i32_v8bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v8i32_v8bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v16i32_v16bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v16i32_v16bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v32i32_v32bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v32i32_v32bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v2i16_v2bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v2i16_v2bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v3i16_v3bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v3i16_v3bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v4i16_v4bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v4i16_v4bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v8i16_v8bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v8i16_v8bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v16i16_v16bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v16i16_v16bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v32i16_v32bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v32i16_v32bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v2i8_v2bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v2i8_v2bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v3i8_v3bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v3i8_v3bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v4i8_v4bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v4i8_v4bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v8i8_v8bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v8i8_v8bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v16i8_v16bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v16i8_v16bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for stofp_v32i8_v32bf16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for utofp_v32i8_v32bf16
define bfloat @stofp_i64_bf16(i64 %a) {
; CHECK-LABEL: stofp_i64_bf16:
; CHECK: // %bb.0: // %entry

92
llvm/test/CodeGen/AArch64/mingw-refptr.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=aarch64-w64-mingw32 | FileCheck %s
; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* \
; RUN: -mtriple=aarch64-w64-mingw32 2>&1| FileCheck %s --check-prefixes=GISEL,FALLBACK
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=aarch64-w64-mingw32 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-w64-mingw32 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
@var = external local_unnamed_addr global i32, align 4
@dsolocalvar = external dso_local local_unnamed_addr global i32, align 4
@ -10,10 +10,11 @@
define dso_local i32 @getVar() {
; CHECK-LABEL: getVar:
; CHECK: adrp x8, .refptr.var
; CHECK: ldr x8, [x8, :lo12:.refptr.var]
; CHECK: ldr w0, [x8]
; CHECK: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, .refptr.var
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.var]
; CHECK-NEXT: ldr w0, [x8]
; CHECK-NEXT: ret
entry:
%0 = load i32, ptr @var, align 4
ret i32 %0
@ -21,9 +22,10 @@ entry:
define dso_local i32 @getDsoLocalVar() {
; CHECK-LABEL: getDsoLocalVar:
; CHECK: adrp x8, dsolocalvar
; CHECK: ldr w0, [x8, :lo12:dsolocalvar]
; CHECK: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, dsolocalvar
; CHECK-NEXT: ldr w0, [x8, :lo12:dsolocalvar]
; CHECK-NEXT: ret
entry:
%0 = load i32, ptr @dsolocalvar, align 4
ret i32 %0
@ -31,9 +33,10 @@ entry:
define dso_local i32 @getLocalVar() {
; CHECK-LABEL: getLocalVar:
; CHECK: adrp x8, localvar
; CHECK: ldr w0, [x8, :lo12:localvar]
; CHECK: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, localvar
; CHECK-NEXT: ldr w0, [x8, :lo12:localvar]
; CHECK-NEXT: ret
entry:
%0 = load i32, ptr @localvar, align 4
ret i32 %0
@ -41,9 +44,10 @@ entry:
define dso_local i32 @getLocalCommon() {
; CHECK-LABEL: getLocalCommon:
; CHECK: adrp x8, localcommon
; CHECK: ldr w0, [x8, :lo12:localcommon]
; CHECK: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, localcommon
; CHECK-NEXT: ldr w0, [x8, :lo12:localcommon]
; CHECK-NEXT: ret
entry:
%0 = load i32, ptr @localcommon, align 4
ret i32 %0
@ -51,10 +55,11 @@ entry:
define dso_local i32 @getExtVar() {
; CHECK-LABEL: getExtVar:
; CHECK: adrp x8, __imp_extvar
; CHECK: ldr x8, [x8, :lo12:__imp_extvar]
; CHECK: ldr w0, [x8]
; CHECK: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, __imp_extvar
; CHECK-NEXT: ldr x8, [x8, :lo12:__imp_extvar]
; CHECK-NEXT: ldr w0, [x8]
; CHECK-NEXT: ret
entry:
%0 = load i32, ptr @extvar, align 4
ret i32 %0
@ -62,7 +67,8 @@ entry:
define dso_local void @callFunc() {
; CHECK-LABEL: callFunc:
; CHECK: b otherFunc
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: b otherFunc
entry:
tail call void @otherFunc()
ret void
@ -70,16 +76,40 @@ entry:
declare dso_local void @otherFunc()
; FALLBACK-NOT: remark:{{.*}}sspFunc
define dso_local void @sspFunc() #0 {
; CHECK-LABEL: sspFunc:
; CHECK: adrp x8, .refptr.__stack_chk_guard
; CHECK: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
; CHECK: ldr x8, [x8]
; GISEL-LABEL: sspFunc:
; GISEL: adrp x8, .refptr.__stack_chk_guard
; GISEL: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
; GISEL: ldr x8, [x8]
; CHECK: .seh_proc sspFunc
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: .seh_stackalloc 32
; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
; CHECK-NEXT: .seh_save_reg x30, 16
; CHECK-NEXT: .seh_endprologue
; CHECK-NEXT: adrp x8, .refptr.__stack_chk_guard
; CHECK-NEXT: add x0, sp, #7
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: str x8, [sp, #8]
; CHECK-NEXT: bl ptrUser
; CHECK-NEXT: adrp x8, .refptr.__stack_chk_guard
; CHECK-NEXT: ldr x8, [x8, :lo12:.refptr.__stack_chk_guard]
; CHECK-NEXT: ldr x9, [sp, #8]
; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: b.ne .LBB6_2
; CHECK-NEXT: // %bb.1: // %entry
; CHECK-NEXT: .seh_startepilogue
; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
; CHECK-NEXT: .seh_save_reg x30, 16
; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: .seh_stackalloc 32
; CHECK-NEXT: .seh_endepilogue
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB6_2: // %entry
; CHECK-NEXT: bl __stack_chk_fail
; CHECK-NEXT: brk #0x1
; CHECK-NEXT: .seh_endfunclet
; CHECK-NEXT: .seh_endproc
entry:
%c = alloca i8, align 1
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %c)
@ -102,3 +132,7 @@ attributes #0 = { sspstrong }
; CHECK: .globl .refptr.var
; CHECK: .refptr.var:
; CHECK: .xword var
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-GI: {{.*}}
; CHECK-SD: {{.*}}

2
llvm/test/CodeGen/AArch64/mulcmle.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 %s -o - -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64 %s -o - -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <1 x i64> @v1i64(<1 x i64> %a) {
; CHECK-SD-LABEL: v1i64:

55
llvm/test/CodeGen/AArch64/overflow.ll
View File

@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,SDAG
; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,GISEL
; RUN: llc < %s -mtriple=arm64-eabi -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -global-isel -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define zeroext i1 @saddo1.i32.unused(i32 %v1, i32 %v2, ptr %res) {
; CHECK-LABEL: saddo1.i32.unused:
@ -105,19 +104,19 @@ entry:
ret i1 %obit
}
define zeroext i1 @saddo.add.i32(i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %v5, ptr %res) {
; SDAG-LABEL: saddo.add.i32:
; SDAG: // %bb.0: // %entry
; SDAG-NEXT: add w8, w4, #100
; SDAG-NEXT: subs w8, w8, #100
; SDAG-NEXT: cset w0, vs
; SDAG-NEXT: str w8, [x5]
; SDAG-NEXT: ret
; CHECK-SD-LABEL: saddo.add.i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: add w8, w4, #100
; CHECK-SD-NEXT: subs w8, w8, #100
; CHECK-SD-NEXT: cset w0, vs
; CHECK-SD-NEXT: str w8, [x5]
; CHECK-SD-NEXT: ret
;
; GISEL-LABEL: saddo.add.i32:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: mov w0, wzr
; GISEL-NEXT: str w4, [x5]
; GISEL-NEXT: ret
; CHECK-GI-LABEL: saddo.add.i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mov w0, wzr
; CHECK-GI-NEXT: str w4, [x5]
; CHECK-GI-NEXT: ret
entry:
%lhs = add nsw i32 %v5, 100
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %lhs, i32 -100)
@ -128,20 +127,20 @@ entry:
}
define zeroext i1 @uaddo.add.i32(i32 %v1, i32 %v2, i32 %v3, i32 %v4, i32 %v5, ptr %res) {
; SDAG-LABEL: uaddo.add.i32:
; SDAG: // %bb.0: // %entry
; SDAG-NEXT: add w8, w4, #5
; SDAG-NEXT: adds w8, w8, #5
; SDAG-NEXT: cset w0, hs
; SDAG-NEXT: str w8, [x5]
; SDAG-NEXT: ret
; CHECK-SD-LABEL: uaddo.add.i32:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: add w8, w4, #5
; CHECK-SD-NEXT: adds w8, w8, #5
; CHECK-SD-NEXT: cset w0, hs
; CHECK-SD-NEXT: str w8, [x5]
; CHECK-SD-NEXT: ret
;
; GISEL-LABEL: uaddo.add.i32:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: adds w8, w4, #10
; GISEL-NEXT: cset w0, hs
; GISEL-NEXT: str w8, [x5]
; GISEL-NEXT: ret
; CHECK-GI-LABEL: uaddo.add.i32:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: adds w8, w4, #10
; CHECK-GI-NEXT: cset w0, hs
; CHECK-GI-NEXT: str w8, [x5]
; CHECK-GI-NEXT: ret
entry:
%lhs = add nuw i32 %v5, 5
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %lhs, i32 5)

2
llvm/test/CodeGen/AArch64/phi.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64 -global-isel=0 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -global-isel=1 -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64 -global-isel=1 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i8 @ti8(i1 %c, ptr %p, i8 %a, i8 %b) {
; CHECK-SD-LABEL: ti8:

2
llvm/test/CodeGen/AArch64/sadd_sat.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i4 @llvm.sadd.sat.i4(i4, i4)
declare i8 @llvm.sadd.sat.i8(i8, i8)

2
llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i4 @llvm.sadd.sat.i4(i4, i4)
declare i8 @llvm.sadd.sat.i8(i8, i8)

4
llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
View File

@ -2,6 +2,10 @@
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for v16i4
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128
declare <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8>, <1 x i8>)
declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)
declare <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8>, <4 x i8>)

2
llvm/test/CodeGen/AArch64/sext.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i16 @sext_i8_to_i16(i8 %a) {
; CHECK-LABEL: sext_i8_to_i16:

2
llvm/test/CodeGen/AArch64/ssub_sat.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i4 @llvm.ssub.sat.i4(i4, i4)
declare i8 @llvm.ssub.sat.i8(i8, i8)

2
llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i4 @llvm.ssub.sat.i4(i4, i4)
declare i8 @llvm.ssub.sat.i8(i8, i8)

4
llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
View File

@ -2,6 +2,10 @@
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for v16i4
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128
declare <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8>, <1 x i8>)
declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>)

2
llvm/test/CodeGen/AArch64/uadd_sat.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i4 @llvm.uadd.sat.i4(i4, i4)
declare i8 @llvm.uadd.sat.i8(i8, i8)

2
llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i4 @llvm.uadd.sat.i4(i4, i4)
declare i8 @llvm.uadd.sat.i8(i8, i8)

4
llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
View File

@ -2,6 +2,10 @@
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for v16i4
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128
declare <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8>, <1 x i8>)
declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>)
declare <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8>, <4 x i8>)

2
llvm/test/CodeGen/AArch64/usub_sat.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i4 @llvm.usub.sat.i4(i4, i4)
declare i8 @llvm.usub.sat.i8(i8, i8)

2
llvm/test/CodeGen/AArch64/usub_sat_plus.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i4 @llvm.usub.sat.i4(i4, i4)
declare i8 @llvm.usub.sat.i8(i8, i8)

4
llvm/test/CodeGen/AArch64/usub_sat_vec.ll
View File

@ -2,6 +2,10 @@
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for v16i4
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128
declare <1 x i8> @llvm.usub.sat.v1i8(<1 x i8>, <1 x i8>)
declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>)
declare <4 x i8> @llvm.usub.sat.v4i8(<4 x i8>, <4 x i8>)

2
llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %a)
declare i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %a)