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[polly] Make reduction detection checks more robust - part 2 (#80721)

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Existing reduction detection algorithm does two types of memory checks
before marking a load store pair as reduction.
Second check is to verify there is no other memory access in ScopStmt
overlapping with the memory of load and store that forms the reduction.
Existing check misses cases where there could be probable overlap such
as
	A[V] += A[P];
In the above case there is chance of overlap between A[V] and A[P] which
is missed.
This commit addresses this by removing the parameter from space before
checking for compatible space.

Part 1 of this patch :
[75297](https://github.com/llvm/llvm-project/pull/75297)
This commit is contained in:
Karthika Devi C 2024-02-13 03:19:32 +05:30 committed by GitHub
parent fcef407aa2
commit 283feb42ee
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
4 changed files with 14 additions and 10 deletions
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12
polly/lib/Analysis/ScopBuilder.cpp
View File

@ -2516,15 +2516,19 @@ bool hasIntersectingAccesses(isl::set AllAccs, MemoryAccess *LoadMA,
MemoryAccess *StoreMA, isl::set Domain,
SmallVector<MemoryAccess *, 8> &MemAccs) {
bool HasIntersectingAccs = false;
auto AllAccsNoParams = AllAccs.project_out_all_params();
for (MemoryAccess *MA : MemAccs) {
if (MA == LoadMA || MA == StoreMA)
continue;
auto AccRel = MA->getAccessRelation().intersect_domain(Domain);
auto Accs = AccRel.range();
auto AccsNoParams = Accs.project_out_all_params();
isl::map AccRel = MA->getAccessRelation().intersect_domain(Domain);
isl::set Accs = AccRel.range();
bool CompatibleSpace = AllAccsNoParams.has_equal_space(AccsNoParams);
if (AllAccs.has_equal_space(Accs)) {
isl::set OverlapAccs = Accs.intersect(AllAccs);
if (CompatibleSpace) {
auto OverlapAccs = Accs.intersect(AllAccs);
bool DoesIntersect = !OverlapAccs.is_empty();
HasIntersectingAccs |= DoesIntersect;
}

4
polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_2.ll
View File

@ -44,9 +44,9 @@
; INNERMOST-NEXT: [p_0, p_1, p_2] -> { Stmt_bb16[i0] -> MemRef_A[p_1] };
; INNERMOST-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; INNERMOST-NEXT: [p_0, p_1, p_2] -> { Stmt_bb16[i0] -> MemRef_A[p_2] };
; INNERMOST-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
; INNERMOST-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; INNERMOST-NEXT: [p_0, p_1, p_2] -> { Stmt_bb16[i0] -> MemRef_A[p_0 + i0] };
; INNERMOST-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
; INNERMOST-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; INNERMOST-NEXT: [p_0, p_1, p_2] -> { Stmt_bb16[i0] -> MemRef_A[p_0 + i0] };
; INNERMOST-NEXT: Stmt_bb26
; INNERMOST-NEXT: Domain :=

4
polly/test/ScopInfo/NonAffine/non-affine-loop-condition-dependent-access_3.ll
View File

@ -44,9 +44,9 @@
; INNERMOST-NEXT: [p_0, p_1, p_2] -> { Stmt_bb16[i0] -> MemRef_A[p_1] };
; INNERMOST-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; INNERMOST-NEXT: [p_0, p_1, p_2] -> { Stmt_bb16[i0] -> MemRef_A[p_2] };
; INNERMOST-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
; INNERMOST-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; INNERMOST-NEXT: [p_0, p_1, p_2] -> { Stmt_bb16[i0] -> MemRef_A[i0] };
; INNERMOST-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
; INNERMOST-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; INNERMOST-NEXT: [p_0, p_1, p_2] -> { Stmt_bb16[i0] -> MemRef_A[i0] };
; INNERMOST-NEXT: Stmt_bb26
; INNERMOST-NEXT: Domain :=

4
polly/test/ScopInfo/int2ptr_ptr2int.ll
View File

@ -11,9 +11,9 @@
;
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: [val, ptr] -> { Stmt_for_body[i0] -> MemRef_A[9 + val] };
; CHECK-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: [val, ptr] -> { Stmt_for_body[i0] -> MemRef_A[9 + ptr] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK-NEXT: [val, ptr] -> { Stmt_for_body[i0] -> MemRef_A[9 + ptr] };
;
; IR: entry: