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[SPIR-V] Add implementation of the non-const G_BUILD_VECTOR and fix emission of the OpGroupBroadcast instruction (#103050)
This PR addresses a TODO in lib/Target/SPIRV/SPIRVInstructionSelector.cpp by adding implementation of the non-const G_BUILD_VECTOR, and fix emission of the OpGroupBroadcast instruction for the case when the `..._group_broadcast` builtin has more than one `local_id` argument and `OpGroupBroadcast` requires a newly constructed vector with 2 or 3 components instead of originally passed series of `local_id` arguments. This PR may resolve https://github.com/llvm/llvm-project/issues/97310 if the reason for the reported fail is an incorrectly generated OpGroupBroadcast instruction that was definitely a case. Existing test is hardened and a new test is added to cover this special case of the OpGroupBroadcast instruction emission.
This commit is contained in:
Vyacheslav Levytskyy
GitHub
parent
c4206f1ff1
commit
2fc7a72733
@ -1135,6 +1135,35 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
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: SPIRV::Scope::Workgroup;
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Register ScopeRegister = buildConstantIntReg(Scope, MIRBuilder, GR);
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Register VecReg;
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if (GroupBuiltin->Opcode == SPIRV::OpGroupBroadcast &&
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Call->Arguments.size() > 2) {
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// For OpGroupBroadcast "LocalId must be an integer datatype. It must be a
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// scalar, a vector with 2 components, or a vector with 3 components.",
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// meaning that we must create a vector from the function arguments if
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// it's a work_group_broadcast(val, local_id_x, local_id_y) or
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// work_group_broadcast(val, local_id_x, local_id_y, local_id_z) call.
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Register ElemReg = Call->Arguments[1];
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SPIRVType *ElemType = GR->getSPIRVTypeForVReg(ElemReg);
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if (!ElemType || ElemType->getOpcode() != SPIRV::OpTypeInt)
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report_fatal_error("Expect an integer <LocalId> argument");
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unsigned VecLen = Call->Arguments.size() - 1;
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VecReg = MRI->createGenericVirtualRegister(
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LLT::fixed_vector(VecLen, MRI->getType(ElemReg)));
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MRI->setRegClass(VecReg, &SPIRV::vIDRegClass);
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SPIRVType *VecType =
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GR->getOrCreateSPIRVVectorType(ElemType, VecLen, MIRBuilder);
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GR->assignSPIRVTypeToVReg(VecType, VecReg, MIRBuilder.getMF());
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auto MIB =
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MIRBuilder.buildInstr(TargetOpcode::G_BUILD_VECTOR).addDef(VecReg);
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for (unsigned i = 1; i < Call->Arguments.size(); i++) {
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MIB.addUse(Call->Arguments[i]);
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MRI->setRegClass(Call->Arguments[i], &SPIRV::iIDRegClass);
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}
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insertAssignInstr(VecReg, nullptr, VecType, GR, MIRBuilder,
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MIRBuilder.getMF().getRegInfo());
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}
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// Build work/sub group instruction.
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auto MIB = MIRBuilder.buildInstr(GroupBuiltin->Opcode)
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.addDef(GroupResultRegister)
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@ -1146,10 +1175,13 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
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if (Call->Arguments.size() > 0) {
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MIB.addUse(Arg0.isValid() ? Arg0 : Call->Arguments[0]);
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MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
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for (unsigned i = 1; i < Call->Arguments.size(); i++) {
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MIB.addUse(Call->Arguments[i]);
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MRI->setRegClass(Call->Arguments[i], &SPIRV::iIDRegClass);
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}
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if (VecReg.isValid())
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MIB.addUse(VecReg);
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else
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for (unsigned i = 1; i < Call->Arguments.size(); i++) {
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MIB.addUse(Call->Arguments[i]);
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MRI->setRegClass(Call->Arguments[i], &SPIRV::iIDRegClass);
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}
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}
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// Build select instruction.
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@ -159,7 +159,7 @@ private:
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bool selectBitreverse(Register ResVReg, const SPIRVType *ResType,
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MachineInstr &I) const;
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bool selectConstVector(Register ResVReg, const SPIRVType *ResType,
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bool selectBuildVector(Register ResVReg, const SPIRVType *ResType,
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MachineInstr &I) const;
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bool selectSplatVector(Register ResVReg, const SPIRVType *ResType,
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MachineInstr &I) const;
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@ -411,7 +411,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
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return selectBitreverse(ResVReg, ResType, I);
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case TargetOpcode::G_BUILD_VECTOR:
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return selectConstVector(ResVReg, ResType, I);
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return selectBuildVector(ResVReg, ResType, I);
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case TargetOpcode::G_SPLAT_VECTOR:
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return selectSplatVector(ResVReg, ResType, I);
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@ -1497,35 +1497,6 @@ bool SPIRVInstructionSelector::selectFreeze(Register ResVReg,
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return false;
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}
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bool SPIRVInstructionSelector::selectConstVector(Register ResVReg,
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const SPIRVType *ResType,
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MachineInstr &I) const {
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// TODO: only const case is supported for now.
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assert(std::all_of(
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I.operands_begin(), I.operands_end(), [this](const MachineOperand &MO) {
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if (MO.isDef())
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return true;
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if (!MO.isReg())
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return false;
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SPIRVType *ConstTy = this->MRI->getVRegDef(MO.getReg());
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assert(ConstTy && ConstTy->getOpcode() == SPIRV::ASSIGN_TYPE &&
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ConstTy->getOperand(1).isReg());
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Register ConstReg = ConstTy->getOperand(1).getReg();
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const MachineInstr *Const = this->MRI->getVRegDef(ConstReg);
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assert(Const);
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return (Const->getOpcode() == TargetOpcode::G_CONSTANT ||
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Const->getOpcode() == TargetOpcode::G_FCONSTANT);
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}));
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auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
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TII.get(SPIRV::OpConstantComposite))
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.addDef(ResVReg)
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.addUse(GR.getSPIRVTypeID(ResType));
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for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i)
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MIB.addUse(I.getOperand(i).getReg());
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return MIB.constrainAllUses(TII, TRI, RBI);
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}
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static unsigned getArrayComponentCount(MachineRegisterInfo *MRI,
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const SPIRVType *ResType) {
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Register OpReg = ResType->getOperand(2).getReg();
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@ -1591,6 +1562,40 @@ static bool isConstReg(MachineRegisterInfo *MRI, Register OpReg) {
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return false;
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}
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bool SPIRVInstructionSelector::selectBuildVector(Register ResVReg,
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const SPIRVType *ResType,
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MachineInstr &I) const {
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unsigned N = 0;
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if (ResType->getOpcode() == SPIRV::OpTypeVector)
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N = GR.getScalarOrVectorComponentCount(ResType);
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else if (ResType->getOpcode() == SPIRV::OpTypeArray)
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N = getArrayComponentCount(MRI, ResType);
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else
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report_fatal_error("Cannot select G_BUILD_VECTOR with a non-vector result");
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if (I.getNumExplicitOperands() - I.getNumExplicitDefs() != N)
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report_fatal_error("G_BUILD_VECTOR and the result type are inconsistent");
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// check if we may construct a constant vector
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bool IsConst = true;
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for (unsigned i = I.getNumExplicitDefs();
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i < I.getNumExplicitOperands() && IsConst; ++i)
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if (!isConstReg(MRI, I.getOperand(i).getReg()))
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IsConst = false;
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if (!IsConst && N < 2)
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report_fatal_error(
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"There must be at least two constituent operands in a vector");
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auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
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TII.get(IsConst ? SPIRV::OpConstantComposite
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: SPIRV::OpCompositeConstruct))
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.addDef(ResVReg)
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.addUse(GR.getSPIRVTypeID(ResType));
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for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i)
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MIB.addUse(I.getOperand(i).getReg());
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return MIB.constrainAllUses(TII, TRI, RBI);
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}
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bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg,
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const SPIRVType *ResType,
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MachineInstr &I) const {
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@ -530,15 +530,23 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
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MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg());
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assert(ElemMI);
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if (ElemMI->getOpcode() == TargetOpcode::G_CONSTANT)
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if (ElemMI->getOpcode() == TargetOpcode::G_CONSTANT) {
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ElemTy = ElemMI->getOperand(1).getCImm()->getType();
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else if (ElemMI->getOpcode() == TargetOpcode::G_FCONSTANT)
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} else if (ElemMI->getOpcode() == TargetOpcode::G_FCONSTANT) {
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ElemTy = ElemMI->getOperand(1).getFPImm()->getType();
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} else {
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// There may be a case when we already know Reg's type.
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MachineInstr *NextMI = MI.getNextNode();
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if (!NextMI || NextMI->getOpcode() != SPIRV::ASSIGN_TYPE ||
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NextMI->getOperand(1).getReg() != Reg)
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llvm_unreachable("Unexpected opcode");
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}
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if (ElemTy)
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Ty = VectorType::get(
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ElemTy, MI.getNumExplicitOperands() - MI.getNumExplicitDefs(),
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false);
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else
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llvm_unreachable("Unexpected opcode");
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unsigned NumElts =
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MI.getNumExplicitOperands() - MI.getNumExplicitDefs();
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Ty = VectorType::get(ElemTy, NumElts, false);
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NeedAssignType = false;
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}
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if (NeedAssignType)
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insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MRI);
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152
llvm/test/CodeGen/SPIRV/transcoding/OpGroupBroadcast.ll
Normal file
152
llvm/test/CodeGen/SPIRV/transcoding/OpGroupBroadcast.ll
Normal file
@ -0,0 +1,152 @@
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; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-SPIRV: OpCapability Groups
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; CHECK-SPIRV-DAG: %[[#Int32Ty:]] = OpTypeInt 32 0
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; CHECK-SPIRV-DAG: %[[#Int64Ty:]] = OpTypeInt 64 0
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; CHECK-SPIRV-DAG: %[[#Float32Ty:]] = OpTypeFloat 32
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; CHECK-SPIRV-DAG: %[[#Vec2Int32Ty:]] = OpTypeVector %[[#Int32Ty]] 2
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; CHECK-SPIRV-DAG: %[[#Vec3Int32Ty:]] = OpTypeVector %[[#Int32Ty]] 3
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; CHECK-SPIRV-DAG: %[[#Vec2Int64Ty:]] = OpTypeVector %[[#Int64Ty]] 2
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; CHECK-SPIRV-DAG: %[[#C2:]] = OpConstant %[[#Int32Ty]] 2
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; CHECK-SPIRV: OpFunction
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; CHECK-SPIRV: %[[#Val:]] = OpFunctionParameter %[[#Int32Ty]]
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; CHECK-SPIRV: %[[#X:]] = OpFunctionParameter %[[#Int32Ty]]
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; CHECK-SPIRV: %[[#Y:]] = OpFunctionParameter %[[#Int32Ty]]
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; CHECK-SPIRV: %[[#Z:]] = OpFunctionParameter %[[#Int32Ty]]
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; CHECK-SPIRV: %[[#]] = OpGroupBroadcast %[[#Int32Ty]] %[[#C2]] %[[#Val]] %[[#X]]
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; CHECK-SPIRV: %[[#XY:]] = OpCompositeConstruct %[[#Vec2Int32Ty]] %[[#X]] %[[#Y]]
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; CHECK-SPIRV: %[[#]] = OpGroupBroadcast %[[#Int32Ty]] %[[#C2]] %[[#Val]] %[[#XY]]
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; CHECK-SPIRV: %[[#XYZ:]] = OpCompositeConstruct %[[#Vec3Int32Ty]] %[[#X]] %[[#Y]] %[[#Z]]
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; CHECK-SPIRV: %[[#]] = OpGroupBroadcast %[[#Int32Ty]] %[[#C2]] %[[#Val]] %[[#XYZ]]
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define spir_kernel void @test_broadcast_xyz(i32 noundef %a, i32 noundef %x, i32 noundef %y, i32 noundef %z) {
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entry:
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%call1 = call spir_func i32 @_Z20work_group_broadcastjj(i32 noundef %a, i32 noundef %x)
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%call2 = call spir_func i32 @_Z20work_group_broadcastjj(i32 noundef %a, i32 noundef %x, i32 noundef %y)
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%call3 = call spir_func i32 @_Z20work_group_broadcastjj(i32 noundef %a, i32 noundef %x, i32 noundef %y, i32 noundef %z)
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ret void
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}
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declare spir_func i32 @_Z20work_group_broadcastjj(i32, i32)
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declare spir_func i32 @_Z20work_group_broadcastjjj(i32, i32, i32)
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declare spir_func i32 @_Z20work_group_broadcastjjjj(i32, i32, i32, i32)
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; CHECK-SPIRV: OpFunction
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; CHECK-SPIRV: OpInBoundsPtrAccessChain
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; CHECK-SPIRV: %[[#LoadedVal:]] = OpLoad %[[#Float32Ty]] %[[#]]
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; CHECK-SPIRV: %[[#IdX:]] = OpCompositeExtract %[[#Int64Ty]] %[[#]] 0
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; CHECK-SPIRV: %[[#IdY:]] = OpCompositeExtract %[[#Int64Ty]] %[[#]] 1
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; CHECK-SPIRV: %[[#LocIdsVec:]] = OpCompositeConstruct %[[#Vec2Int64Ty]] %[[#IdX]] %[[#IdY]]
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; CHECK-SPIRV: %[[#]] = OpGroupBroadcast %[[#Float32Ty]] %[[#C2]] %[[#LoadedVal]] %[[#LocIdsVec]]
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define spir_kernel void @test_wg_broadcast_2D(ptr addrspace(1) %input, ptr addrspace(1) %output) #0 !kernel_arg_addr_space !7 !kernel_arg_access_qual !8 !kernel_arg_type !9 !kernel_arg_type_qual !10 !kernel_arg_base_type !9 !spirv.ParameterDecorations !11 {
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entry:
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%0 = call spir_func i64 @_Z13get_global_idj(i32 0) #1
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%1 = insertelement <3 x i64> undef, i64 %0, i32 0
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%2 = call spir_func i64 @_Z13get_global_idj(i32 1) #1
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%3 = insertelement <3 x i64> %1, i64 %2, i32 1
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%4 = call spir_func i64 @_Z13get_global_idj(i32 2) #1
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%5 = insertelement <3 x i64> %3, i64 %4, i32 2
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%call = extractelement <3 x i64> %5, i32 0
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%6 = call spir_func i64 @_Z13get_global_idj(i32 0) #1
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%7 = insertelement <3 x i64> undef, i64 %6, i32 0
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%8 = call spir_func i64 @_Z13get_global_idj(i32 1) #1
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%9 = insertelement <3 x i64> %7, i64 %8, i32 1
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%10 = call spir_func i64 @_Z13get_global_idj(i32 2) #1
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%11 = insertelement <3 x i64> %9, i64 %10, i32 2
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%call1 = extractelement <3 x i64> %11, i32 1
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%12 = call spir_func i64 @_Z12get_group_idj(i32 0) #1
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%13 = insertelement <3 x i64> undef, i64 %12, i32 0
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%14 = call spir_func i64 @_Z12get_group_idj(i32 1) #1
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%15 = insertelement <3 x i64> %13, i64 %14, i32 1
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%16 = call spir_func i64 @_Z12get_group_idj(i32 2) #1
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%17 = insertelement <3 x i64> %15, i64 %16, i32 2
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%call2 = extractelement <3 x i64> %17, i32 0
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%18 = call spir_func i64 @_Z14get_local_sizej(i32 0) #1
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%19 = insertelement <3 x i64> undef, i64 %18, i32 0
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%20 = call spir_func i64 @_Z14get_local_sizej(i32 1) #1
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%21 = insertelement <3 x i64> %19, i64 %20, i32 1
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%22 = call spir_func i64 @_Z14get_local_sizej(i32 2) #1
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%23 = insertelement <3 x i64> %21, i64 %22, i32 2
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%call3 = extractelement <3 x i64> %23, i32 0
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%rem = urem i64 %call2, %call3
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%24 = call spir_func i64 @_Z12get_group_idj(i32 0) #1
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%25 = insertelement <3 x i64> undef, i64 %24, i32 0
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%26 = call spir_func i64 @_Z12get_group_idj(i32 1) #1
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%27 = insertelement <3 x i64> %25, i64 %26, i32 1
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%28 = call spir_func i64 @_Z12get_group_idj(i32 2) #1
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%29 = insertelement <3 x i64> %27, i64 %28, i32 2
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%call4 = extractelement <3 x i64> %29, i32 1
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%30 = call spir_func i64 @_Z14get_local_sizej(i32 0) #1
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%31 = insertelement <3 x i64> undef, i64 %30, i32 0
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%32 = call spir_func i64 @_Z14get_local_sizej(i32 1) #1
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%33 = insertelement <3 x i64> %31, i64 %32, i32 1
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%34 = call spir_func i64 @_Z14get_local_sizej(i32 2) #1
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%35 = insertelement <3 x i64> %33, i64 %34, i32 2
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%call5 = extractelement <3 x i64> %35, i32 1
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%rem6 = urem i64 %call4, %call5
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%36 = call spir_func i64 @_Z15get_global_sizej(i32 0) #1
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%37 = insertelement <3 x i64> undef, i64 %36, i32 0
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%38 = call spir_func i64 @_Z15get_global_sizej(i32 1) #1
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%39 = insertelement <3 x i64> %37, i64 %38, i32 1
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%40 = call spir_func i64 @_Z15get_global_sizej(i32 2) #1
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%41 = insertelement <3 x i64> %39, i64 %40, i32 2
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%call7 = extractelement <3 x i64> %41, i32 0
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%mul = mul i64 %call1, %call7
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%add = add i64 %mul, %call
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%arrayidx = getelementptr inbounds float, ptr addrspace(1) %input, i64 %add
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%42 = load float, ptr addrspace(1) %arrayidx, align 4
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%.splatinsert = insertelement <2 x i64> undef, i64 %rem, i32 0
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%.splat = shufflevector <2 x i64> %.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
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%43 = insertelement <2 x i64> %.splat, i64 %rem6, i32 1
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%44 = extractelement <2 x i64> %43, i32 0
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%45 = extractelement <2 x i64> %43, i32 1
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%call8 = call spir_func float @_Z20work_group_broadcastfmm(float %42, i64 %44, i64 %45) #2
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%arrayidx9 = getelementptr inbounds float, ptr addrspace(1) %output, i64 %add
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store float %call8, ptr addrspace(1) %arrayidx9, align 4
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ret void
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}
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; Function Attrs: nounwind willreturn memory(none)
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declare spir_func i64 @_Z13get_global_idj(i32) #1
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; Function Attrs: nounwind willreturn memory(none)
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declare spir_func i64 @_Z12get_group_idj(i32) #1
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; Function Attrs: nounwind willreturn memory(none)
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declare spir_func i64 @_Z14get_local_sizej(i32) #1
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; Function Attrs: nounwind willreturn memory(none)
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declare spir_func i64 @_Z15get_global_sizej(i32) #1
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; Function Attrs: convergent nounwind
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declare spir_func float @_Z20work_group_broadcastfmm(float, i64, i64) #2
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind willreturn memory(none) }
|
||||
attributes #2 = { convergent nounwind }
|
||||
|
||||
!spirv.MemoryModel = !{!0}
|
||||
!opencl.enable.FP_CONTRACT = !{}
|
||||
!spirv.Source = !{!1}
|
||||
!opencl.spir.version = !{!2}
|
||||
!opencl.ocl.version = !{!3}
|
||||
!opencl.used.extensions = !{!4}
|
||||
!opencl.used.optional.core.features = !{!5}
|
||||
!spirv.Generator = !{!6}
|
||||
|
||||
!0 = !{i32 2, i32 2}
|
||||
!1 = !{i32 3, i32 300000}
|
||||
!2 = !{i32 2, i32 0}
|
||||
!3 = !{i32 3, i32 0}
|
||||
!4 = !{!"cl_khr_subgroups"}
|
||||
!5 = !{}
|
||||
!6 = !{i16 6, i16 14}
|
||||
!7 = !{i32 1, i32 1}
|
||||
!8 = !{!"none", !"none"}
|
||||
!9 = !{!"float*", !"float*"}
|
||||
!10 = !{!"", !""}
|
||||
!11 = !{!5, !5}
|
||||
@ -5,6 +5,8 @@
|
||||
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
|
||||
|
||||
; CHECK-SPIRV-DAG: %[[#int:]] = OpTypeInt 32 0
|
||||
; CHECK-SPIRV-DAG: %[[#intv2:]] = OpTypeVector %[[#int]] 2
|
||||
; CHECK-SPIRV-DAG: %[[#intv3:]] = OpTypeVector %[[#int]] 3
|
||||
; CHECK-SPIRV-DAG: %[[#float:]] = OpTypeFloat 32
|
||||
; CHECK-SPIRV-DAG: %[[#ScopeCrossWorkgroup:]] = OpConstant %[[#int]] 0
|
||||
; CHECK-SPIRV-DAG: %[[#ScopeWorkgroup:]] = OpConstant %[[#int]] 2
|
||||
@ -252,6 +254,10 @@ declare spir_func i32 @_Z21work_group_reduce_minj(i32 noundef) local_unnamed_add
|
||||
|
||||
; CHECK-SPIRV: OpFunction
|
||||
; CHECK-SPIRV: %[[#]] = OpGroupBroadcast %[[#int]] %[[#ScopeWorkgroup]] %[[#BroadcastValue:]] %[[#BroadcastLocalId:]]
|
||||
; CHECK-SPIRV: %[[#BroadcastVec2:]] = OpCompositeConstruct %[[#intv2]] %[[#BroadcastLocalId]] %[[#BroadcastLocalId]]
|
||||
; CHECK-SPIRV: %[[#]] = OpGroupBroadcast %[[#int]] %[[#ScopeWorkgroup]] %[[#BroadcastValue]] %[[#BroadcastVec2]]
|
||||
; CHECK-SPIRV: %[[#BroadcastVec3:]] = OpCompositeConstruct %[[#intv3]] %[[#BroadcastLocalId]] %[[#BroadcastLocalId]] %[[#BroadcastLocalId]]
|
||||
; CHECK-SPIRV: %[[#]] = OpGroupBroadcast %[[#int]] %[[#ScopeWorkgroup]] %[[#BroadcastValue]] %[[#BroadcastVec3]]
|
||||
; CHECK-SPIRV: %[[#]] = OpGroupBroadcast %[[#int]] %[[#ScopeCrossWorkgroup]] %[[#BroadcastValue]] %[[#BroadcastLocalId]]
|
||||
; CHECK-SPIRV: OpFunctionEnd
|
||||
|
||||
@ -263,12 +269,16 @@ define dso_local spir_kernel void @testWorkGroupBroadcast(i32 noundef %a, i32 ad
|
||||
entry:
|
||||
%0 = load i32, i32 addrspace(1)* %id, align 4
|
||||
%call = call spir_func i32 @_Z20work_group_broadcastjj(i32 noundef %a, i32 noundef %0)
|
||||
%call_v2 = call spir_func i32 @_Z20work_group_broadcastjj(i32 noundef %a, i32 noundef %0, i32 noundef %0)
|
||||
%call_v3 = call spir_func i32 @_Z20work_group_broadcastjj(i32 noundef %a, i32 noundef %0, i32 noundef %0, i32 noundef %0)
|
||||
store i32 %call, i32 addrspace(1)* %res, align 4
|
||||
%call1 = call spir_func i32 @__spirv_GroupBroadcast(i32 0, i32 noundef %a, i32 noundef %0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare spir_func i32 @_Z20work_group_broadcastjj(i32 noundef, i32 noundef) local_unnamed_addr
|
||||
declare spir_func i32 @_Z20work_group_broadcastjjj(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr
|
||||
declare spir_func i32 @_Z20work_group_broadcastjjjj(i32 noundef, i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr
|
||||
declare spir_func i32 @__spirv_GroupBroadcast(i32 noundef, i32 noundef, i32 noundef) local_unnamed_addr
|
||||
|
||||
; CHECK-SPIRV: OpFunction
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user