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[libunwind][RISCV] Make asm statement volatile (#130286)

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Compiling with `O3`, the `early-machinelicm` pass hoisted the asm
statement to a path that has been executed unconditionally during stack
unwinding. On hardware without vector extension support, this resulted
in reading a nonexistent register.
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Gergely Futo 2025-03-10 10:13:33 +01:00 committed by GitHub
parent 0264d42dc7
commit 3acfef56b1
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1 changed files with 1 additions and 1 deletions
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libunwind/src/Registers.hpp
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@ -4126,7 +4126,7 @@ inline reg_t Registers_riscv::getRegister(int regNum) const {
return _registers[regNum];
if (regNum == UNW_RISCV_VLENB) {
reg_t vlenb;
__asm__("csrr %0, 0xC22" : "=r"(vlenb));
__asm__ volatile("csrr %0, 0xC22" : "=r"(vlenb));
return vlenb;
}
_LIBUNWIND_ABORT("unsupported riscv register");