From 3acfef56b1c5f74edd6ea2111a440677ea2c6763 Mon Sep 17 00:00:00 2001
From: Gergely Futo <gergely.futo@hightec-rt.com>
Date: Mon, 10 Mar 2025 10:13:33 +0100
Subject: [PATCH] [libunwind][RISCV] Make asm statement volatile (#130286)

Compiling with `O3`, the `early-machinelicm` pass hoisted the asm
statement to a path that has been executed unconditionally during stack
unwinding. On hardware without vector extension support, this resulted
in reading a nonexistent register.
---
 libunwind/src/Registers.hpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libunwind/src/Registers.hpp b/libunwind/src/Registers.hpp
index 452f46a0d56e..2c3bfb7e8428 100644
--- a/libunwind/src/Registers.hpp
+++ b/libunwind/src/Registers.hpp
@@ -4126,7 +4126,7 @@ inline reg_t Registers_riscv::getRegister(int regNum) const {
     return _registers[regNum];
   if (regNum == UNW_RISCV_VLENB) {
     reg_t vlenb;
-    __asm__("csrr %0, 0xC22" : "=r"(vlenb));
+    __asm__ volatile("csrr %0, 0xC22" : "=r"(vlenb));
     return vlenb;
   }
   _LIBUNWIND_ABORT("unsupported riscv register");