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[RISCV] Check S0 register list check for qc.cm.pushfp to after we parsed the whole register list. (#134180)

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This is more of a semantic check. The diagnostic location to has been
changed to point at the register list start instead of the
closing brace or whatever character might be there instead of a brace
if its malformed.
This commit is contained in:
Craig Topper 2025-04-02 21:48:48 -07:00 committed by GitHub
parent 4998273189
commit 3ea7902494
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GPG Key ID: B5690EEEBB952194
2 changed files with 6 additions and 16 deletions
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20
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
View File

@ -2592,20 +2592,8 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
return Error(getLoc(), "register list must start from 'ra' or 'x1'");
getLexer().Lex();
bool SeenComma = parseOptionalToken(AsmToken::Comma);
// There are two choices here:
// - `s0` is not required (usual case), so only try to parse `s0` if there is
// a comma
// - `s0` is required (qc.cm.pushfp), and so we must see the comma between
// `ra` and `s0` and must always try to parse `s0`, below
if (MustIncludeS0 && !SeenComma) {
Error(getLoc(), "register list must include 's0' or 'x8'");
return ParseStatus::Failure;
}
// parse case like ,s0 (knowing the comma must be there if required)
if (SeenComma) {
if (parseOptionalToken(AsmToken::Comma)) {
if (getLexer().isNot(AsmToken::Identifier))
return Error(getLoc(), "invalid register");
StringRef RegName = getLexer().getTok().getIdentifier();
@ -2668,8 +2656,10 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
auto Encode = RISCVZC::encodeRlist(RegEnd, IsRVE);
assert(Encode != RISCVZC::INVALID_RLIST);
if (MustIncludeS0)
assert(Encode != RISCVZC::RA);
if (MustIncludeS0 && Encode == RISCVZC::RA)
return Error(S, "register list must include 's0' or 'x8'");
Operands.push_back(RISCVOperand::createRlist(Encode, S));
return ParseStatus::Success;

2
llvm/test/MC/RISCV/rv32xqccmp-invalid.s
View File

@ -34,6 +34,6 @@ qc.cm.pushfp {ra, s0}, -12
# CHECK-ERROR: :[[@LINE+1]]:24: error: stack adjustment for register list must be a multiple of 16 bytes in the range [16, 64]
qc.cm.pop {ra, s0-s1}, -40
# CHECK-ERROR: :[[@LINE+1]]:17: error: register list must include 's0' or 'x8'
# CHECK-ERROR: :[[@LINE+1]]:14: error: register list must include 's0' or 'x8'
qc.cm.pushfp {ra}, -16