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[InstCombine] Add test for missing (or (zext x), (shl (ashr x, bw-1))) -> (sext x) case
#129363 handled all the cases where there was a sext for the original source value, but not for cases where the source is already half the size of the destination type Another regression noticed in #76524
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@ -89,6 +89,31 @@ entry:
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ret void
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}
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; (non)ext split from i64 to i128
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define void @i128_ext_split_store_i64(i64 %x, ptr %out) {
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; CHECK-LABEL: define void @i128_ext_split_store_i64(
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; CHECK-SAME: i64 [[X:%.*]], ptr [[OUT:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[LO:%.*]] = zext i64 [[X]] to i128
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; CHECK-NEXT: [[SIGN:%.*]] = ashr i64 [[X]], 63
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; CHECK-NEXT: [[WIDEN:%.*]] = zext i64 [[SIGN]] to i128
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; CHECK-NEXT: [[HI:%.*]] = shl nuw i128 [[WIDEN]], 64
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; CHECK-NEXT: [[RES:%.*]] = or disjoint i128 [[HI]], [[LO]]
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; CHECK-NEXT: store i128 [[RES]], ptr [[OUT]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%lo = zext i64 %x to i128
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%sign = ashr i64 %x, 63
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%widen = zext i64 %sign to i128
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%hi = shl nuw i128 %widen, 64
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%res = or disjoint i128 %hi, %lo
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store i128 %res, ptr %out, align 16
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ret void
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}
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; negative test - wrong constant value
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define i128 @i128_ext_split_neg1(i32 %x) {
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; CHECK-LABEL: define i128 @i128_ext_split_neg1(
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