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[llvm] Use std::size instead of llvm::array_lengthof

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LLVM contains a helpful function for getting the size of a C-style
array: `llvm::array_lengthof`. This is useful prior to C++17, but not as
helpful for C++17 or later: `std::size` already has support for C-style
arrays.

Change call sites to use `std::size` instead.

Differential Revision: https://reviews.llvm.org/D133429
This commit is contained in:
Joe Loser 2022-09-06 18:06:58 -06:00
parent 7aec9ddcfd
commit 5e96cea1db
69 changed files with 182 additions and 192 deletions
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25
llvm/include/llvm/CodeGen/TargetLowering.h
View File

@ -935,7 +935,7 @@ public:
/// promotions or expansions.
bool isTypeLegal(EVT VT) const {
assert(!VT.isSimple() ||
(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
(unsigned)VT.getSimpleVT().SimpleTy < std::size(RegClassForVT));
return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
}
@ -1110,7 +1110,8 @@ public:
if (VT.isExtended()) return Expand;
// If a target-specific SDNode requires legalization, require the target
// to provide custom legalization for it.
if (Op >= array_lengthof(OpActions[0])) return Custom;
if (Op >= std::size(OpActions[0]))
return Custom;
return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
}
@ -1417,8 +1418,8 @@ public:
/// expander for it.
LegalizeAction
getCondCodeAction(ISD::CondCode CC, MVT VT) const {
assert((unsigned)CC < array_lengthof(CondCodeActions) &&
((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
assert((unsigned)CC < std::size(CondCodeActions) &&
((unsigned)VT.SimpleTy >> 3) < std::size(CondCodeActions[0]) &&
"Table isn't big enough!");
// See setCondCodeAction for how this is encoded.
uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
@ -1526,7 +1527,7 @@ public:
/// Return the type of registers that this ValueType will eventually require.
MVT getRegisterType(MVT VT) const {
assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
assert((unsigned)VT.SimpleTy < std::size(RegisterTypeForVT));
return RegisterTypeForVT[VT.SimpleTy];
}
@ -1534,7 +1535,7 @@ public:
MVT getRegisterType(LLVMContext &Context, EVT VT) const {
if (VT.isSimple()) {
assert((unsigned)VT.getSimpleVT().SimpleTy <
array_lengthof(RegisterTypeForVT));
std::size(RegisterTypeForVT));
return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
}
if (VT.isVector()) {
@ -1567,7 +1568,7 @@ public:
Optional<MVT> RegisterVT = None) const {
if (VT.isSimple()) {
assert((unsigned)VT.getSimpleVT().SimpleTy <
array_lengthof(NumRegistersForVT));
std::size(NumRegistersForVT));
return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
}
if (VT.isVector()) {
@ -1635,7 +1636,7 @@ public:
/// If true, the target has custom DAG combine transformations that it can
/// perform for the specified node.
bool hasTargetDAGCombine(ISD::NodeType NT) const {
assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray));
return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
}
@ -2298,7 +2299,7 @@ protected:
/// specified value type. This indicates the selector can handle values of
/// that class natively.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
assert((unsigned)VT.SimpleTy < std::size(RegClassForVT));
RegClassForVT[VT.SimpleTy] = RC;
}
@ -2315,7 +2316,7 @@ protected:
/// type and indicate what to do about it. Note that VT may refer to either
/// the type of a result or that of an operand of Op.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) {
assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
assert(Op < std::size(OpActions[0]) && "Table isn't big enough!");
OpActions[(unsigned)VT.SimpleTy][Op] = Action;
}
void setOperationAction(ArrayRef<unsigned> Ops, MVT VT,
@ -2417,7 +2418,7 @@ protected:
void setCondCodeAction(ArrayRef<ISD::CondCode> CCs, MVT VT,
LegalizeAction Action) {
for (auto CC : CCs) {
assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
assert(VT.isValid() && (unsigned)CC < std::size(CondCodeActions) &&
"Table isn't big enough!");
assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
/// The lower 3 bits of the SimpleTy index into Nth 4bit set from the
@ -2454,7 +2455,7 @@ protected:
/// PerformDAGCombine virtual method.
void setTargetDAGCombine(ArrayRef<ISD::NodeType> NTs) {
for (auto NT : NTs) {
assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
assert(unsigned(NT >> 3) < std::size(TargetDAGCombineArray));
TargetDAGCombineArray[NT >> 3] |= 1 << (NT & 7);
}
}

8
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -4311,7 +4311,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle(
// The input vector this mask element indexes into.
unsigned Input = (unsigned)Idx / NewElts;
if (Input >= array_lengthof(Inputs)) {
if (Input >= std::size(Inputs)) {
// The mask element does not index into any input vector.
Ops.push_back(-1);
continue;
@ -4322,7 +4322,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle(
// Find or create a shuffle vector operand to hold this input.
unsigned OpNo;
for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
for (OpNo = 0; OpNo < std::size(InputUsed); ++OpNo) {
if (InputUsed[OpNo] == Input) {
// This input vector is already an operand.
break;
@ -4333,7 +4333,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle(
}
}
if (OpNo >= array_lengthof(InputUsed)) {
if (OpNo >= std::size(InputUsed)) {
// More than two input vectors used! Give up on trying to create a
// shuffle vector. Insert all elements into a BUILD_VECTOR instead.
UseBuildVector = true;
@ -4356,7 +4356,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle(
// The input vector this mask element indexes into.
unsigned Input = (unsigned)Idx / NewElts;
if (Input >= array_lengthof(Inputs)) {
if (Input >= std::size(Inputs)) {
// The mask element is "undef" or indexes off the end of the input.
SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0));
continue;

14
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -2378,7 +2378,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
&DL](SmallVectorImpl<int> &Mask) {
// Check if all inputs are shuffles of the same operands or non-shuffles.
MapVector<std::pair<SDValue, SDValue>, SmallVector<unsigned>> ShufflesIdxs;
for (unsigned Idx = 0; Idx < array_lengthof(Inputs); ++Idx) {
for (unsigned Idx = 0; Idx < std::size(Inputs); ++Idx) {
SDValue Input = Inputs[Idx];
auto *Shuffle = dyn_cast<ShuffleVectorSDNode>(Input.getNode());
if (!Shuffle ||
@ -2425,7 +2425,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
ShufflesIdxs[std::make_pair(P.first.second, P.first.first)].clear();
}
// Check if any concat_vectors can be simplified.
SmallBitVector UsedSubVector(2 * array_lengthof(Inputs));
SmallBitVector UsedSubVector(2 * std::size(Inputs));
for (int &Idx : Mask) {
if (Idx == UndefMaskElem)
continue;
@ -2445,7 +2445,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
}
if (UsedSubVector.count() > 1) {
SmallVector<SmallVector<std::pair<unsigned, int>, 2>> Pairs;
for (unsigned I = 0; I < array_lengthof(Inputs); ++I) {
for (unsigned I = 0; I < std::size(Inputs); ++I) {
if (UsedSubVector.test(2 * I) == UsedSubVector.test(2 * I + 1))
continue;
if (Pairs.empty() || Pairs.back().size() == 2)
@ -2489,7 +2489,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
// Try to remove extra shuffles (except broadcasts) and shuffles with the
// reused operands.
Changed = false;
for (unsigned I = 0; I < array_lengthof(Inputs); ++I) {
for (unsigned I = 0; I < std::size(Inputs); ++I) {
auto *Shuffle = dyn_cast<ShuffleVectorSDNode>(Inputs[I].getNode());
if (!Shuffle)
continue;
@ -2589,7 +2589,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
}
// Adjust mask in case of reused inputs. Also, need to insert constant
// inputs at first, otherwise it affects the final outcome.
if (UniqueInputs.size() != array_lengthof(Inputs)) {
if (UniqueInputs.size() != std::size(Inputs)) {
auto &&UniqueVec = UniqueInputs.takeVector();
auto &&UniqueConstantVec = UniqueConstantInputs.takeVector();
unsigned ConstNum = UniqueConstantVec.size();
@ -2627,7 +2627,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
// Build a shuffle mask for the output, discovering on the fly which
// input vectors to use as shuffle operands.
unsigned FirstMaskIdx = High * NewElts;
SmallVector<int> Mask(NewElts * array_lengthof(Inputs), UndefMaskElem);
SmallVector<int> Mask(NewElts * std::size(Inputs), UndefMaskElem);
copy(makeArrayRef(OrigMask).slice(FirstMaskIdx, NewElts), Mask.begin());
assert(!Output && "Expected default initialized initial value.");
TryPeekThroughShufflesInputs(Mask);
@ -2647,7 +2647,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
return SecondIteration;
};
processShuffleMasks(
Mask, array_lengthof(Inputs), array_lengthof(Inputs),
Mask, std::size(Inputs), std::size(Inputs),
/*NumOfUsedRegs=*/1,
[&Output, &DAG = DAG, NewVT]() { Output = DAG.getUNDEF(NewVT); },
[&Output, &DAG = DAG, NewVT, &DL, &Inputs,

2
llvm/lib/CodeGen/TargetLoweringBase.cpp
View File

@ -950,7 +950,7 @@ TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
// If this is a simple type, use the ComputeRegisterProp mechanism.
if (VT.isSimple()) {
MVT SVT = VT.getSimpleVT();
assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
MVT NVT = TransformToType[SVT.SimpleTy];
LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);

2
llvm/lib/DWP/DWP.cpp
View File

@ -407,7 +407,7 @@ void writeIndexTable(
const MapVector<uint64_t, UnitIndexEntry> &IndexEntries,
uint32_t DWARFUnitIndex::Entry::SectionContribution::*Field) {
for (const auto &E : IndexEntries)
for (size_t I = 0; I != array_lengthof(E.second.Contributions); ++I)
for (size_t I = 0; I != std::size(E.second.Contributions); ++I)
if (ContributionOffsets[I])
Out.emitIntValue(E.second.Contributions[I].*Field, 4);
}

7
llvm/lib/IR/DebugInfoMetadata.cpp
View File

@ -329,7 +329,7 @@ void GenericDINode::recalculateHash() {
} \
} while (false)
#define DEFINE_GETIMPL_STORE(CLASS, ARGS, OPS) \
return storeImpl(new (array_lengthof(OPS), Storage) \
return storeImpl(new (std::size(OPS), Storage) \
CLASS(Context, Storage, UNWRAP_ARGS(ARGS), OPS), \
Storage, Context.pImpl->CLASS##s)
#define DEFINE_GETIMPL_STORE_NO_OPS(CLASS, ARGS) \
@ -337,8 +337,7 @@ void GenericDINode::recalculateHash() {
CLASS(Context, Storage, UNWRAP_ARGS(ARGS)), \
Storage, Context.pImpl->CLASS##s)
#define DEFINE_GETIMPL_STORE_NO_CONSTRUCTOR_ARGS(CLASS, OPS) \
return storeImpl(new (array_lengthof(OPS), Storage) \
CLASS(Context, Storage, OPS), \
return storeImpl(new (std::size(OPS), Storage) CLASS(Context, Storage, OPS), \
Storage, Context.pImpl->CLASS##s)
#define DEFINE_GETIMPL_STORE_N(CLASS, ARGS, OPS, NUM_OPS) \
return storeImpl(new (NUM_OPS, Storage) \
@ -850,7 +849,7 @@ DICompileUnit *DICompileUnit::getImpl(
Macros,
SysRoot,
SDK};
return storeImpl(new (array_lengthof(Ops), Storage) DICompileUnit(
return storeImpl(new (std::size(Ops), Storage) DICompileUnit(
Context, Storage, SourceLanguage, IsOptimized,
RuntimeVersion, EmissionKind, DWOId, SplitDebugInlining,
DebugInfoForProfiling, NameTableKind, RangesBaseAddress,

2
llvm/lib/MC/MCAsmBackend.cpp
View File

@ -105,7 +105,7 @@ const MCFixupKindInfo &MCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"FK_SecRel_8", 0, 64, 0},
};
assert((size_t)Kind <= array_lengthof(Builtins) && "Unknown fixup kind");
assert((size_t)Kind <= std::size(Builtins) && "Unknown fixup kind");
return Builtins[Kind];
}

2
llvm/lib/MC/MCDwarf.cpp
View File

@ -306,7 +306,7 @@ MCDwarfLineTableHeader::Emit(MCStreamer *MCOS, MCDwarfLineTableParams Params,
0, // length of DW_LNS_set_epilogue_begin
1 // DW_LNS_set_isa
};
assert(array_lengthof(StandardOpcodeLengths) >=
assert(std::size(StandardOpcodeLengths) >=
(Params.DWARF2LineOpcodeBase - 1U));
return Emit(
MCOS, Params,

2
llvm/lib/Object/MachOObjectFile.cpp
View File

@ -2329,7 +2329,7 @@ void MachOObjectFile::getRelocationTypeName(
"ARM64_RELOC_ADDEND"
};
if (RType >= array_lengthof(Table))
if (RType >= std::size(Table))
res = "Unknown";
else
res = Table[RType];

4
llvm/lib/Support/ARMAttributeParser.cpp
View File

@ -214,7 +214,7 @@ Error ARMAttributeParser::ABI_align_needed(AttrType tag) {
uint64_t value = de.getULEB128(cursor);
std::string description;
if (value < array_lengthof(strings))
if (value < std::size(strings))
description = strings[value];
else if (value <= 12)
description = "8-byte alignment, " + utostr(1ULL << value) +
@ -233,7 +233,7 @@ Error ARMAttributeParser::ABI_align_preserved(AttrType tag) {
uint64_t value = de.getULEB128(cursor);
std::string description;
if (value < array_lengthof(strings))
if (value < std::size(strings))
description = std::string(strings[value]);
else if (value <= 12)
description = std::string("8-byte stack alignment, ") +

2
llvm/lib/Support/CrashRecoveryContext.cpp
View File

@ -353,7 +353,7 @@ static void uninstallExceptionOrSignalHandlers() {
static const int Signals[] =
{ SIGABRT, SIGBUS, SIGFPE, SIGILL, SIGSEGV, SIGTRAP };
static const unsigned NumSignals = array_lengthof(Signals);
static const unsigned NumSignals = std::size(Signals);
static struct sigaction PrevActions[NumSignals];
static void CrashRecoverySignalHandler(int Signal) {

2
llvm/lib/Support/NativeFormatting.cpp
View File

@ -149,7 +149,7 @@ void llvm::write_hex(raw_ostream &S, uint64_t N, HexPrintStyle Style,
std::max(static_cast<unsigned>(W), std::max(1u, Nibbles) + PrefixChars);
char NumberBuffer[kMaxWidth];
::memset(NumberBuffer, '0', llvm::array_lengthof(NumberBuffer));
::memset(NumberBuffer, '0', std::size(NumberBuffer));
if (Prefix)
NumberBuffer[1] = 'x';
char *EndPtr = NumberBuffer + NumChars;

10
llvm/lib/Support/Triple.cpp
View File

@ -982,13 +982,13 @@ std::string Triple::normalize(StringRef Str) {
// If they are not there already, permute the components into their canonical
// positions by seeing if they parse as a valid architecture, and if so moving
// the component to the architecture position etc.
for (unsigned Pos = 0; Pos != array_lengthof(Found); ++Pos) {
for (unsigned Pos = 0; Pos != std::size(Found); ++Pos) {
if (Found[Pos])
continue; // Already in the canonical position.
for (unsigned Idx = 0; Idx != Components.size(); ++Idx) {
// Do not reparse any components that already matched.
if (Idx < array_lengthof(Found) && Found[Idx])
if (Idx < std::size(Found) && Found[Idx])
continue;
// Does this component parse as valid for the target position?
@ -1036,7 +1036,7 @@ std::string Triple::normalize(StringRef Str) {
// components to the right.
for (unsigned i = Pos; !CurrentComponent.empty(); ++i) {
// Skip over any fixed components.
while (i < array_lengthof(Found) && Found[i])
while (i < std::size(Found) && Found[i])
++i;
// Place the component at the new position, getting the component
// that was at this position - it will be moved right.
@ -1057,7 +1057,7 @@ std::string Triple::normalize(StringRef Str) {
if (CurrentComponent.empty())
break;
// Advance to the next component, skipping any fixed components.
while (++i < array_lengthof(Found) && Found[i])
while (++i < std::size(Found) && Found[i])
;
}
// The last component was pushed off the end - append it.
@ -1065,7 +1065,7 @@ std::string Triple::normalize(StringRef Str) {
Components.push_back(CurrentComponent);
// Advance Idx to the component's new position.
while (++Idx < array_lengthof(Found) && Found[Idx])
while (++Idx < std::size(Found) && Found[Idx])
;
} while (Idx < Pos); // Add more until the final position is reached.
}

10
llvm/lib/Support/Unix/Signals.inc
View File

@ -239,8 +239,8 @@ static const int InfoSigs[] = {
};
static const size_t NumSigs =
array_lengthof(IntSigs) + array_lengthof(KillSigs) +
array_lengthof(InfoSigs) + 1 /* SIGPIPE */;
std::size(IntSigs) + std::size(KillSigs) +
std::size(InfoSigs) + 1 /* SIGPIPE */;
static std::atomic<unsigned> NumRegisteredSignals = ATOMIC_VAR_INIT(0);
@ -298,7 +298,7 @@ static void RegisterHandlers() { // Not signal-safe.
enum class SignalKind { IsKill, IsInfo };
auto registerHandler = [&](int Signal, SignalKind Kind) {
unsigned Index = NumRegisteredSignals.load();
assert(Index < array_lengthof(RegisteredSignalInfo) &&
assert(Index < std::size(RegisteredSignalInfo) &&
"Out of space for signal handlers!");
struct sigaction NewHandler;
@ -566,13 +566,13 @@ void llvm::sys::PrintStackTrace(raw_ostream &OS, int Depth) {
#if defined(HAVE_BACKTRACE)
// Use backtrace() to output a backtrace on Linux systems with glibc.
if (!depth)
depth = backtrace(StackTrace, static_cast<int>(array_lengthof(StackTrace)));
depth = backtrace(StackTrace, static_cast<int>(std::size(StackTrace)));
#endif
#if defined(HAVE__UNWIND_BACKTRACE)
// Try _Unwind_Backtrace() if backtrace() failed.
if (!depth)
depth = unwindBacktrace(StackTrace,
static_cast<int>(array_lengthof(StackTrace)));
static_cast<int>(std::size(StackTrace)));
#endif
if (!depth)
return;

2
llvm/lib/Support/Windows/Path.inc
View File

@ -687,7 +687,7 @@ static bool isReservedName(StringRef path) {
return true;
// Then compare against the list of ancient reserved names.
for (size_t i = 0; i < array_lengthof(sReservedNames); ++i) {
for (size_t i = 0; i < std::size(sReservedNames); ++i) {
if (path.equals_insensitive(sReservedNames[i]))
return true;
}

2
llvm/lib/Support/Windows/Signals.inc
View File

@ -246,7 +246,7 @@ static bool printStackTraceWithLLVMSymbolizer(llvm::raw_ostream &OS,
if (StackFrame.AddrFrame.Offset == 0)
break;
StackTrace[Depth++] = (void *)(uintptr_t)StackFrame.AddrPC.Offset;
if (Depth >= array_lengthof(StackTrace))
if (Depth >= std::size(StackTrace))
break;
}

14
llvm/lib/Support/X86TargetParser.cpp
View File

@ -54,7 +54,7 @@ public:
}
constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
// GCC <6.2 crashes if this is written in a single statement.
uint32_t NewBits = Bits[I] & RHS.Bits[I];
Bits[I] = NewBits;
@ -63,7 +63,7 @@ public:
}
constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
// GCC <6.2 crashes if this is written in a single statement.
uint32_t NewBits = Bits[I] | RHS.Bits[I];
Bits[I] = NewBits;
@ -74,7 +74,7 @@ public:
// gcc 5.3 miscompiles this if we try to write this using operator&=.
constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
FeatureBitset Result;
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
Result.Bits[I] = Bits[I] & RHS.Bits[I];
return Result;
}
@ -82,20 +82,20 @@ public:
// gcc 5.3 miscompiles this if we try to write this using operator&=.
constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
FeatureBitset Result;
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
Result.Bits[I] = Bits[I] | RHS.Bits[I];
return Result;
}
constexpr FeatureBitset operator~() const {
FeatureBitset Result;
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
Result.Bits[I] = ~Bits[I];
return Result;
}
constexpr bool operator!=(const FeatureBitset &RHS) const {
for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
if (Bits[I] != RHS.Bits[I])
return true;
return false;
@ -692,7 +692,7 @@ unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) {
#include "llvm/Support/X86TargetParser.def"
std::numeric_limits<unsigned>::max() // Need to consume last comma.
};
std::array<unsigned, array_lengthof(Priorities) - 1> HelperList;
std::array<unsigned, std::size(Priorities) - 1> HelperList;
std::iota(HelperList.begin(), HelperList.end(), 0);
assert(std::is_permutation(HelperList.begin(), HelperList.end(),
std::begin(Priorities),

5
llvm/lib/Support/raw_ostream.cpp
View File

@ -480,12 +480,11 @@ static raw_ostream &write_padding(raw_ostream &OS, unsigned NumChars) {
C, C, C, C, C, C, C, C, C, C, C, C, C, C, C, C};
// Usually the indentation is small, handle it with a fastpath.
if (NumChars < array_lengthof(Chars))
if (NumChars < std::size(Chars))
return OS.write(Chars, NumChars);
while (NumChars) {
unsigned NumToWrite = std::min(NumChars,
(unsigned)array_lengthof(Chars)-1);
unsigned NumToWrite = std::min(NumChars, (unsigned)std::size(Chars) - 1);
OS.write(Chars, NumToWrite);
NumChars -= NumToWrite;
}

4
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -6203,7 +6203,7 @@ void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
AArch64::X3, AArch64::X4, AArch64::X5,
AArch64::X6, AArch64::X7 };
unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
unsigned NumGPRArgRegs = std::size(GPRArgRegs);
if (Subtarget->isWindowsArm64EC()) {
// In the ARM64EC ABI, only x0-x3 are used to pass arguments to varargs
// functions.
@ -6256,7 +6256,7 @@ void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
static const MCPhysReg FPRArgRegs[] = {
AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
static const unsigned NumFPRArgRegs = std::size(FPRArgRegs);
unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);

4
llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
View File

@ -347,7 +347,7 @@ const UnmangledFuncInfo UnmangledFuncInfo::Table[] = {
};
const unsigned UnmangledFuncInfo::TableSize =
array_lengthof(UnmangledFuncInfo::Table);
std::size(UnmangledFuncInfo::Table);
static AMDGPULibFunc::Param getRetType(AMDGPULibFunc::EFuncId id,
const AMDGPULibFunc::Param (&Leads)[2]) {
@ -555,7 +555,7 @@ static AMDGPULibFunc::ENamePrefix parseNamePrefix(StringRef& mangledName) {
}
StringMap<int> ManglingRule::buildManglingRulesMap() {
StringMap<int> Map(array_lengthof(manglingRules));
StringMap<int> Map(std::size(manglingRules));
int Id = 0;
for (auto Rule : manglingRules)
Map.insert({Rule.Name, Id++});

2
llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
View File

@ -29,7 +29,7 @@ unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) {
R600::sub12, R600::sub13, R600::sub14, R600::sub15
};
assert(Channel < array_lengthof(SubRegFromChannelTable));
assert(Channel < std::size(SubRegFromChannelTable));
return SubRegFromChannelTable[Channel];
}

11
llvm/lib/Target/ARC/ARCISelLowering.cpp
View File

@ -560,18 +560,17 @@ SDValue ARCTargetLowering::LowerCallArguments(
ARC::R4, ARC::R5, ARC::R6, ARC::R7};
auto *AFI = MF.getInfo<ARCFunctionInfo>();
unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
if (FirstVAReg < array_lengthof(ArgRegs)) {
if (FirstVAReg < std::size(ArgRegs)) {
int Offset = 0;
// Save remaining registers, storing higher register numbers at a higher
// address
// There are (array_lengthof(ArgRegs) - FirstVAReg) registers which
// There are (std::size(ArgRegs) - FirstVAReg) registers which
// need to be saved.
int VarFI =
MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4,
CCInfo.getNextStackOffset(), true);
int VarFI = MFI.CreateFixedObject((std::size(ArgRegs) - FirstVAReg) * 4,
CCInfo.getNextStackOffset(), true);
AFI->setVarArgsFrameIndex(VarFI);
SDValue FIN = DAG.getFrameIndex(VarFI, MVT::i32);
for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) {
for (unsigned i = FirstVAReg; i < std::size(ArgRegs); i++) {
// Move argument from phys reg -> virt reg
unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass);
RegInfo.addLiveIn(ArgRegs[i], VReg);

2
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -115,7 +115,7 @@ static const ARM_MLxEntry ARM_MLxTable[] = {
ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
: ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
Subtarget(STI) {
for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
for (unsigned i = 0, e = std::size(ARM_MLxTable); i != e; ++i) {
if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
llvm_unreachable("Duplicated entries?");
MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);

2
llvm/lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -2792,7 +2792,7 @@ bool ARMFrameLowering::assignCalleeSavedSpillSlots(
const TargetFrameLowering::SpillSlot *
ARMFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
static const SpillSlot FixedSpillOffsets[] = {{ARM::FPCXTNS, -4}};
NumEntries = array_lengthof(FixedSpillOffsets);
NumEntries = std::size(FixedSpillOffsets);
return FixedSpillOffsets;
}

2
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -4486,7 +4486,7 @@ SDValue ARMTargetLowering::LowerFormalArguments(
int lastInsIndex = -1;
if (isVarArg && MFI.hasVAStart()) {
unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
if (RegIdx != array_lengthof(GPRArgRegs))
if (RegIdx != std::size(GPRArgRegs))
ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
}

2
llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
View File

@ -245,7 +245,7 @@ INITIALIZE_PASS(Thumb2SizeReduce, DEBUG_TYPE, THUMB2_SIZE_REDUCE_NAME, false,
Thumb2SizeReduce::Thumb2SizeReduce(std::function<bool(const Function &)> Ftor)
: MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
OptimizeSize = MinimizeSize = false;
for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
for (unsigned i = 0, e = std::size(ReduceTable); i != e; ++i) {
unsigned FromOpc = ReduceTable[i].WideOpc;
if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
llvm_unreachable("Duplicated entries?");

20
llvm/lib/Target/AVR/AVRISelLowering.cpp
View File

@ -1108,9 +1108,9 @@ static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
AVR::R24R23, AVR::R23R22,
AVR::R22R21, AVR::R21R20};
static_assert(array_lengthof(RegList8AVR) == array_lengthof(RegList16AVR),
static_assert(std::size(RegList8AVR) == std::size(RegList16AVR),
"8-bit and 16-bit register arrays must be of equal length");
static_assert(array_lengthof(RegList8Tiny) == array_lengthof(RegList16Tiny),
static_assert(std::size(RegList8Tiny) == std::size(RegList16Tiny),
"8-bit and 16-bit register arrays must be of equal length");
/// Analyze incoming and outgoing function arguments. We need custom C++ code
@ -1127,11 +1127,11 @@ static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI,
ArrayRef<MCPhysReg> RegList8;
ArrayRef<MCPhysReg> RegList16;
if (Tiny) {
RegList8 = makeArrayRef(RegList8Tiny, array_lengthof(RegList8Tiny));
RegList16 = makeArrayRef(RegList16Tiny, array_lengthof(RegList16Tiny));
RegList8 = makeArrayRef(RegList8Tiny, std::size(RegList8Tiny));
RegList16 = makeArrayRef(RegList16Tiny, std::size(RegList16Tiny));
} else {
RegList8 = makeArrayRef(RegList8AVR, array_lengthof(RegList8AVR));
RegList16 = makeArrayRef(RegList16AVR, array_lengthof(RegList16AVR));
RegList8 = makeArrayRef(RegList8AVR, std::size(RegList8AVR));
RegList16 = makeArrayRef(RegList16AVR, std::size(RegList16AVR));
}
unsigned NumArgs = Args.size();
@ -1223,11 +1223,11 @@ static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
ArrayRef<MCPhysReg> RegList8;
ArrayRef<MCPhysReg> RegList16;
if (Tiny) {
RegList8 = makeArrayRef(RegList8Tiny, array_lengthof(RegList8Tiny));
RegList16 = makeArrayRef(RegList16Tiny, array_lengthof(RegList16Tiny));
RegList8 = makeArrayRef(RegList8Tiny, std::size(RegList8Tiny));
RegList16 = makeArrayRef(RegList16Tiny, std::size(RegList16Tiny));
} else {
RegList8 = makeArrayRef(RegList8AVR, array_lengthof(RegList8AVR));
RegList16 = makeArrayRef(RegList16AVR, array_lengthof(RegList16AVR));
RegList8 = makeArrayRef(RegList8AVR, std::size(RegList8AVR));
RegList16 = makeArrayRef(RegList16AVR, std::size(RegList16AVR));
}
// GCC-ABI says that the size is rounded up to the next even number,

8
llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
View File

@ -680,7 +680,7 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
/* 28 */ 0, 0, UTIMERLO, UTIMERHI
};
if (RegNo >= array_lengthof(CtrlRegDecoderTable))
if (RegNo >= std::size(CtrlRegDecoderTable))
return MCDisassembler::Fail;
static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
@ -708,7 +708,7 @@ DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
/* 28 */ 0, 0, UTIMER, 0
};
if (RegNo >= array_lengthof(CtrlReg64DecoderTable))
if (RegNo >= std::size(CtrlReg64DecoderTable))
return MCDisassembler::Fail;
static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
@ -862,7 +862,7 @@ DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
/* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
};
if (RegNo >= array_lengthof(GuestRegDecoderTable))
if (RegNo >= std::size(GuestRegDecoderTable))
return MCDisassembler::Fail;
if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
return MCDisassembler::Fail;
@ -889,7 +889,7 @@ DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
/* 28 */ G29_28, 0, G31_30, 0
};
if (RegNo >= array_lengthof(GuestReg64DecoderTable))
if (RegNo >= std::size(GuestReg64DecoderTable))
return MCDisassembler::Fail;
if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
return MCDisassembler::Fail;

2
llvm/lib/Target/Hexagon/HexagonFrameLowering.h
View File

@ -97,7 +97,7 @@ public:
{ Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
{ Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
};
NumEntries = array_lengthof(Offsets);
NumEntries = std::size(Offsets);
return Offsets;
}

4
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
View File

@ -998,8 +998,8 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI,
static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 };
static const unsigned Regs1[] = { LC1, SA1 };
auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, array_lengthof(Regs01))
: makeArrayRef(Regs1, array_lengthof(Regs1));
auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, std::size(Regs01))
: makeArrayRef(Regs1, std::size(Regs1));
for (unsigned R : CheckRegs)
if (MI->modifiesRegister(R, TRI))
return true;

2
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -304,7 +304,7 @@ bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) {
SDNode *S = StoreInstrForLoadIntrinsic(L, C);
SDValue F[] = { SDValue(N,0), SDValue(N,1), SDValue(C,0), SDValue(C,1) };
SDValue T[] = { SDValue(L,0), SDValue(S,0), SDValue(L,1), SDValue(S,0) };
ReplaceUses(F, T, array_lengthof(T));
ReplaceUses(F, T, std::size(T));
// This transformation will leave the intrinsic dead. If it remains in
// the DAG, the selection code will see it again, but without the load,
// and it will generate a store that is normally required for it.

2
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -144,7 +144,7 @@ static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
Hexagon::R0, Hexagon::R1, Hexagon::R2,
Hexagon::R3, Hexagon::R4, Hexagon::R5
};
const unsigned NumArgRegs = array_lengthof(ArgRegs);
const unsigned NumArgRegs = std::size(ArgRegs);
unsigned RegNum = State.getFirstUnallocated(ArgRegs);
// RegNum is an index into ArgRegs: skip a register if RegNum is odd.

2
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
View File

@ -641,7 +641,7 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
Hexagon::fixup_Hexagon_GPREL16_0, Hexagon::fixup_Hexagon_GPREL16_1,
Hexagon::fixup_Hexagon_GPREL16_2, Hexagon::fixup_Hexagon_GPREL16_3
};
assert(Shift < array_lengthof(GPRelFixups));
assert(Shift < std::size(GPRelFixups));
auto UsesGP = [] (const MCInstrDesc &D) {
for (const MCPhysReg *U = D.getImplicitUses(); U && *U; ++U)
if (*U == Hexagon::GP)

4
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
View File

@ -1105,7 +1105,7 @@ static bool CC_LoongArch(const DataLayout &DL, LoongArchABI::ABI ABI,
}
// FPR32 and FPR64 alias each other.
if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s))
if (State.getFirstUnallocated(ArgFPR32s) == std::size(ArgFPR32s))
UseGPRForFloat = true;
if (UseGPRForFloat && ValVT == MVT::f32) {
@ -1130,7 +1130,7 @@ static bool CC_LoongArch(const DataLayout &DL, LoongArchABI::ABI ABI,
DL.getTypeAllocSize(OrigTy) == TwoGRLenInBytes) {
unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
// Skip 'odd' register if necessary.
if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1)
State.AllocateReg(ArgGPRs);
}

2
llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
View File

@ -59,7 +59,7 @@ LoongArchAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
// TODO: Add more fixup kinds.
};
static_assert((array_lengthof(Infos)) == LoongArch::NumTargetFixupKinds,
static_assert((std::size(Infos)) == LoongArch::NumTargetFixupKinds,
"Not all fixup kinds added to Infos array");
// Fixup kinds from .reloc directive are like R_LARCH_NONE. They

4
llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp
View File

@ -81,9 +81,9 @@ public:
{"fixup_8", 0, 8, 0},
{"fixup_sym_diff", 0, 32, 0},
};
static_assert((array_lengthof(Infos)) == MSP430::NumTargetFixupKinds,
static_assert((std::size(Infos)) == MSP430::NumTargetFixupKinds,
"Not all fixup kinds added to Infos array");
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);

4
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -458,12 +458,12 @@ static void AnalyzeArguments(CCState &State,
static const MCPhysReg CRegList[] = {
MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
};
static const unsigned CNbRegs = array_lengthof(CRegList);
static const unsigned CNbRegs = std::size(CRegList);
static const MCPhysReg BuiltinRegList[] = {
MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
};
static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
static const unsigned BuiltinNbRegs = std::size(BuiltinRegList);
ArrayRef<MCPhysReg> RegList;
unsigned NbRegs;

4
llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
View File

@ -429,7 +429,7 @@ getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_JALR", 0, 32, 0 },
{ "fixup_MICROMIPS_JALR", 0, 32, 0 }
};
static_assert(array_lengthof(LittleEndianInfos) == Mips::NumTargetFixupKinds,
static_assert(std::size(LittleEndianInfos) == Mips::NumTargetFixupKinds,
"Not all MIPS little endian fixup kinds added!");
const static MCFixupKindInfo BigEndianInfos[] = {
@ -508,7 +508,7 @@ getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_JALR", 0, 32, 0 },
{ "fixup_MICROMIPS_JALR", 0, 32, 0 }
};
static_assert(array_lengthof(BigEndianInfos) == Mips::NumTargetFixupKinds,
static_assert(std::size(BigEndianInfos) == Mips::NumTargetFixupKinds,
"Not all MIPS big endian fixup kinds added!");
if (Kind >= FirstLiteralRelocationKind)

2
llvm/lib/Target/Mips/Mips16ISelLowering.cpp
View File

@ -246,7 +246,7 @@ bool Mips16TargetLowering::isEligibleForTailCallOptimization(
}
void Mips16TargetLowering::setMips16HardFloatLibCalls() {
for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) {
for (unsigned I = 0; I != std::size(HardFloatLibCalls); ++I) {
assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
"Array not sorted!");
if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)

6
llvm/lib/Target/PowerPC/PPCCallingConv.cpp
View File

@ -37,7 +37,7 @@ static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
const unsigned NumArgRegs = array_lengthof(ArgRegs);
const unsigned NumArgRegs = std::size(ArgRegs);
unsigned RegNum = State.getFirstUnallocated(ArgRegs);
@ -62,7 +62,7 @@ static bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
const unsigned NumArgRegs = array_lengthof(ArgRegs);
const unsigned NumArgRegs = std::size(ArgRegs);
unsigned RegNum = State.getFirstUnallocated(ArgRegs);
int RegsLeft = NumArgRegs - RegNum;
@ -88,7 +88,7 @@ static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
PPC::F8
};
const unsigned NumArgRegs = array_lengthof(ArgRegs);
const unsigned NumArgRegs = std::size(ArgRegs);
unsigned RegNum = State.getFirstUnallocated(ArgRegs);

8
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
View File

@ -229,23 +229,23 @@ const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
CALLEE_SAVED_FPRS, CALLEE_SAVED_GPRS64, CALLEE_SAVED_VRS};
if (Subtarget.is64BitELFABI()) {
NumEntries = array_lengthof(ELFOffsets64);
NumEntries = std::size(ELFOffsets64);
return ELFOffsets64;
}
if (Subtarget.is32BitELFABI()) {
NumEntries = array_lengthof(ELFOffsets32);
NumEntries = std::size(ELFOffsets32);
return ELFOffsets32;
}
assert(Subtarget.isAIXABI() && "Unexpected ABI.");
if (Subtarget.isPPC64()) {
NumEntries = array_lengthof(AIXOffsets64);
NumEntries = std::size(AIXOffsets64);
return AIXOffsets64;
}
NumEntries = array_lengthof(AIXOffsets32);
NumEntries = std::size(AIXOffsets32);
return AIXOffsets32;
}

20
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -4179,13 +4179,13 @@ SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
PPC::R3, PPC::R4, PPC::R5, PPC::R6,
PPC::R7, PPC::R8, PPC::R9, PPC::R10,
};
const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
const unsigned NumGPArgRegs = std::size(GPArgRegs);
static const MCPhysReg FPArgRegs[] = {
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
PPC::F8
};
unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
unsigned NumFPArgRegs = std::size(FPArgRegs);
if (useSoftFloat() || hasSPE())
NumFPArgRegs = 0;
@ -4297,9 +4297,9 @@ SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
};
const unsigned Num_GPR_Regs = array_lengthof(GPR);
const unsigned Num_GPR_Regs = std::size(GPR);
const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
const unsigned Num_VR_Regs = array_lengthof(VR);
const unsigned Num_VR_Regs = std::size(VR);
// Do a first pass over the arguments to determine whether the ABI
// guarantees that our caller has allocated the parameter save area
@ -4757,9 +4757,9 @@ needStackSlotPassParameters(const PPCSubtarget &Subtarget,
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
};
const unsigned NumGPRs = array_lengthof(GPR);
const unsigned NumGPRs = std::size(GPR);
const unsigned NumFPRs = 13;
const unsigned NumVRs = array_lengthof(VR);
const unsigned NumVRs = std::size(VR);
const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
unsigned NumBytes = LinkageSize;
@ -6010,9 +6010,9 @@ SDValue PPCTargetLowering::LowerCall_64SVR4(
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
};
const unsigned NumGPRs = array_lengthof(GPR);
const unsigned NumGPRs = std::size(GPR);
const unsigned NumFPRs = useSoftFloat() ? 0 : 13;
const unsigned NumVRs = array_lengthof(VR);
const unsigned NumVRs = std::size(VR);
// On ELFv2, we can avoid allocating the parameter area if all the arguments
// can be passed to the callee in registers.
@ -7183,7 +7183,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
static const MCPhysReg GPR_64[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6,
PPC::X7, PPC::X8, PPC::X9, PPC::X10};
const unsigned NumGPArgRegs = array_lengthof(IsPPC64 ? GPR_64 : GPR_32);
const unsigned NumGPArgRegs = std::size(IsPPC64 ? GPR_64 : GPR_32);
// The fixed integer arguments of a variadic function are stored to the
// VarArgsFrameIndex on the stack so that they may be loaded by
@ -9396,7 +9396,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
-8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
};
for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
for (unsigned idx = 0; idx < std::size(SplatCsts); ++idx) {
// Indirect through the SplatCsts array so that we favor 'vsplti -1' for
// cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
int i = SplatCsts[idx];

4
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -311,7 +311,7 @@ static const uint16_t FMAOpIdxInfo[][6] = {
// Check if an opcode is a FMA instruction. If it is, return the index in array
// FMAOpIdxInfo. Otherwise, return -1.
int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const {
for (unsigned I = 0; I < array_lengthof(FMAOpIdxInfo); I++)
for (unsigned I = 0; I < std::size(FMAOpIdxInfo); I++)
if (FMAOpIdxInfo[I][InfoArrayIdxFMAInst] == Opcode)
return I;
return -1;
@ -2332,7 +2332,7 @@ bool PPCInstrInfo::ClobbersPredicate(MachineInstr &MI,
bool Found = false;
for (const MachineOperand &MO : MI.operands()) {
for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
for (unsigned c = 0; c < std::size(RCs) && !Found; ++c) {
const TargetRegisterClass *RC = RCs[c];
if (MO.isReg()) {
if (MO.isDef() && RC->contains(MO.getReg())) {

2
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
View File

@ -94,7 +94,7 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{"fixup_riscv_set_6b", 2, 6, 0},
{"fixup_riscv_sub_6b", 2, 6, 0},
};
static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
"Not all fixup kinds added to Infos array");
// Fixup kinds from .reloc directive are like R_RISCV_NONE. They

4
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -10818,7 +10818,7 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
}
// FPR16, FPR32, and FPR64 alias each other.
if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s)) {
if (State.getFirstUnallocated(ArgFPR32s) == std::size(ArgFPR32s)) {
UseGPRForF16_F32 = true;
UseGPRForF64 = true;
}
@ -10847,7 +10847,7 @@ static bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
DL.getTypeAllocSize(OrigTy) == TwoXLenInBytes) {
unsigned RegIdx = State.getFirstUnallocated(ArgGPRs);
// Skip 'odd' register if necessary.
if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1)
State.AllocateReg(ArgGPRs);
}

2
llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
View File

@ -226,7 +226,7 @@ static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
if (RegNo >= array_lengthof(PRRegDecoderTable))
if (RegNo >= std::size(PRRegDecoderTable))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo]));
return MCDisassembler::Success;

2
llvm/lib/Target/VE/VEFrameLowering.h
View File

@ -62,7 +62,7 @@ public:
{VE::SX25, 104}, {VE::SX26, 112}, {VE::SX27, 120}, {VE::SX28, 128},
{VE::SX29, 136}, {VE::SX30, 144}, {VE::SX31, 152}, {VE::SX32, 160},
{VE::SX33, 168}};
NumEntries = array_lengthof(Offsets);
NumEntries = std::size(Offsets);
return Offsets;
}

4
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -4264,7 +4264,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
}
}
for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
for (unsigned I = 0, E = std::size(Match); I != E; ++I) {
Tmp.back() = Suffixes[I];
if (MemOp && HasVectorReg)
MemOp->Mem.Size = MemSize[I];
@ -4310,7 +4310,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
if (NumSuccessfulMatches > 1) {
char MatchChars[4];
unsigned NumMatches = 0;
for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
for (unsigned I = 0, E = std::size(Match); I != E; ++I)
if (Match[I] == Match_Success)
MatchChars[NumMatches++] = Suffixes[I];

4
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -12550,7 +12550,7 @@ static int canLowerByDroppingElements(ArrayRef<int> Mask, bool MatchEven,
continue;
bool IsAnyViable = false;
for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
for (unsigned j = 0; j != std::size(ViableForN); ++j)
if (ViableForN[j]) {
uint64_t N = j + 1;
@ -12565,7 +12565,7 @@ static int canLowerByDroppingElements(ArrayRef<int> Mask, bool MatchEven,
break;
}
for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
for (unsigned j = 0; j != std::size(ViableForN); ++j)
if (ViableForN[j])
return j + 1;

4
llvm/lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -1345,11 +1345,11 @@ SDValue XCoreTargetLowering::LowerCCCArguments(
};
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs);
if (FirstVAReg < array_lengthof(ArgRegs)) {
if (FirstVAReg < std::size(ArgRegs)) {
int offset = 0;
// Save remaining registers, storing higher register numbers at a higher
// address
for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
for (int i = std::size(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
// Create a stack slot
int FI = MFI.CreateFixedObject(4, offset, true);
if (i == (int)FirstVAReg) {

3
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
View File

@ -576,8 +576,7 @@ Value *FAddCombine::simplifyFAdd(AddendVect& Addends, unsigned InstrQuota) {
}
}
assert((NextTmpIdx <= array_lengthof(TmpResult) + 1) &&
"out-of-bound access");
assert((NextTmpIdx <= std::size(TmpResult) + 1) && "out-of-bound access");
Value *Result;
if (!SimpVect.empty())

2
llvm/lib/Transforms/Utils/MetaRenamer.cpp
View File

@ -87,7 +87,7 @@ struct Renamer {
Renamer(unsigned int seed) { prng.srand(seed); }
const char *newName() {
return metaNames[prng.rand() % array_lengthof(metaNames)];
return metaNames[prng.rand() % std::size(metaNames)];
}
PRNG prng;

2
llvm/tools/llvm-objdump/COFFDump.cpp
View File

@ -173,7 +173,7 @@ void COFFDumper::printPEHeader(const PEHeader &Hdr) const {
"Reserved",
};
outs() << "\nThe Data Directory\n";
for (uint32_t I = 0; I != array_lengthof(DirName); ++I) {
for (uint32_t I = 0; I != std::size(DirName); ++I) {
uint32_t Addr = 0, Size = 0;
if (const data_directory *Data = Obj.getDataDirectory(I)) {
Addr = Data->RelativeVirtualAddress;

4
llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
View File

@ -906,8 +906,8 @@ void Decoder::decodeOpcodes(ArrayRef<uint8_t> Opcodes, unsigned Offset,
bool Terminated = false;
for (unsigned OI = Offset, OE = Opcodes.size(); !Terminated && OI < OE; ) {
for (unsigned DI = 0;; ++DI) {
if ((isAArch64 && (DI >= array_lengthof(Ring64))) ||
(!isAArch64 && (DI >= array_lengthof(Ring)))) {
if ((isAArch64 && (DI >= std::size(Ring64))) ||
(!isAArch64 && (DI >= std::size(Ring)))) {
SW.startLine() << format("0x%02x ; Bad opcode!\n",
Opcodes.data()[OI]);
++OI;

2
llvm/tools/llvm-readobj/ELFDumper.cpp
View File

@ -5064,7 +5064,7 @@ template <typename ELFT> static GNUAbiTag getGNUAbiTag(ArrayRef<uint8_t> Desc) {
"Linux", "Hurd", "Solaris", "FreeBSD", "NetBSD", "Syllable", "NaCl",
};
StringRef OSName = "Unknown";
if (Words[0] < array_lengthof(OSNames))
if (Words[0] < std::size(OSNames))
OSName = OSNames[Words[0]];
uint32_t Major = Words[1], Minor = Words[2], Patch = Words[3];
std::string str;

20
llvm/unittests/ADT/APFloatTest.cpp
View File

@ -937,13 +937,13 @@ TEST(APFloatTest, fromStringSpecials) {
};
// Convert payload integer to decimal string representation.
std::string NaNPayloadDecStrings[array_lengthof(NaNPayloads)];
for (size_t I = 0; I < array_lengthof(NaNPayloads); ++I)
std::string NaNPayloadDecStrings[std::size(NaNPayloads)];
for (size_t I = 0; I < std::size(NaNPayloads); ++I)
NaNPayloadDecStrings[I] = utostr(NaNPayloads[I]);
// Convert payload integer to hexadecimal string representation.
std::string NaNPayloadHexStrings[array_lengthof(NaNPayloads)];
for (size_t I = 0; I < array_lengthof(NaNPayloads); ++I)
std::string NaNPayloadHexStrings[std::size(NaNPayloads)];
for (size_t I = 0; I < std::size(NaNPayloads); ++I)
NaNPayloadHexStrings[I] = "0x" + utohexstr(NaNPayloads[I]);
// Fix payloads to expected result.
@ -967,7 +967,7 @@ TEST(APFloatTest, fromStringSpecials) {
for (char TypeChar : NaNTypes) {
bool Signaling = (TypeChar == 's' || TypeChar == 'S');
for (size_t J = 0; J < array_lengthof(NaNPayloads); ++J) {
for (size_t J = 0; J < std::size(NaNPayloads); ++J) {
uint64_t Payload = (Signaling && !NaNPayloads[J]) ? SNaNDefaultPayload
: NaNPayloads[J];
std::string &PayloadDec = NaNPayloadDecStrings[J];
@ -2262,7 +2262,7 @@ TEST(APFloatTest, add) {
{ MSmallestNormalized, MSmallestNormalized, "-0x1p-125", APFloat::opOK, APFloat::fcNormal }
};
for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) {
for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) {
APFloat x(SpecialCaseTests[i].x);
APFloat y(SpecialCaseTests[i].y);
APFloat::opStatus status = x.add(y, APFloat::rmNearestTiesToEven);
@ -2502,7 +2502,7 @@ TEST(APFloatTest, subtract) {
{ MSmallestNormalized, MSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero }
};
for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) {
for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) {
APFloat x(SpecialCaseTests[i].x);
APFloat y(SpecialCaseTests[i].y);
APFloat::opStatus status = x.subtract(y, APFloat::rmNearestTiesToEven);
@ -2806,7 +2806,7 @@ TEST(APFloatTest, multiply) {
APFloat::rmNearestTiesToAway},
};
for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) {
for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) {
APFloat x(SpecialCaseTests[i].x);
APFloat y(SpecialCaseTests[i].y);
APFloat::opStatus status = x.multiply(y, SpecialCaseTests[i].roundingMode);
@ -3088,7 +3088,7 @@ TEST(APFloatTest, divide) {
APFloat::rmNearestTiesToAway},
};
for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) {
for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) {
APFloat x(SpecialCaseTests[i].x);
APFloat y(SpecialCaseTests[i].y);
APFloat::opStatus status = x.divide(y, SpecialCaseTests[i].roundingMode);
@ -4048,7 +4048,7 @@ TEST(APFloatTest, remainder) {
{ MVal6, MVal6, "-0x0p+0", APFloat::opOK, APFloat::fcZero },
};
for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) {
for (size_t i = 0; i < std::size(SpecialCaseTests); ++i) {
APFloat x(SpecialCaseTests[i].x);
APFloat y(SpecialCaseTests[i].y);
APFloat::opStatus status = x.remainder(y);

12
llvm/unittests/ADT/StringRefTest.cpp
View File

@ -664,7 +664,7 @@ TEST(StringRefTest, getAsInteger) {
uint32_t U32;
uint64_t U64;
for (size_t i = 0; i < array_lengthof(Unsigned); ++i) {
for (size_t i = 0; i < std::size(Unsigned); ++i) {
bool U8Success = StringRef(Unsigned[i].Str).getAsInteger(0, U8);
if (static_cast<uint8_t>(Unsigned[i].Expected) == Unsigned[i].Expected) {
ASSERT_FALSE(U8Success);
@ -696,7 +696,7 @@ TEST(StringRefTest, getAsInteger) {
int32_t S32;
int64_t S64;
for (size_t i = 0; i < array_lengthof(Signed); ++i) {
for (size_t i = 0; i < std::size(Signed); ++i) {
bool S8Success = StringRef(Signed[i].Str).getAsInteger(0, S8);
if (static_cast<int8_t>(Signed[i].Expected) == Signed[i].Expected) {
ASSERT_FALSE(S8Success);
@ -742,7 +742,7 @@ static const char* BadStrings[] = {
TEST(StringRefTest, getAsUnsignedIntegerBadStrings) {
unsigned long long U64;
for (size_t i = 0; i < array_lengthof(BadStrings); ++i) {
for (size_t i = 0; i < std::size(BadStrings); ++i) {
bool IsBadNumber = StringRef(BadStrings[i]).getAsInteger(0, U64);
ASSERT_TRUE(IsBadNumber);
}
@ -825,7 +825,7 @@ TEST(StringRefTest, consumeIntegerUnsigned) {
uint32_t U32;
uint64_t U64;
for (size_t i = 0; i < array_lengthof(ConsumeUnsigned); ++i) {
for (size_t i = 0; i < std::size(ConsumeUnsigned); ++i) {
StringRef Str = ConsumeUnsigned[i].Str;
bool U8Success = Str.consumeInteger(0, U8);
if (static_cast<uint8_t>(ConsumeUnsigned[i].Expected) ==
@ -873,7 +873,7 @@ TEST(StringRefTest, consumeIntegerSigned) {
int32_t S32;
int64_t S64;
for (size_t i = 0; i < array_lengthof(ConsumeSigned); ++i) {
for (size_t i = 0; i < std::size(ConsumeSigned); ++i) {
StringRef Str = ConsumeSigned[i].Str;
bool S8Success = Str.consumeInteger(0, S8);
if (static_cast<int8_t>(ConsumeSigned[i].Expected) ==
@ -950,7 +950,7 @@ static const char join_result3[] = "a::b::c";
TEST(StringRefTest, joinStrings) {
std::vector<StringRef> v1;
std::vector<std::string> v2;
for (size_t i = 0; i < array_lengthof(join_input); ++i) {
for (size_t i = 0; i < std::size(join_input); ++i) {
v1.push_back(join_input[i]);
v2.push_back(join_input[i]);
}

2
llvm/unittests/ADT/TinyPtrVectorTest.cpp
View File

@ -45,7 +45,7 @@ protected:
std::vector<PtrT> TestPtrs;
TinyPtrVectorTest() {
for (size_t i = 0, e = array_lengthof(TestValues); i != e; ++i)
for (size_t i = 0, e = std::size(TestValues); i != e; ++i)
TestPtrs.push_back(PtrT(&TestValues[i]));
std::shuffle(TestPtrs.begin(), TestPtrs.end(), std::mt19937{});

4
llvm/unittests/ProfileData/CoverageMappingTest.cpp
View File

@ -292,7 +292,7 @@ TEST_P(CoverageMappingTest, basic_write_read) {
TEST_P(CoverageMappingTest, correct_deserialize_for_more_than_two_files) {
const char *FileNames[] = {"bar", "baz", "foo"};
static const unsigned N = array_lengthof(FileNames);
static const unsigned N = std::size(FileNames);
startFunction("func", 0x1234);
for (unsigned I = 0; I < N; ++I)
@ -321,7 +321,7 @@ TEST_P(CoverageMappingTest, load_coverage_for_more_than_two_files) {
ProfileWriter.addRecord({"func", 0x1234, {0}}, Err);
const char *FileNames[] = {"bar", "baz", "foo"};
static const unsigned N = array_lengthof(FileNames);
static const unsigned N = std::size(FileNames);
startFunction("func", 0x1234);
for (unsigned I = 0; I < N; ++I)

2
llvm/unittests/Support/BinaryStreamTest.cpp
View File

@ -103,7 +103,7 @@ private:
};
constexpr endianness Endians[] = {big, little, native};
constexpr uint32_t NumEndians = llvm::array_lengthof(Endians);
constexpr uint32_t NumEndians = std::size(Endians);
constexpr uint32_t NumStreams = 2 * NumEndians;
class BinaryStreamTest : public testing::Test {

2
llvm/unittests/Support/CSKYTargetParserTest.cpp
View File

@ -1135,7 +1135,7 @@ TEST(TargetParserTest, CSKYArchExtFeature) {
{"10e60", "no10e60", "+10e60", "-10e60"},
};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
for (unsigned i = 0; i < std::size(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]), CSKY::getArchExtFeature(ArchExt[i][0]));
EXPECT_EQ(StringRef(ArchExt[i][3]), CSKY::getArchExtFeature(ArchExt[i][1]));
}

14
llvm/unittests/Support/CommandLineTest.cpp
View File

@ -375,7 +375,7 @@ TEST(CommandLineTest, AliasesWithArguments) {
{ "-tool", "-alias", "x" }
};
for (size_t i = 0, e = array_lengthof(Inputs); i < e; ++i) {
for (size_t i = 0, e = std::size(Inputs); i < e; ++i) {
StackOption<std::string> Actual("actual");
StackOption<bool> Extra("extra");
StackOption<std::string> Input(cl::Positional);
@ -404,8 +404,8 @@ void testAliasRequired(int argc, const char *const *argv) {
TEST(CommandLineTest, AliasRequired) {
const char *opts1[] = { "-tool", "-option=x" };
const char *opts2[] = { "-tool", "-o", "x" };
testAliasRequired(array_lengthof(opts1), opts1);
testAliasRequired(array_lengthof(opts2), opts2);
testAliasRequired(std::size(opts1), opts1);
testAliasRequired(std::size(opts2), opts2);
}
TEST(CommandLineTest, HideUnrelatedOptions) {
@ -455,8 +455,8 @@ TEST(CommandLineTest, HideUnrelatedOptionsMulti) {
TEST(CommandLineTest, SetMultiValues) {
StackOption<int> Option("option");
const char *args[] = {"prog", "-option=1", "-option=2"};
EXPECT_TRUE(cl::ParseCommandLineOptions(array_lengthof(args), args,
StringRef(), &llvm::nulls()));
EXPECT_TRUE(cl::ParseCommandLineOptions(std::size(args), args, StringRef(),
&llvm::nulls()));
EXPECT_EQ(Option, 2);
}
@ -1032,8 +1032,8 @@ TEST(CommandLineTest, ResponseFileEOLs) {
/*CurrentDir=*/StringRef(TestRoot), FS));
const char *Expected[] = {"clang", "-Xclang", "-Wno-whatever", nullptr,
"input.cpp"};
ASSERT_EQ(array_lengthof(Expected), Argv.size());
for (size_t I = 0, E = array_lengthof(Expected); I < E; ++I) {
ASSERT_EQ(std::size(Expected), Argv.size());
for (size_t I = 0, E = std::size(Expected); I < E; ++I) {
if (Expected[I] == nullptr) {
ASSERT_EQ(Argv[I], nullptr);
} else {

3
llvm/unittests/Support/FormatVariadicTest.cpp
View File

@ -528,8 +528,7 @@ TEST(FormatVariadicTest, BigTest) {
std::string S;
llvm::raw_string_ostream Stream(S);
Stream << formatv(Intro, std::tuple_size<Tuple>::value,
llvm::array_lengthof(Ts))
Stream << formatv(Intro, std::tuple_size<Tuple>::value, std::size(Ts))
<< "\n";
Stream << formatv(Header, "Char", "HexInt", "Str", "Ref", "std::str",
"double", "float", "pointer", "comma", "exp", "bigint",

12
llvm/unittests/Support/TargetParserTest.cpp
View File

@ -736,7 +736,7 @@ TEST(TargetParserTest, ARMArchExtFeature) {
{"mve", "nomve", "+mve", "-mve"},
{"mve.fp", "nomve.fp", "+mve.fp", "-mve.fp"}};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
for (unsigned i = 0; i < std::size(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]), ARM::getArchExtFeature(ArchExt[i][0]));
EXPECT_EQ(StringRef(ArchExt[i][3]), ARM::getArchExtFeature(ArchExt[i][1]));
}
@ -767,7 +767,7 @@ TEST(TargetParserTest, ARMArchExtDependencies) {
TEST(TargetParserTest, ARMparseHWDiv) {
const char *hwdiv[] = {"thumb", "arm", "arm,thumb", "thumb,arm"};
for (unsigned i = 0; i < array_lengthof(hwdiv); i++)
for (unsigned i = 0; i < std::size(hwdiv); i++)
EXPECT_NE(ARM::AEK_INVALID, ARM::parseHWDiv((StringRef)hwdiv[i]));
}
@ -785,7 +785,7 @@ TEST(TargetParserTest, ARMparseArchEndianAndISA) {
"v8.7a", "v8.8-a", "v8.8a", "v8-r", "v8m.base", "v8m.main",
"v8.1m.main"};
for (unsigned i = 0; i < array_lengthof(Arch); i++) {
for (unsigned i = 0; i < std::size(Arch); i++) {
std::string arm_1 = "armeb" + (std::string)(Arch[i]);
std::string arm_2 = "arm" + (std::string)(Arch[i]) + "eb";
std::string arm_3 = "arm" + (std::string)(Arch[i]);
@ -824,7 +824,7 @@ TEST(TargetParserTest, ARMparseArchEndianAndISA) {
}
TEST(TargetParserTest, ARMparseArchProfile) {
for (unsigned i = 0; i < array_lengthof(ARMArch); i++) {
for (unsigned i = 0; i < std::size(ARMArch); i++) {
switch (ARM::parseArch(ARMArch[i])) {
case ARM::ArchKind::ARMV6M:
case ARM::ArchKind::ARMV7M:
@ -864,7 +864,7 @@ TEST(TargetParserTest, ARMparseArchProfile) {
}
TEST(TargetParserTest, ARMparseArchVersion) {
for (unsigned i = 0; i < array_lengthof(ARMArch); i++)
for (unsigned i = 0; i < std::size(ARMArch); i++)
if (((std::string)ARMArch[i]).substr(0, 4) == "armv")
EXPECT_EQ((ARMArch[i][4] - 48u), ARM::parseArchVersion(ARMArch[i]));
else
@ -1585,7 +1585,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"pmuv3", "nopmuv3", "+perfmon", "-perfmon"},
};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
for (unsigned i = 0; i < std::size(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]),
AArch64::getArchExtFeature(ArchExt[i][0]));
EXPECT_EQ(StringRef(ArchExt[i][3]),

16
llvm/utils/KillTheDoctor/KillTheDoctor.cpp
View File

@ -204,10 +204,8 @@ static std::error_code GetFileNameFromHandle(HANDLE FileHandle,
if (!MappedFile)
return windows_error(::GetLastError());
Success = ::GetMappedFileNameA(::GetCurrentProcess(),
MappedFile,
Filename,
array_lengthof(Filename) - 1);
Success = ::GetMappedFileNameA(::GetCurrentProcess(), MappedFile, Filename,
std::size(Filename) - 1);
if (!Success)
return windows_error(::GetLastError());
@ -239,15 +237,11 @@ static std::string FindProgram(const std::string &Program,
LPCSTR Extension = NULL;
if (ext.size() && ext[0] == '.')
Extension = ext.c_str();
DWORD length = ::SearchPathA(NULL,
Program.c_str(),
Extension,
array_lengthof(PathName),
PathName,
NULL);
DWORD length = ::SearchPathA(NULL, Program.c_str(), Extension,
std::size(PathName), PathName, NULL);
if (length == 0)
ec = windows_error(::GetLastError());
else if (length > array_lengthof(PathName)) {
else if (length > std::size(PathName)) {
// This may have been the file, return with error.
ec = windows_error(ERROR_BUFFER_OVERFLOW);
break;

2
llvm/utils/TableGen/AsmWriterEmitter.cpp
View File

@ -1180,7 +1180,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
O.indent(2) << " makeArrayRef(OpToPatterns),\n";
O.indent(2) << " makeArrayRef(Patterns),\n";
O.indent(2) << " makeArrayRef(Conds),\n";
O.indent(2) << " StringRef(AsmStrings, array_lengthof(AsmStrings)),\n";
O.indent(2) << " StringRef(AsmStrings, std::size(AsmStrings)),\n";
if (MCOpPredicates.empty())
O.indent(2) << " nullptr,\n";
else

2
llvm/utils/TableGen/CodeGenTarget.cpp
View File

@ -482,7 +482,7 @@ static const char *FixedInstrs[] = {
nullptr};
unsigned CodeGenTarget::getNumFixedInstructions() {
return array_lengthof(FixedInstrs) - 1;
return std::size(FixedInstrs) - 1;
}
/// Return all of the instructions defined by the target, ordered by

4
llvm/utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -440,7 +440,7 @@ void RegisterInfoEmitter::EmitRegMappingTables(
OS << "extern const unsigned " << Namespace
<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize";
if (!isCtor)
OS << " = array_lengthof(" << Namespace
OS << " = std::size(" << Namespace
<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n";
else
OS << ";\n\n";
@ -498,7 +498,7 @@ void RegisterInfoEmitter::EmitRegMappingTables(
OS << "extern const unsigned " << Namespace
<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
if (!isCtor)
OS << " = array_lengthof(" << Namespace
OS << " = std::size(" << Namespace
<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
else
OS << ";\n\n";

2
llvm/utils/TableGen/X86DisassemblerTables.cpp
View File

@ -653,7 +653,7 @@ static const char* stringForDecisionType(ModRMDecisionType dt) {
}
DisassemblerTables::DisassemblerTables() {
for (unsigned i = 0; i < llvm::array_lengthof(Tables); i++)
for (unsigned i = 0; i < std::size(Tables); i++)
Tables[i] = std::make_unique<ContextDecision>();
HasConflicts = false;