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RegAlloc: Rename MLRegalloc* files to use consistent captalization
The other regalloc related files use RegAlloc, not Regalloc.
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@ -541,5 +541,5 @@ utils/bazel/llvm-project-overlay/libc/** @llvm/pr-subscribers-libc
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/llvm/test/Transforms/inline/ML/ @llvm/pr-subscribers-mlgo
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/llvm/lib/CodeGen/ML* @llvm/pr-subscribers-mlgo
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/llvm/unittests/CodeGen/ML* @llvm/pr-subscribers-mlgo
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/llvm/test/CodeGen/MLRegalloc/ @llvm/pr-subscribers-mlgo
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/llvm/test/CodeGen/MLRegAlloc/ @llvm/pr-subscribers-mlgo
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@ -5800,7 +5800,7 @@ llvm/lib/CodeGen/MIRPrintingPass.cpp
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llvm/lib/CodeGen/MIRSampleProfile.cpp
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llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
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llvm/lib/CodeGen/MIRYamlMapping.cpp
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llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp
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llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
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llvm/lib/CodeGen/MultiHazardRecognizer.cpp
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llvm/lib/CodeGen/NonRelocatableStringpool.cpp
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llvm/lib/CodeGen/ParallelCG.cpp
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@ -8,7 +8,7 @@ invocation (with the appropriate flags enabling the interactive mode)
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Examples:
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test/Transforms/Inline/ML/interactive-mode.ll
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test/CodeGen/MLRegalloc/interactive-mode.ll
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test/CodeGen/MLRegAlloc/interactive-mode.ll
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"""
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import ctypes
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@ -12,8 +12,8 @@ if (DEFINED LLVM_HAVE_TF_AOT OR LLVM_HAVE_TFLITE)
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"../Analysis/models/gen-regalloc-eviction-test-model.py"
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serve
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action
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RegallocEvictModel
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llvm::RegallocEvictModel
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RegAllocEvictModel
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llvm::RegAllocEvictModel
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)
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endif()
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@ -162,8 +162,8 @@ add_llvm_component_library(LLVMCodeGen
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MIRFSDiscriminator.cpp
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MIRSampleProfile.cpp
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MIRYamlMapping.cpp
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MLRegallocEvictAdvisor.cpp
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MLRegallocPriorityAdvisor.cpp
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MLRegAllocEvictAdvisor.cpp
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MLRegAllocPriorityAdvisor.cpp
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ModuloSchedule.cpp
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MultiHazardRecognizer.cpp
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PatchableFunction.cpp
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@ -21,7 +21,7 @@
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#include "llvm/Analysis/NoInferenceModelRunner.h"
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#include "llvm/Analysis/Utils/TrainingLogger.h"
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#endif
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#include "MLRegallocEvictAdvisor.h"
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#include "MLRegAllocEvictAdvisor.h"
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#include "llvm/Analysis/ReleaseModeModelRunner.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveRegMatrix.h"
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@ -48,8 +48,8 @@ using namespace llvm;
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// Generated header in release (AOT) mode
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#if defined(LLVM_HAVE_TF_AOT_REGALLOCEVICTMODEL)
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#include "RegallocEvictModel.h"
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using CompiledModelType = RegallocEvictModel;
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#include "RegAllocEvictModel.h"
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using CompiledModelType = RegAllocEvictModel;
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#else
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using CompiledModelType = NoopSavedModelImpl;
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#endif
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@ -40,7 +40,7 @@ add_llvm_unittest(CodeGenTests
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TypeTraitsTest.cpp
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TargetOptionsTest.cpp
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TestAsmPrinter.cpp
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MLRegallocDevelopmentFeatures.cpp
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MLRegAllocDevelopmentFeatures.cpp
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)
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add_subdirectory(GlobalISel)
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@ -1,4 +1,4 @@
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//===- MLRegAllocDevelopmentFeatures.cpp - test dev MLRegalloc features ---===//
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//===- MLRegAllocDevelopmentFeatures.cpp - test dev MLRegAlloc features ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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@ -6,7 +6,7 @@
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//
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//===----------------------------------------------------------------------===//
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#include "../../lib/CodeGen/MLRegallocEvictAdvisor.h"
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#include "../../lib/CodeGen/MLRegAllocEvictAdvisor.h"
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#include "llvm/Analysis/NoInferenceModelRunner.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -42,7 +42,7 @@ struct LRPosInfoIndexes {
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size_t PhysReg;
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};
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class RegallocDevelopmentFeaturesTest : public ::Test {
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class RegAllocDevelopmentFeaturesTest : public ::Test {
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protected:
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SmallVector<LRStartEndInfo>
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setupOverlapProblem(const SmallVectorImpl<LRPosInfoIndexes> &Segments,
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@ -139,7 +139,7 @@ protected:
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// meta tests to ensure that test setup works correctly
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TEST_F(RegallocDevelopmentFeaturesTest,
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TEST_F(RegAllocDevelopmentFeaturesTest,
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MetaOverlapInstructionDistancesAreCorrect) {
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SmallVector<LRPosInfoIndexes, 2> OverlapSetup;
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OverlapSetup.push_back({0, 5, 0});
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@ -151,7 +151,7 @@ TEST_F(RegallocDevelopmentFeaturesTest,
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ASSERT_EQ(OverlapProblem[0].End.distance(OverlapProblem[1].Begin), 0);
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}
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TEST_F(RegallocDevelopmentFeaturesTest, MetaSlotIndicesAreValid) {
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TEST_F(RegAllocDevelopmentFeaturesTest, MetaSlotIndicesAreValid) {
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SmallVector<LRPosInfoIndexes, 1> OverlapSetup;
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OverlapSetup.push_back({0, 10, 0});
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ilist<IndexListEntry> IndexList;
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@ -162,7 +162,7 @@ TEST_F(RegallocDevelopmentFeaturesTest, MetaSlotIndicesAreValid) {
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// Testing of feature extraction for per-instruction features
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TEST_F(RegallocDevelopmentFeaturesTest, InstructionOpcodesAreCorrect) {
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TEST_F(RegAllocDevelopmentFeaturesTest, InstructionOpcodesAreCorrect) {
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SmallVector<LRPosInfoIndexes, 1> OverlapSetup;
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OverlapSetup.push_back({0, ModelMaxSupportedInstructionCount - 1, 0});
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ilist<IndexListEntry> IndexList;
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@ -187,35 +187,35 @@ TEST_F(RegallocDevelopmentFeaturesTest, InstructionOpcodesAreCorrect) {
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}
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}
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TEST_F(RegallocDevelopmentFeaturesTest, FullOverlap) {
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TEST_F(RegAllocDevelopmentFeaturesTest, FullOverlap) {
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SmallVector<LRPosInfoIndexes, 2> OverlapSetup;
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OverlapSetup.push_back({0, ModelMaxSupportedInstructionCount - 1, 0});
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OverlapSetup.push_back({0, ModelMaxSupportedInstructionCount - 1, 1});
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runOverlapTest(OverlapSetup);
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}
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TEST_F(RegallocDevelopmentFeaturesTest, PartialOverlap) {
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TEST_F(RegAllocDevelopmentFeaturesTest, PartialOverlap) {
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SmallVector<LRPosInfoIndexes, 2> OverlapSetup;
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OverlapSetup.push_back({0, 20, 0});
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OverlapSetup.push_back({15, 30, 1});
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runOverlapTest(OverlapSetup);
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}
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TEST_F(RegallocDevelopmentFeaturesTest, PartialOverlapOpposite) {
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TEST_F(RegAllocDevelopmentFeaturesTest, PartialOverlapOpposite) {
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SmallVector<LRPosInfoIndexes, 2> OverlapSetup;
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OverlapSetup.push_back({15, 30, 1});
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OverlapSetup.push_back({0, 20, 0});
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runOverlapTest(OverlapSetup);
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}
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TEST_F(RegallocDevelopmentFeaturesTest, InternalOverlap) {
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TEST_F(RegAllocDevelopmentFeaturesTest, InternalOverlap) {
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SmallVector<LRPosInfoIndexes, 2> OverlapSetup;
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OverlapSetup.push_back({0, 30, 0});
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OverlapSetup.push_back({10, 20, 1});
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runOverlapTest(OverlapSetup);
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}
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TEST_F(RegallocDevelopmentFeaturesTest, TripleInternalOverlap) {
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TEST_F(RegAllocDevelopmentFeaturesTest, TripleInternalOverlap) {
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SmallVector<LRPosInfoIndexes, 3> OverlapSetup;
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OverlapSetup.push_back({0, 30, 0});
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OverlapSetup.push_back({10, 25, 1});
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@ -223,7 +223,7 @@ TEST_F(RegallocDevelopmentFeaturesTest, TripleInternalOverlap) {
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runOverlapTest(OverlapSetup);
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}
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TEST_F(RegallocDevelopmentFeaturesTest, InternalMultiOverlap) {
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TEST_F(RegAllocDevelopmentFeaturesTest, InternalMultiOverlap) {
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SmallVector<LRPosInfoIndexes, 3> OverlapSetup;
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OverlapSetup.push_back({0, 45, 0});
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OverlapSetup.push_back({30, 40, 1});
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@ -231,7 +231,7 @@ TEST_F(RegallocDevelopmentFeaturesTest, InternalMultiOverlap) {
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runOverlapTest(OverlapSetup);
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}
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TEST_F(RegallocDevelopmentFeaturesTest, SingleMBBTest) {
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TEST_F(RegAllocDevelopmentFeaturesTest, SingleMBBTest) {
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NoInferenceModelRunner ModelRunner = setupModelRunner();
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SlotIndex CurrentIndex;
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// set index to 1 so we can ensure that the mapping actually get set
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@ -244,7 +244,7 @@ TEST_F(RegallocDevelopmentFeaturesTest, SingleMBBTest) {
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ASSERT_EQ(ModelRunner.getTensor<int64_t>(3)[0], 1);
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}
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TEST_F(RegallocDevelopmentFeaturesTest, MBBFullTruncated) {
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TEST_F(RegAllocDevelopmentFeaturesTest, MBBFullTruncated) {
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SmallVector<LRPosInfoIndexes, 1> OverlapSetup;
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OverlapSetup.push_back({0, ModelMaxSupportedInstructionCount - 1, 0});
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ilist<IndexListEntry> IndexList;
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@ -128,8 +128,8 @@ static_library("CodeGen") {
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"MIRSampleProfile.cpp",
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"MIRVRegNamerUtils.cpp",
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"MIRYamlMapping.cpp",
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"MLRegallocEvictAdvisor.cpp",
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"MLRegallocPriorityAdvisor.cpp",
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"MLRegAllocEvictAdvisor.cpp",
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"MLRegAllocPriorityAdvisor.cpp",
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"MachineBasicBlock.cpp",
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"MachineBlockFrequencyInfo.cpp",
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"MachineBlockPlacement.cpp",
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@ -30,7 +30,7 @@ unittest("CodeGenTests") {
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"InstrRefLDVTest.cpp",
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"LexicalScopesTest.cpp",
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"LowLevelTypeTest.cpp",
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"MLRegallocDevelopmentFeatures.cpp",
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"MLRegAllocDevelopmentFeatures.cpp",
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"MachineBasicBlockTest.cpp",
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"MachineInstrBundleIteratorTest.cpp",
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"MachineInstrTest.cpp",
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