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[X86] Redefine avx512 packed fpclass intrinsics to return a vXi1 mask and implement the mask input argument using an 'and' IR instruction.
This recommits r335562 and 335563 as a single commit. The frontend will surround the intrinsic with the appropriate marshalling to/from a scalar type to match the sigature of the builtin that software expects. By exposing the vXi1 type directly in the llvm intrinsic we make it available to optimizers much earlier. This can enable the scalar marshalling code to be optimized away. llvm-svn: 335568
This commit is contained in:
Craig Topper
parent
9766fd64fb
commit
689e363ff2
@ -1251,28 +1251,22 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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llvm_v4i64_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_fpclass_pd_128 :
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GCCBuiltin<"__builtin_ia32_fpclasspd128_mask">,
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Intrinsic<[llvm_i8_ty], [llvm_v2f64_ty, llvm_i32_ty, llvm_i8_ty],
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Intrinsic<[llvm_v2i1_ty], [llvm_v2f64_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_fpclass_pd_256 :
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GCCBuiltin<"__builtin_ia32_fpclasspd256_mask">,
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Intrinsic<[llvm_i8_ty], [llvm_v4f64_ty, llvm_i32_ty, llvm_i8_ty],
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Intrinsic<[llvm_v4i1_ty], [llvm_v4f64_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_fpclass_pd_512 :
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GCCBuiltin<"__builtin_ia32_fpclasspd512_mask">,
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Intrinsic<[llvm_i8_ty], [llvm_v8f64_ty, llvm_i32_ty, llvm_i8_ty],
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Intrinsic<[llvm_v8i1_ty], [llvm_v8f64_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_fpclass_ps_128 :
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GCCBuiltin<"__builtin_ia32_fpclassps128_mask">,
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Intrinsic<[llvm_i8_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i8_ty],
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Intrinsic<[llvm_v4i1_ty], [llvm_v4f32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_fpclass_ps_256 :
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GCCBuiltin<"__builtin_ia32_fpclassps256_mask">,
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Intrinsic<[llvm_i8_ty], [llvm_v8f32_ty, llvm_i32_ty, llvm_i8_ty],
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Intrinsic<[llvm_v8i1_ty], [llvm_v8f32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_fpclass_ps_512 :
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GCCBuiltin<"__builtin_ia32_fpclassps512_mask">,
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Intrinsic<[llvm_i16_ty], [llvm_v16f32_ty, llvm_i32_ty, llvm_i16_ty],
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Intrinsic<[llvm_v16i1_ty], [llvm_v16f32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_fpclass_sd :
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GCCBuiltin<"__builtin_ia32_fpclasssd_mask">,
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@ -406,6 +406,24 @@ static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name,
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if (Name == "avx512.mask.cmp.ps.512") // Added in 7.0
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return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_512,
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NewFn);
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if (Name == "avx512.mask.fpclass.pd.128") // Added in 7.0
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return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_fpclass_pd_128,
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NewFn);
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if (Name == "avx512.mask.fpclass.pd.256") // Added in 7.0
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return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_fpclass_pd_256,
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NewFn);
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if (Name == "avx512.mask.fpclass.pd.512") // Added in 7.0
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return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_fpclass_pd_512,
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NewFn);
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if (Name == "avx512.mask.fpclass.ps.128") // Added in 7.0
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return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_fpclass_ps_128,
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NewFn);
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if (Name == "avx512.mask.fpclass.ps.256") // Added in 7.0
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return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_fpclass_ps_256,
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NewFn);
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if (Name == "avx512.mask.fpclass.ps.512") // Added in 7.0
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return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_fpclass_ps_512,
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NewFn);
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// frcz.ss/sd may need to have an argument dropped. Added in 3.2
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if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) {
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@ -3125,6 +3143,31 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
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return;
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}
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case Intrinsic::x86_avx512_mask_fpclass_pd_128:
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case Intrinsic::x86_avx512_mask_fpclass_pd_256:
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case Intrinsic::x86_avx512_mask_fpclass_pd_512:
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case Intrinsic::x86_avx512_mask_fpclass_ps_128:
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case Intrinsic::x86_avx512_mask_fpclass_ps_256:
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case Intrinsic::x86_avx512_mask_fpclass_ps_512: {
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SmallVector<Value *, 4> Args;
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Args.push_back(CI->getArgOperand(0));
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Args.push_back(CI->getArgOperand(1));
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NewCall = Builder.CreateCall(NewFn, Args);
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unsigned NumElts = Args[0]->getType()->getVectorNumElements();
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Value *Res = ApplyX86MaskOn1BitsVec(Builder, NewCall, CI->getArgOperand(2),
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NumElts);
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std::string Name = CI->getName();
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if (!Name.empty()) {
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CI->setName(Name + ".old");
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NewCall->setName(Name);
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}
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CI->replaceAllUsesWith(Res);
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CI->eraseFromParent();
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return;
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}
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case Intrinsic::thread_pointer: {
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NewCall = Builder.CreateCall(NewFn, {});
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break;
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@ -20748,23 +20748,11 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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Mask, PassThru, Subtarget, DAG);
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}
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case FPCLASS: {
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// FPclass intrinsics with mask
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SDValue Src1 = Op.getOperand(1);
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MVT VT = Src1.getSimpleValueType();
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MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
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SDValue Imm = Op.getOperand(2);
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SDValue Mask = Op.getOperand(3);
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MVT BitcastVT = MVT::getVectorVT(MVT::i1,
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Mask.getSimpleValueType().getSizeInBits());
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SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
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SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask, SDValue(),
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Subtarget, DAG);
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// Need to fill with zeros to ensure the bitcast will produce zeroes
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// for the upper bits in the v2i1/v4i1 case.
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SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
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DAG.getConstant(0, dl, BitcastVT),
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FPclassMask, DAG.getIntPtrConstant(0, dl));
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return DAG.getBitcast(Op.getValueType(), Res);
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// FPclass intrinsics
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SDValue Src1 = Op.getOperand(1);
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MVT MaskVT = Op.getSimpleValueType();
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SDValue Imm = Op.getOperand(2);
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return DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
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}
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case FPCLASSS: {
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SDValue Src1 = Op.getOperand(1);
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@ -20808,8 +20796,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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}
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case CMP_MASK_CC: {
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MVT VT = Op.getOperand(1).getSimpleValueType();
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MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
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MVT MaskVT = Op.getSimpleValueType();
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SDValue Cmp;
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SDValue CC = Op.getOperand(3);
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CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
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161
llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll
Normal file
161
llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll
Normal file
@ -0,0 +1,161 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=CHECK,X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/avx512dq-builtins.c
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define zeroext i8 @test_mm512_mask_fpclass_pd_mask(i8 zeroext %__U, <8 x double> %__A) {
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; X86-LABEL: test_mm512_mask_fpclass_pd_mask:
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; X86: # %bb.0: # %entry
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; X86-NEXT: vfpclasspd $4, %zmm0, %k0
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; X86-NEXT: kmovw %k0, %eax
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; X86-NEXT: andb {{[0-9]+}}(%esp), %al
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; X86-NEXT: # kill: def $al killed $al killed $eax
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; X86-NEXT: vzeroupper
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm512_mask_fpclass_pd_mask:
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; X64: # %bb.0: # %entry
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; X64-NEXT: vfpclasspd $4, %zmm0, %k0
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; X64-NEXT: kmovw %k0, %eax
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; X64-NEXT: andb %dil, %al
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: vzeroupper
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; X64-NEXT: retq
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entry:
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%0 = tail call <8 x i1> @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %__A, i32 4)
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%1 = bitcast i8 %__U to <8 x i1>
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%2 = and <8 x i1> %0, %1
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%3 = bitcast <8 x i1> %2 to i8
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ret i8 %3
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}
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declare <8 x i1> @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double>, i32)
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define zeroext i8 @test_mm512_fpclass_pd_mask(<8 x double> %__A) {
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; CHECK-LABEL: test_mm512_fpclass_pd_mask:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0
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; CHECK-NEXT: kmovw %k0, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: ret{{[l|q]}}
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entry:
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%0 = tail call <8 x i1> @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %__A, i32 4)
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%1 = bitcast <8 x i1> %0 to i8
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ret i8 %1
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}
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define zeroext i16 @test_mm512_mask_fpclass_ps_mask(i16 zeroext %__U, <16 x float> %__A) {
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; X86-LABEL: test_mm512_mask_fpclass_ps_mask:
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; X86: # %bb.0: # %entry
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; X86-NEXT: vfpclassps $4, %zmm0, %k0
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; X86-NEXT: kmovw %k0, %eax
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; X86-NEXT: andw {{[0-9]+}}(%esp), %ax
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; X86-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NEXT: vzeroupper
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm512_mask_fpclass_ps_mask:
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; X64: # %bb.0: # %entry
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; X64-NEXT: vfpclassps $4, %zmm0, %k0
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; X64-NEXT: kmovw %k0, %eax
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; X64-NEXT: andl %edi, %eax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: vzeroupper
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; X64-NEXT: retq
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entry:
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%0 = tail call <16 x i1> @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %__A, i32 4)
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%1 = bitcast i16 %__U to <16 x i1>
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%2 = and <16 x i1> %0, %1
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%3 = bitcast <16 x i1> %2 to i16
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ret i16 %3
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}
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declare <16 x i1> @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float>, i32)
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define zeroext i16 @test_mm512_fpclass_ps_mask(<16 x float> %__A) {
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; CHECK-LABEL: test_mm512_fpclass_ps_mask:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfpclassps $4, %zmm0, %k0
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; CHECK-NEXT: kmovw %k0, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: ret{{[l|q]}}
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entry:
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%0 = tail call <16 x i1> @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %__A, i32 4)
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%1 = bitcast <16 x i1> %0 to i16
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ret i16 %1
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}
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define zeroext i8 @test_mm_fpclass_sd_mask(<4 x float> %__A) {
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; CHECK-LABEL: test_mm_fpclass_sd_mask:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfpclasssd $2, %xmm0, %k0
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; CHECK-NEXT: kmovw %k0, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: ret{{[l|q]}}
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entry:
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%0 = bitcast <4 x float> %__A to <2 x double>
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%1 = tail call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %0, i32 2, i8 -1)
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ret i8 %1
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}
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declare i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double>, i32, i8)
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define zeroext i8 @test_mm_mask_fpclass_sd_mask(i8 zeroext %__U, <4 x float> %__A) {
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; X86-LABEL: test_mm_mask_fpclass_sd_mask:
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; X86: # %bb.0: # %entry
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; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1
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; X86-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1}
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; X86-NEXT: kmovw %k0, %eax
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; X86-NEXT: # kill: def $al killed $al killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm_mask_fpclass_sd_mask:
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; X64: # %bb.0: # %entry
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1}
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; X64-NEXT: kmovw %k0, %eax
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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entry:
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%0 = bitcast <4 x float> %__A to <2 x double>
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%1 = tail call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %0, i32 2, i8 %__U)
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ret i8 %1
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}
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define zeroext i8 @test_mm_fpclass_ss_mask(<4 x float> %__A) {
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; CHECK-LABEL: test_mm_fpclass_ss_mask:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfpclassss $2, %xmm0, %k0
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; CHECK-NEXT: kmovw %k0, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: ret{{[l|q]}}
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entry:
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%0 = tail call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %__A, i32 2, i8 -1)
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ret i8 %0
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}
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declare i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float>, i32, i8)
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define zeroext i8 @test_mm_mask_fpclass_ss_mask(i8 zeroext %__U, <4 x float> %__A) {
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; X86-LABEL: test_mm_mask_fpclass_ss_mask:
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; X86: # %bb.0: # %entry
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; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1
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; X86-NEXT: vfpclassss $2, %xmm0, %k0 {%k1}
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; X86-NEXT: kmovw %k0, %eax
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; X86-NEXT: # kill: def $al killed $al killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mm_mask_fpclass_ss_mask:
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; X64: # %bb.0: # %entry
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vfpclassss $2, %xmm0, %k0 {%k1}
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; X64-NEXT: kmovw %k0, %eax
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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entry:
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%0 = tail call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %__A, i32 2, i8 %__U)
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ret i8 %0
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}
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@ -536,3 +536,34 @@ define i8@test_int_x86_avx512_cvtq2mask_512(<8 x i64> %x0) {
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%res = call i8 @llvm.x86.avx512.cvtq2mask.512(<8 x i64> %x0)
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ret i8 %res
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}
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declare i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double>, i32, i8)
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define i8 @test_int_x86_avx512_mask_fpclass_pd_512(<8 x double> %x0) {
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; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_512:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vfpclasspd $2, %zmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x48,0x66,0xc8,0x02]
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; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x49,0x66,0xc0,0x04]
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; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
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%res = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 4, i8 -1)
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%res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 2, i8 %res)
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ret i8 %res1
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}
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declare i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float>, i32, i16)
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|
||||
define i16@test_int_x86_avx512_mask_fpclass_ps_512(<16 x float> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_512:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vfpclassps $2, %zmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x48,0x66,0xc8,0x02]
|
||||
; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x49,0x66,0xc0,0x04]
|
||||
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
|
||||
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 -1)
|
||||
%res1 = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 2, i16 %res)
|
||||
ret i16 %res1
|
||||
}
|
||||
|
||||
@ -600,7 +600,7 @@ define <2 x double>@test_int_x86_avx512_mask_range_sd(<2 x double> %x0, <2 x dou
|
||||
ret <2 x double> %res4
|
||||
}
|
||||
|
||||
declare i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double>, i32, i8)
|
||||
declare <8 x i1> @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double>, i32)
|
||||
|
||||
define i8 @test_int_x86_avx512_mask_fpclass_pd_512(<8 x double> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_512:
|
||||
@ -611,11 +611,13 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_512(<8 x double> %x0) {
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 4, i8 -1)
|
||||
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 2, i8 %res)
|
||||
ret i8 %res1
|
||||
%res = call <8 x i1> @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 4)
|
||||
%res1 = call <8 x i1> @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 2)
|
||||
%1 = and <8 x i1> %res1, %res
|
||||
%2 = bitcast <8 x i1> %1 to i8
|
||||
ret i8 %2
|
||||
}
|
||||
declare i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float>, i32, i16)
|
||||
declare <16 x i1> @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float>, i32)
|
||||
|
||||
define i16@test_int_x86_avx512_mask_fpclass_ps_512(<16 x float> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_512:
|
||||
@ -626,9 +628,11 @@ define i16@test_int_x86_avx512_mask_fpclass_ps_512(<16 x float> %x0) {
|
||||
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 -1)
|
||||
%res1 = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 2, i16 %res)
|
||||
ret i16 %res1
|
||||
%res = call <16 x i1> @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4)
|
||||
%res1 = call <16 x i1> @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 2)
|
||||
%1 = and <16 x i1> %res1, %res
|
||||
%2 = bitcast <16 x i1> %1 to i16
|
||||
ret i16 %2
|
||||
}
|
||||
|
||||
declare i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double>, i32, i8)
|
||||
|
||||
@ -203,3 +203,174 @@ entry:
|
||||
%1 = select <4 x i1> %extract.i, <4 x double> %conv.i.i, <4 x double> zeroinitializer
|
||||
ret <4 x double> %1
|
||||
}
|
||||
|
||||
define zeroext i8 @test_mm_mask_fpclass_pd_mask(i8 zeroext %__U, <2 x double> %__A) {
|
||||
; X86-LABEL: test_mm_mask_fpclass_pd_mask:
|
||||
; X86: # %bb.0: # %entry
|
||||
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1
|
||||
; X86-NEXT: vfpclasspd $2, %xmm0, %k0 {%k1}
|
||||
; X86-NEXT: kmovw %k0, %eax
|
||||
; X86-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_mm_mask_fpclass_pd_mask:
|
||||
; X64: # %bb.0: # %entry
|
||||
; X64-NEXT: kmovw %edi, %k1
|
||||
; X64-NEXT: vfpclasspd $2, %xmm0, %k0 {%k1}
|
||||
; X64-NEXT: kmovw %k0, %eax
|
||||
; X64-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X64-NEXT: retq
|
||||
entry:
|
||||
%0 = tail call <2 x i1> @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %__A, i32 2)
|
||||
%1 = bitcast i8 %__U to <8 x i1>
|
||||
%extract = shufflevector <8 x i1> %1, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
|
||||
%2 = and <2 x i1> %0, %extract
|
||||
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
|
||||
%4 = bitcast <8 x i1> %3 to i8
|
||||
ret i8 %4
|
||||
}
|
||||
|
||||
declare <2 x i1> @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double>, i32)
|
||||
|
||||
define zeroext i8 @test_mm_fpclass_pd_mask(<2 x double> %__A) {
|
||||
; CHECK-LABEL: test_mm_fpclass_pd_mask:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vfpclasspd $2, %xmm0, %k0
|
||||
; CHECK-NEXT: kmovw %k0, %eax
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: ret{{[l|q]}}
|
||||
entry:
|
||||
%0 = tail call <2 x i1> @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %__A, i32 2)
|
||||
%1 = shufflevector <2 x i1> %0, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
|
||||
%2 = bitcast <8 x i1> %1 to i8
|
||||
ret i8 %2
|
||||
}
|
||||
|
||||
define zeroext i8 @test_mm256_mask_fpclass_pd_mask(i8 zeroext %__U, <4 x double> %__A) {
|
||||
; X86-LABEL: test_mm256_mask_fpclass_pd_mask:
|
||||
; X86: # %bb.0: # %entry
|
||||
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1
|
||||
; X86-NEXT: vfpclasspd $2, %ymm0, %k0 {%k1}
|
||||
; X86-NEXT: kmovw %k0, %eax
|
||||
; X86-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X86-NEXT: vzeroupper
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_mm256_mask_fpclass_pd_mask:
|
||||
; X64: # %bb.0: # %entry
|
||||
; X64-NEXT: kmovw %edi, %k1
|
||||
; X64-NEXT: vfpclasspd $2, %ymm0, %k0 {%k1}
|
||||
; X64-NEXT: kmovw %k0, %eax
|
||||
; X64-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X64-NEXT: vzeroupper
|
||||
; X64-NEXT: retq
|
||||
entry:
|
||||
%0 = tail call <4 x i1> @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %__A, i32 2)
|
||||
%1 = bitcast i8 %__U to <8 x i1>
|
||||
%extract = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%2 = and <4 x i1> %0, %extract
|
||||
%3 = shufflevector <4 x i1> %2, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%4 = bitcast <8 x i1> %3 to i8
|
||||
ret i8 %4
|
||||
}
|
||||
|
||||
declare <4 x i1> @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double>, i32)
|
||||
|
||||
define zeroext i8 @test_mm256_fpclass_pd_mask(<4 x double> %__A) {
|
||||
; CHECK-LABEL: test_mm256_fpclass_pd_mask:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vfpclasspd $2, %ymm0, %k0
|
||||
; CHECK-NEXT: kmovw %k0, %eax
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: vzeroupper
|
||||
; CHECK-NEXT: ret{{[l|q]}}
|
||||
entry:
|
||||
%0 = tail call <4 x i1> @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %__A, i32 2)
|
||||
%1 = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%2 = bitcast <8 x i1> %1 to i8
|
||||
ret i8 %2
|
||||
}
|
||||
|
||||
define zeroext i8 @test_mm_mask_fpclass_ps_mask(i8 zeroext %__U, <4 x float> %__A) {
|
||||
; X86-LABEL: test_mm_mask_fpclass_ps_mask:
|
||||
; X86: # %bb.0: # %entry
|
||||
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1
|
||||
; X86-NEXT: vfpclassps $2, %xmm0, %k0 {%k1}
|
||||
; X86-NEXT: kmovw %k0, %eax
|
||||
; X86-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_mm_mask_fpclass_ps_mask:
|
||||
; X64: # %bb.0: # %entry
|
||||
; X64-NEXT: kmovw %edi, %k1
|
||||
; X64-NEXT: vfpclassps $2, %xmm0, %k0 {%k1}
|
||||
; X64-NEXT: kmovw %k0, %eax
|
||||
; X64-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X64-NEXT: retq
|
||||
entry:
|
||||
%0 = tail call <4 x i1> @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %__A, i32 2)
|
||||
%1 = bitcast i8 %__U to <8 x i1>
|
||||
%extract = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%2 = and <4 x i1> %0, %extract
|
||||
%3 = shufflevector <4 x i1> %2, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%4 = bitcast <8 x i1> %3 to i8
|
||||
ret i8 %4
|
||||
}
|
||||
|
||||
declare <4 x i1> @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float>, i32)
|
||||
|
||||
define zeroext i8 @test_mm_fpclass_ps_mask(<4 x float> %__A) {
|
||||
; CHECK-LABEL: test_mm_fpclass_ps_mask:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vfpclassps $2, %xmm0, %k0
|
||||
; CHECK-NEXT: kmovw %k0, %eax
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: ret{{[l|q]}}
|
||||
entry:
|
||||
%0 = tail call <4 x i1> @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %__A, i32 2)
|
||||
%1 = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%2 = bitcast <8 x i1> %1 to i8
|
||||
ret i8 %2
|
||||
}
|
||||
|
||||
define zeroext i8 @test_mm256_mask_fpclass_ps_mask(i8 zeroext %__U, <8 x float> %__A) {
|
||||
; X86-LABEL: test_mm256_mask_fpclass_ps_mask:
|
||||
; X86: # %bb.0: # %entry
|
||||
; X86-NEXT: vfpclassps $2, %ymm0, %k0
|
||||
; X86-NEXT: kmovw %k0, %eax
|
||||
; X86-NEXT: andb {{[0-9]+}}(%esp), %al
|
||||
; X86-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X86-NEXT: vzeroupper
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_mm256_mask_fpclass_ps_mask:
|
||||
; X64: # %bb.0: # %entry
|
||||
; X64-NEXT: vfpclassps $2, %ymm0, %k0
|
||||
; X64-NEXT: kmovw %k0, %eax
|
||||
; X64-NEXT: andb %dil, %al
|
||||
; X64-NEXT: # kill: def $al killed $al killed $eax
|
||||
; X64-NEXT: vzeroupper
|
||||
; X64-NEXT: retq
|
||||
entry:
|
||||
%0 = tail call <8 x i1> @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %__A, i32 2)
|
||||
%1 = bitcast i8 %__U to <8 x i1>
|
||||
%2 = and <8 x i1> %0, %1
|
||||
%3 = bitcast <8 x i1> %2 to i8
|
||||
ret i8 %3
|
||||
}
|
||||
|
||||
declare <8 x i1> @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float>, i32)
|
||||
|
||||
define zeroext i8 @test_mm256_fpclass_ps_mask(<8 x float> %__A) {
|
||||
; CHECK-LABEL: test_mm256_fpclass_ps_mask:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vfpclassps $2, %ymm0, %k0
|
||||
; CHECK-NEXT: kmovw %k0, %eax
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: vzeroupper
|
||||
; CHECK-NEXT: ret{{[l|q]}}
|
||||
entry:
|
||||
%0 = tail call <8 x i1> @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %__A, i32 2)
|
||||
%1 = bitcast <8 x i1> %0 to i8
|
||||
ret i8 %1
|
||||
}
|
||||
|
||||
@ -2928,3 +2928,65 @@ define <4 x double>@test_int_x86_avx512_mask_cvt_uqq2pd_256(<4 x i64> %x0, <4 x
|
||||
%res2 = fadd <4 x double> %res, %res1
|
||||
ret <4 x double> %res2
|
||||
}
|
||||
|
||||
declare i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float>, i32, i8)
|
||||
|
||||
define i8 @test_int_x86_avx512_mask_fpclass_ps_128(<4 x float> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_128:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vfpclassps $4, %xmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x08,0x66,0xc8,0x04]
|
||||
; CHECK-NEXT: vfpclassps $2, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x66,0xc0,0x02]
|
||||
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 2, i8 -1)
|
||||
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 4, i8 %res)
|
||||
ret i8 %res1
|
||||
}
|
||||
|
||||
declare i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float>, i32, i8)
|
||||
|
||||
define i8 @test_int_x86_avx512_mask_fpclass_ps_256(<8 x float> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_256:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vfpclassps $4, %ymm0, %k1 # encoding: [0x62,0xf3,0x7d,0x28,0x66,0xc8,0x04]
|
||||
; CHECK-NEXT: vfpclassps $2, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x29,0x66,0xc0,0x02]
|
||||
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 2, i8 -1)
|
||||
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 4, i8 %res)
|
||||
ret i8 %res1
|
||||
}
|
||||
|
||||
declare i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double>, i32, i8)
|
||||
|
||||
define i8 @test_int_x86_avx512_mask_fpclass_pd_128(<2 x double> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_128:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vfpclasspd $2, %xmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x08,0x66,0xc8,0x02]
|
||||
; CHECK-NEXT: vfpclasspd $4, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x66,0xc0,0x04]
|
||||
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 4, i8 -1)
|
||||
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 2, i8 %res)
|
||||
ret i8 %res1
|
||||
}
|
||||
|
||||
declare i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double>, i32, i8)
|
||||
|
||||
define i8 @test_int_x86_avx512_mask_fpclass_pd_256(<4 x double> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_256:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vfpclasspd $4, %ymm0, %k1 # encoding: [0x62,0xf3,0xfd,0x28,0x66,0xc8,0x04]
|
||||
; CHECK-NEXT: vfpclasspd $2, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x29,0x66,0xc0,0x02]
|
||||
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 2, i8 -1)
|
||||
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 4, i8 %res)
|
||||
ret i8 %res1
|
||||
}
|
||||
|
||||
@ -734,7 +734,7 @@ define <8 x float>@test_int_x86_avx512_mask_range_ps_256(<8 x float> %x0, <8 x f
|
||||
ret <8 x float> %res2
|
||||
}
|
||||
|
||||
declare i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float>, i32, i8)
|
||||
declare <4 x i1> @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float>, i32)
|
||||
|
||||
define i8 @test_int_x86_avx512_mask_fpclass_ps_128(<4 x float> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_128:
|
||||
@ -744,12 +744,15 @@ define i8 @test_int_x86_avx512_mask_fpclass_ps_128(<4 x float> %x0) {
|
||||
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 2, i8 -1)
|
||||
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 4, i8 %res)
|
||||
ret i8 %res1
|
||||
%res = call <4 x i1> @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 2)
|
||||
%res1 = call <4 x i1> @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 4)
|
||||
%1 = and <4 x i1> %res1, %res
|
||||
%2 = shufflevector <4 x i1> %1, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%3 = bitcast <8 x i1> %2 to i8
|
||||
ret i8 %3
|
||||
}
|
||||
|
||||
declare i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float>, i32, i8)
|
||||
declare <8 x i1> @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float>, i32)
|
||||
|
||||
define i8 @test_int_x86_avx512_mask_fpclass_ps_256(<8 x float> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_256:
|
||||
@ -760,12 +763,14 @@ define i8 @test_int_x86_avx512_mask_fpclass_ps_256(<8 x float> %x0) {
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 2, i8 -1)
|
||||
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 4, i8 %res)
|
||||
ret i8 %res1
|
||||
%res = call <8 x i1> @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 2)
|
||||
%res1 = call <8 x i1> @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 4)
|
||||
%1 = and <8 x i1> %res1, %res
|
||||
%2 = bitcast <8 x i1> %1 to i8
|
||||
ret i8 %2
|
||||
}
|
||||
|
||||
declare i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double>, i32, i8)
|
||||
declare <2 x i1> @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double>, i32)
|
||||
|
||||
define i8 @test_int_x86_avx512_mask_fpclass_pd_128(<2 x double> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_128:
|
||||
@ -775,12 +780,15 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_128(<2 x double> %x0) {
|
||||
; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0]
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 4, i8 -1)
|
||||
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 2, i8 %res)
|
||||
ret i8 %res1
|
||||
%res = call <2 x i1> @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 4)
|
||||
%res1 = call <2 x i1> @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 2)
|
||||
%1 = and <2 x i1> %res1, %res
|
||||
%2 = shufflevector <2 x i1> %1, <2 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
|
||||
%3 = bitcast <8 x i1> %2 to i8
|
||||
ret i8 %3
|
||||
}
|
||||
|
||||
declare i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double>, i32, i8)
|
||||
declare <4 x i1> @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double>, i32)
|
||||
|
||||
define i8 @test_int_x86_avx512_mask_fpclass_pd_256(<4 x double> %x0) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_256:
|
||||
@ -791,7 +799,10 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_256(<4 x double> %x0) {
|
||||
; CHECK-NEXT: # kill: def $al killed $al killed $eax
|
||||
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
||||
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||
%res = call i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 2, i8 -1)
|
||||
%res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 4, i8 %res)
|
||||
ret i8 %res1
|
||||
%res = call <4 x i1> @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 2)
|
||||
%res1 = call <4 x i1> @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 4)
|
||||
%1 = and <4 x i1> %res1, %res
|
||||
%2 = shufflevector <4 x i1> %1, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
%3 = bitcast <8 x i1> %2 to i8
|
||||
ret i8 %3
|
||||
}
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user