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[AArch64] Remove copy/pasted RISC-V extension names from some tests. NFC

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This commit is contained in:
Craig Topper 2023-07-31 17:34:28 -07:00
parent 8ccdb8e40a
commit 690edeab78
4 changed files with 8 additions and 12 deletions
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5
clang/test/Sema/aarch64-sve-vector-exp-ops.c
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@ -1,6 +1,5 @@
// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +sve -target-feature +zvfh \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// REQUIRES: aarch64-registered-target
#include <arm_sve.h>

5
clang/test/Sema/aarch64-sve-vector-log-ops.c
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@ -1,6 +1,5 @@
// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +sve -target-feature +zvfh \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// REQUIRES: aarch64-registered-target
#include <arm_sve.h>

5
clang/test/Sema/aarch64-sve-vector-pow-ops.c
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@ -1,6 +1,5 @@
// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +sve -target-feature +experimental-zvfh \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// REQUIRES: aarch64-registered-target
#include <arm_sve.h>

5
clang/test/Sema/aarch64-sve-vector-trig-ops.c
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@ -1,6 +1,5 @@
// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +sve -target-feature +zvfh \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// REQUIRES: aarch64-registered-target
#include <arm_sve.h>