From 690edeab78ba6996a44f6fd9e8fce79cb78e7737 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Mon, 31 Jul 2023 17:34:28 -0700
Subject: [PATCH] [AArch64] Remove copy/pasted RISC-V extension names from some
 tests. NFC

---
 clang/test/Sema/aarch64-sve-vector-exp-ops.c  | 5 ++---
 clang/test/Sema/aarch64-sve-vector-log-ops.c  | 5 ++---
 clang/test/Sema/aarch64-sve-vector-pow-ops.c  | 5 ++---
 clang/test/Sema/aarch64-sve-vector-trig-ops.c | 5 ++---
 4 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/clang/test/Sema/aarch64-sve-vector-exp-ops.c b/clang/test/Sema/aarch64-sve-vector-exp-ops.c
index 2b17442cc2cd..f2bba8c7eeb1 100644
--- a/clang/test/Sema/aarch64-sve-vector-exp-ops.c
+++ b/clang/test/Sema/aarch64-sve-vector-exp-ops.c
@@ -1,6 +1,5 @@
-// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \
-// RUN:   -target-feature +v -target-feature +zfh  -target-feature +sve -target-feature +zvfh \
-// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify
 // REQUIRES: aarch64-registered-target
 
 #include <arm_sve.h>
diff --git a/clang/test/Sema/aarch64-sve-vector-log-ops.c b/clang/test/Sema/aarch64-sve-vector-log-ops.c
index 493e919a3f50..2beb616c1edb 100644
--- a/clang/test/Sema/aarch64-sve-vector-log-ops.c
+++ b/clang/test/Sema/aarch64-sve-vector-log-ops.c
@@ -1,6 +1,5 @@
-// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \
-// RUN:   -target-feature +v -target-feature +zfh  -target-feature +sve -target-feature +zvfh \
-// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify
 // REQUIRES: aarch64-registered-target
 
 #include <arm_sve.h>
diff --git a/clang/test/Sema/aarch64-sve-vector-pow-ops.c b/clang/test/Sema/aarch64-sve-vector-pow-ops.c
index 1024cdc2517d..e61d752911fc 100644
--- a/clang/test/Sema/aarch64-sve-vector-pow-ops.c
+++ b/clang/test/Sema/aarch64-sve-vector-pow-ops.c
@@ -1,6 +1,5 @@
-// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \
-// RUN:   -target-feature +v -target-feature +zfh  -target-feature +sve -target-feature +experimental-zvfh \
-// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify
 // REQUIRES: aarch64-registered-target
 
 #include <arm_sve.h>
diff --git a/clang/test/Sema/aarch64-sve-vector-trig-ops.c b/clang/test/Sema/aarch64-sve-vector-trig-ops.c
index 6d71088f9f54..7ca941f578c7 100644
--- a/clang/test/Sema/aarch64-sve-vector-trig-ops.c
+++ b/clang/test/Sema/aarch64-sve-vector-trig-ops.c
@@ -1,6 +1,5 @@
-// RUN: %clang_cc1 -triple aarch64 -target-feature +f -target-feature +d \
-// RUN:   -target-feature +v -target-feature +zfh  -target-feature +sve -target-feature +zvfh \
-// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify 
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve \
+// RUN:   -disable-O0-optnone -o - -fsyntax-only %s -verify
 // REQUIRES: aarch64-registered-target
 
 #include <arm_sve.h>