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[RISCV] Use GPRMemZeroOffset instead of GPRMem in RISCVInstrInfoVPseudos.td. NFC
The distinction between GPRMem and GPRMemZeroOffset only matters for parsing which doesn't apply to pseudos.
This commit is contained in:
Craig Topper
parent
c359f7625f
commit
6a63abce7b
@ -783,7 +783,7 @@ class VPseudoUSLoadNoMask<VReg RetClass,
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int EEW,
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DAGOperand sewop = sew> :
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Pseudo<(outs RetClass:$rd),
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(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sewop:$sew,
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(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew,
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vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
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@ -800,7 +800,7 @@ class VPseudoUSLoadMask<VReg RetClass,
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int EEW> :
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Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
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(ins GetVRegNoV0<RetClass>.R:$passthru,
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GPRMem:$rs1,
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GPRMemZeroOffset:$rs1,
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VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
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@ -818,7 +818,7 @@ class VPseudoUSLoadMask<VReg RetClass,
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class VPseudoUSLoadFFNoMask<VReg RetClass,
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int EEW> :
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Pseudo<(outs RetClass:$rd, GPR:$vl),
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(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
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(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
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sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
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@ -835,7 +835,7 @@ class VPseudoUSLoadFFMask<VReg RetClass,
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int EEW> :
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Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
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(ins GetVRegNoV0<RetClass>.R:$passthru,
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GPRMem:$rs1,
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GPRMemZeroOffset:$rs1,
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VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
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@ -853,7 +853,7 @@ class VPseudoUSLoadFFMask<VReg RetClass,
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class VPseudoSLoadNoMask<VReg RetClass,
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int EEW> :
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Pseudo<(outs RetClass:$rd),
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(ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl,
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(ins RetClass:$dest, GPRMemZeroOffset:$rs1, GPR:$rs2, AVL:$vl,
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sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
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@ -870,7 +870,7 @@ class VPseudoSLoadMask<VReg RetClass,
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int EEW> :
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Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
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(ins GetVRegNoV0<RetClass>.R:$passthru,
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GPRMem:$rs1, GPR:$rs2,
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GPRMemZeroOffset:$rs1, GPR:$rs2,
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VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
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@ -893,7 +893,7 @@ class VPseudoILoadNoMask<VReg RetClass,
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bit EarlyClobber,
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bits<2> TargetConstraintType = 1> :
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Pseudo<(outs RetClass:$rd),
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(ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
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(ins RetClass:$dest, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl,
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sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
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@ -916,7 +916,7 @@ class VPseudoILoadMask<VReg RetClass,
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bits<2> TargetConstraintType = 1> :
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Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
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(ins GetVRegNoV0<RetClass>.R:$passthru,
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GPRMem:$rs1, IdxClass:$rs2,
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GPRMemZeroOffset:$rs1, IdxClass:$rs2,
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VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
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@ -936,7 +936,7 @@ class VPseudoUSStoreNoMask<VReg StClass,
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int EEW,
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DAGOperand sewop = sew> :
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Pseudo<(outs),
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(ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sewop:$sew), []>,
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(ins StClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew), []>,
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RISCVVPseudo,
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RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
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let mayLoad = 0;
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@ -949,7 +949,7 @@ class VPseudoUSStoreNoMask<VReg StClass,
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class VPseudoUSStoreMask<VReg StClass,
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int EEW> :
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Pseudo<(outs),
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(ins StClass:$rd, GPRMem:$rs1,
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(ins StClass:$rd, GPRMemZeroOffset:$rs1,
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VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
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RISCVVPseudo,
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RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
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@ -964,7 +964,7 @@ class VPseudoUSStoreMask<VReg StClass,
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class VPseudoSStoreNoMask<VReg StClass,
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int EEW> :
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Pseudo<(outs),
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(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
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(ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
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AVL:$vl, sew:$sew), []>,
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RISCVVPseudo,
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RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
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@ -978,7 +978,7 @@ class VPseudoSStoreNoMask<VReg StClass,
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class VPseudoSStoreMask<VReg StClass,
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int EEW> :
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Pseudo<(outs),
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(ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
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(ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
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VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
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RISCVVPseudo,
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RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
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@ -1329,7 +1329,7 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
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class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
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bit Ordered>:
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Pseudo<(outs),
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(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
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(ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl,
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sew:$sew),[]>,
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RISCVVPseudo,
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RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
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@ -1343,7 +1343,7 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
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class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
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bit Ordered>:
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Pseudo<(outs),
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(ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2,
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(ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,
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VMaskOp:$vm, AVL:$vl, sew:$sew),[]>,
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RISCVVPseudo,
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RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
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@ -1598,7 +1598,7 @@ class VPseudoUSSegLoadNoMask<VReg RetClass,
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int EEW,
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bits<4> NF> :
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Pseudo<(outs RetClass:$rd),
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(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
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(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl,
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sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
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@ -1615,7 +1615,7 @@ class VPseudoUSSegLoadMask<VReg RetClass,
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int EEW,
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bits<4> NF> :
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Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
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(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
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(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
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VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
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@ -1634,7 +1634,7 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass,
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int EEW,
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bits<4> NF> :
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Pseudo<(outs RetClass:$rd, GPR:$vl),
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(ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
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(ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
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sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
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@ -1651,7 +1651,7 @@ class VPseudoUSSegLoadFFMask<VReg RetClass,
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int EEW,
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bits<4> NF> :
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Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
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(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
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(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
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VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
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@ -1670,7 +1670,7 @@ class VPseudoSSegLoadNoMask<VReg RetClass,
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int EEW,
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bits<4> NF> :
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Pseudo<(outs RetClass:$rd),
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(ins RetClass:$passthru, GPRMem:$rs1, GPR:$offset, AVL:$vl,
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(ins RetClass:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset, AVL:$vl,
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sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
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@ -1687,7 +1687,7 @@ class VPseudoSSegLoadMask<VReg RetClass,
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int EEW,
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bits<4> NF> :
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Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
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(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
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(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
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GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
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vec_policy:$policy), []>,
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RISCVVPseudo,
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@ -1710,7 +1710,7 @@ class VPseudoISegLoadNoMask<VReg RetClass,
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bits<4> NF,
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bit Ordered> :
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Pseudo<(outs RetClass:$rd),
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(ins RetClass:$passthru, GPRMem:$rs1, IdxClass:$offset, AVL:$vl,
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(ins RetClass:$passthru, GPRMemZeroOffset:$rs1, IdxClass:$offset, AVL:$vl,
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sew:$sew, vec_policy:$policy), []>,
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RISCVVPseudo,
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RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
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@ -1732,7 +1732,7 @@ class VPseudoISegLoadMask<VReg RetClass,
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bits<4> NF,
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bit Ordered> :
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Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
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(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
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(ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
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IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
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vec_policy:$policy), []>,
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RISCVVPseudo,
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@ -1754,7 +1754,7 @@ class VPseudoUSSegStoreNoMask<VReg ValClass,
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int EEW,
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bits<4> NF> :
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Pseudo<(outs),
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(ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>,
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(ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew), []>,
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RISCVVPseudo,
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RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
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let mayLoad = 0;
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@ -1768,7 +1768,7 @@ class VPseudoUSSegStoreMask<VReg ValClass,
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int EEW,
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bits<4> NF> :
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Pseudo<(outs),
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(ins ValClass:$rd, GPRMem:$rs1,
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(ins ValClass:$rd, GPRMemZeroOffset:$rs1,
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VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
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RISCVVPseudo,
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RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
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@ -1784,7 +1784,7 @@ class VPseudoSSegStoreNoMask<VReg ValClass,
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int EEW,
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bits<4> NF> :
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Pseudo<(outs),
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(ins ValClass:$rd, GPRMem:$rs1, GPR:$offset,
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(ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR:$offset,
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AVL:$vl, sew:$sew), []>,
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RISCVVPseudo,
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RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
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@ -1799,7 +1799,7 @@ class VPseudoSSegStoreMask<VReg ValClass,
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int EEW,
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bits<4> NF> :
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Pseudo<(outs),
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(ins ValClass:$rd, GPRMem:$rs1, GPR: $offset,
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(ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR: $offset,
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VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
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RISCVVPseudo,
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RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
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@ -1818,7 +1818,7 @@ class VPseudoISegStoreNoMask<VReg ValClass,
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bits<4> NF,
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bit Ordered> :
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Pseudo<(outs),
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(ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
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(ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
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AVL:$vl, sew:$sew), []>,
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RISCVVPseudo,
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RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
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@ -1836,7 +1836,7 @@ class VPseudoISegStoreMask<VReg ValClass,
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bits<4> NF,
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bit Ordered> :
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Pseudo<(outs),
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(ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
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(ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
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VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
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RISCVVPseudo,
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RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
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