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[InstCombine] Check for poison instead of undef in shuffle combine

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Otherwise we may replace undef with poison.

Note that a lot of tests regressing here already have variants
that use poison instead of undef (often in a separate
inseltpoison file), which is why I'm not adjusting them to the
new pattern.
This commit is contained in:
Nikita Popov 2023-12-18 14:44:32 +01:00
parent 7e5019e82b
commit 6c9813aa02
7 changed files with 22 additions and 13 deletions
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7
llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
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@ -3013,10 +3013,11 @@ Instruction *InstCombinerImpl::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
ShuffleVectorInst* LHSShuffle = dyn_cast<ShuffleVectorInst>(LHS);
ShuffleVectorInst* RHSShuffle = dyn_cast<ShuffleVectorInst>(RHS);
if (LHSShuffle)
if (!match(LHSShuffle->getOperand(1), m_Undef()) && !match(RHS, m_Undef()))
if (!match(LHSShuffle->getOperand(1), m_Poison()) &&
!match(RHS, m_Poison()))
LHSShuffle = nullptr;
if (RHSShuffle)
if (!match(RHSShuffle->getOperand(1), m_Undef()))
if (!match(RHSShuffle->getOperand(1), m_Poison()))
RHSShuffle = nullptr;
if (!LHSShuffle && !RHSShuffle)
return MadeChange ? &SVI : nullptr;
@ -3039,7 +3040,7 @@ Instruction *InstCombinerImpl::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
Value* newRHS = RHS;
if (LHSShuffle) {
// case 1
if (match(RHS, m_Undef())) {
if (match(RHS, m_Poison())) {
newLHS = LHSOp0;
newRHS = LHSOp1;
}

2
llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
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@ -238,7 +238,7 @@ define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_4(<4 x i3
%elt2 = extractelement <4 x float> %data, i32 2
%ins0 = insertelement <2 x float> poison, float %elt0, i32 0
%ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
%shuf = shufflevector <4 x float> undef, <4 x float> %data, <2 x i32> <i32 5, i32 1>
%shuf = shufflevector <4 x float> poison, <4 x float> %data, <2 x i32> <i32 5, i32 1>
%ret = fadd <2 x float> %ins1, %shuf
ret <2 x float> %ret
}

2
llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
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@ -238,7 +238,7 @@ define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_4(<4 x i3
%elt2 = extractelement <4 x float> %data, i32 2
%ins0 = insertelement <2 x float> undef, float %elt0, i32 0
%ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
%shuf = shufflevector <4 x float> undef, <4 x float> %data, <2 x i32> <i32 5, i32 1>
%shuf = shufflevector <4 x float> poison, <4 x float> %data, <2 x i32> <i32 5, i32 1>
%ret = fadd <2 x float> %ins1, %shuf
ret <2 x float> %ret
}

4
llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll
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@ -236,7 +236,7 @@ define <4 x float> @elts_test_vpermilvar_ps(<4 x float> %a0, i32 %a1) {
define <8 x float> @elts_test_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a1) {
; CHECK-LABEL: @elts_test_vpermilvar_ps_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> poison, <8 x i32> <i32 poison, i32 0, i32 poison, i32 1, i32 poison, i32 6, i32 poison, i32 7>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> undef, <8 x i32> <i32 poison, i32 0, i32 poison, i32 1, i32 poison, i32 6, i32 poison, i32 7>
; CHECK-NEXT: ret <8 x float> [[TMP1]]
;
%1 = shufflevector <8 x i32> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 2, i32 1, i32 0>, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
@ -270,7 +270,7 @@ define <2 x double> @elts_test_vpermilvar_pd(<2 x double> %a0, i64 %a1) {
define <4 x double> @elts_test_vpermilvar_pd_256(<4 x double> %a0, <4 x i64> %a1) {
; CHECK-LABEL: @elts_test_vpermilvar_pd_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 poison>
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 poison>
; CHECK-NEXT: ret <4 x double> [[TMP1]]
;
%1 = shufflevector <4 x i64> <i64 0, i64 2, i64 0, i64 2>, <4 x i64> %a1, <4 x i32> <i32 1, i32 2, i32 3, i32 4>

4
llvm/test/Transforms/InstCombine/obfuscated_splat.ll
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@ -5,7 +5,9 @@ define void @test_undef(ptr %in_ptr, ptr %out_ptr) {
; CHECK-LABEL: define void @test_undef(
; CHECK-SAME: ptr [[IN_PTR:%.*]], ptr [[OUT_PTR:%.*]]) {
; CHECK-NEXT: [[A:%.*]] = load <4 x float>, ptr [[IN_PTR]], align 16
; CHECK-NEXT: [[D:%.*]] = shufflevector <4 x float> [[A]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[B:%.*]] = shufflevector <4 x float> [[A]], <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 poison, i32 poison>
; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x float> [[B]], <4 x float> [[A]], <4 x i32> <i32 0, i32 1, i32 4, i32 poison>
; CHECK-NEXT: [[D:%.*]] = shufflevector <4 x float> [[C]], <4 x float> [[A]], <4 x i32> <i32 0, i32 1, i32 2, i32 4>
; CHECK-NEXT: store <4 x float> [[D]], ptr [[OUT_PTR]], align 16
; CHECK-NEXT: ret void
;

3
llvm/test/Transforms/InstCombine/trunc-extractelement.ll
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@ -182,7 +182,8 @@ define <4 x i64> @PR45314(<4 x i64> %x) {
;
; BE-LABEL: @PR45314(
; BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32>
; BE-NEXT: [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; BE-NEXT: [[I:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; BE-NEXT: [[S:%.*]] = shufflevector <8 x i32> [[I]], <8 x i32> undef, <8 x i32> zeroinitializer
; BE-NEXT: [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64>
; BE-NEXT: ret <4 x i64> [[B]]
;

13
llvm/test/Transforms/InstCombine/vec_shuffle.ll
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@ -108,7 +108,8 @@ define <4 x float> @test8(<4 x float> %x, <4 x float> %y) {
; different length then the second.
define <4 x i8> @test9(<16 x i8> %t6) {
; CHECK-LABEL: @test9(
; CHECK-NEXT: [[T9:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> undef, <4 x i32> <i32 13, i32 9, i32 4, i32 13>
; CHECK-NEXT: [[T7:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> undef, <4 x i32> <i32 13, i32 9, i32 4, i32 13>
; CHECK-NEXT: [[T9:%.*]] = shufflevector <4 x i8> [[T7]], <4 x i8> undef, <4 x i32> <i32 3, i32 1, i32 2, i32 0>
; CHECK-NEXT: ret <4 x i8> [[T9]]
;
%t7 = shufflevector <16 x i8> %t6, <16 x i8> undef, <4 x i32> < i32 13, i32 9, i32 4, i32 13 >
@ -135,7 +136,8 @@ define <4 x i8> @test9a(<16 x i8> %t6) {
; different length then the second.
define <4 x i8> @test9b(<4 x i8> %t6, <4 x i8> %t7) {
; CHECK-LABEL: @test9b(
; CHECK-NEXT: [[T9:%.*]] = shufflevector <4 x i8> [[T6:%.*]], <4 x i8> [[T7:%.*]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: [[T1:%.*]] = shufflevector <4 x i8> [[T6:%.*]], <4 x i8> [[T7:%.*]], <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 4, i32 5, i32 poison, i32 poison>
; CHECK-NEXT: [[T9:%.*]] = shufflevector <8 x i8> [[T1]], <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: ret <4 x i8> [[T9]]
;
%t1 = shufflevector <4 x i8> %t6, <4 x i8> %t7, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4, i32 5, i32 2, i32 3>
@ -146,7 +148,8 @@ define <4 x i8> @test9b(<4 x i8> %t6, <4 x i8> %t7) {
; Redundant vector splats should be removed. Radar 8597790.
define <4 x i32> @test10(<4 x i32> %t5) {
; CHECK-LABEL: @test10(
; CHECK-NEXT: [[T7:%.*]] = shufflevector <4 x i32> [[T5:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x i32> [[T5:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[T7:%.*]] = shufflevector <4 x i32> [[T6]], <4 x i32> undef, <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x i32> [[T7]]
;
%t6 = shufflevector <4 x i32> %t5, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
@ -158,7 +161,9 @@ define <4 x i32> @test10(<4 x i32> %t5) {
define <8 x i8> @test11(<16 x i8> %t6) {
; CHECK-LABEL: @test11(
; CHECK-NEXT: [[T3:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[T1:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[T2:%.*]] = shufflevector <16 x i8> [[T6]], <16 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i8> [[T1]], <4 x i8> [[T2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: ret <8 x i8> [[T3]]
;
%t1 = shufflevector <16 x i8> %t6, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>