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[FastISel] Use Register. NFC

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This commit is contained in:
Craig Topper 2025-03-02 10:24:47 -08:00
parent 3a11d5a8df
commit 6d847b1aad
3 changed files with 34 additions and 35 deletions
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32
llvm/include/llvm/CodeGen/FastISel.h
View File

@ -352,17 +352,17 @@ protected:
/// This method is called by target-independent code to request that an
/// instruction with the given type, opcode, and register operand be emitted.
virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0);
virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0);
/// This method is called by target-independent code to request that an
/// instruction with the given type, opcode, and register operands be emitted.
virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
unsigned Op1);
virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
Register Op1);
/// This method is called by target-independent code to request that an
/// instruction with the given type, opcode, and register and immediate
/// operands be emitted.
virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0,
uint64_t Imm);
/// This method is a wrapper of fastEmit_ri.
@ -370,7 +370,7 @@ protected:
/// It first tries to emit an instruction with an immediate operand using
/// fastEmit_ri. If that fails, it materializes the immediate into a register
/// and try fastEmit_rr instead.
Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, uint64_t Imm,
Register fastEmit_ri_(MVT VT, unsigned Opcode, Register Op0, uint64_t Imm,
MVT ImmType);
/// This method is called by target-independent code to request that an
@ -391,30 +391,30 @@ protected:
/// Emit a MachineInstr with one register operand and a result register
/// in the given register class.
Register fastEmitInst_r(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0);
const TargetRegisterClass *RC, Register Op0);
/// Emit a MachineInstr with two register operands and a result
/// register in the given register class.
Register fastEmitInst_rr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0,
unsigned Op1);
const TargetRegisterClass *RC, Register Op0,
Register Op1);
/// Emit a MachineInstr with three register operands and a result
/// register in the given register class.
Register fastEmitInst_rrr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0,
unsigned Op1, unsigned Op2);
const TargetRegisterClass *RC, Register Op0,
Register Op1, Register Op2);
/// Emit a MachineInstr with a register operand, an immediate, and a
/// result register in the given register class.
Register fastEmitInst_ri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0,
const TargetRegisterClass *RC, Register Op0,
uint64_t Imm);
/// Emit a MachineInstr with one register operand and two immediate
/// operands.
Register fastEmitInst_rii(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0,
const TargetRegisterClass *RC, Register Op0,
uint64_t Imm1, uint64_t Imm2);
/// Emit a MachineInstr with a floating point immediate, and a result
@ -426,8 +426,8 @@ protected:
/// Emit a MachineInstr with two register operands, an immediate, and a
/// result register in the given register class.
Register fastEmitInst_rri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0,
unsigned Op1, uint64_t Imm);
const TargetRegisterClass *RC, Register Op0,
Register Op1, uint64_t Imm);
/// Emit a MachineInstr with a single immediate operand, and a result
/// register in the given register class.
@ -436,11 +436,11 @@ protected:
/// Emit a MachineInstr for an extract_subreg from a specified index of
/// a superregister to a specified type.
Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, uint32_t Idx);
Register fastEmitInst_extractsubreg(MVT RetVT, Register Op0, uint32_t Idx);
/// Emit MachineInstrs to compute the value of Op with all but the
/// least significant bit set to zero.
Register fastEmitZExtFromI1(MVT VT, unsigned Op0);
Register fastEmitZExtFromI1(MVT VT, Register Op0);
/// Emit an unconditional branch to the given block, unless it is the
/// immediate (fall-through) successor, and update the CFG.

35
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@ -1951,12 +1951,12 @@ bool FastISel::fastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/) {
unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, Register /*Op0*/) {
return 0;
}
unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
unsigned /*Op1*/) {
unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, Register /*Op0*/,
Register /*Op1*/) {
return 0;
}
@ -1969,7 +1969,7 @@ unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
return 0;
}
unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, Register /*Op0*/,
uint64_t /*Imm*/) {
return 0;
}
@ -1978,7 +1978,7 @@ unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
/// instruction with an immediate operand using fastEmit_ri.
/// If that fails, it materializes the immediate into a register and try
/// fastEmit_rr instead.
Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, Register Op0,
uint64_t Imm, MVT ImmType) {
// If this is a multiply by a power of two, emit this as a shift left.
if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
@ -2044,7 +2044,7 @@ Register FastISel::fastEmitInst_(unsigned MachineInstOpcode,
}
Register FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0) {
const TargetRegisterClass *RC, Register Op0) {
const MCInstrDesc &II = TII.get(MachineInstOpcode);
Register ResultReg = createResultReg(RC);
@ -2065,8 +2065,8 @@ Register FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
}
Register FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0,
unsigned Op1) {
const TargetRegisterClass *RC, Register Op0,
Register Op1) {
const MCInstrDesc &II = TII.get(MachineInstOpcode);
Register ResultReg = createResultReg(RC);
@ -2089,8 +2089,8 @@ Register FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
}
Register FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0,
unsigned Op1, unsigned Op2) {
const TargetRegisterClass *RC, Register Op0,
Register Op1, Register Op2) {
const MCInstrDesc &II = TII.get(MachineInstOpcode);
Register ResultReg = createResultReg(RC);
@ -2116,7 +2116,7 @@ Register FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
}
Register FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0,
const TargetRegisterClass *RC, Register Op0,
uint64_t Imm) {
const MCInstrDesc &II = TII.get(MachineInstOpcode);
@ -2139,7 +2139,7 @@ Register FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
}
Register FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0,
const TargetRegisterClass *RC, Register Op0,
uint64_t Imm1, uint64_t Imm2) {
const MCInstrDesc &II = TII.get(MachineInstOpcode);
@ -2184,8 +2184,8 @@ Register FastISel::fastEmitInst_f(unsigned MachineInstOpcode,
}
Register FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
const TargetRegisterClass *RC, unsigned Op0,
unsigned Op1, uint64_t Imm) {
const TargetRegisterClass *RC, Register Op0,
Register Op1, uint64_t Imm) {
const MCInstrDesc &II = TII.get(MachineInstOpcode);
Register ResultReg = createResultReg(RC);
@ -2226,11 +2226,10 @@ Register FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
return ResultReg;
}
Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, Register Op0,
uint32_t Idx) {
Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
assert(Register::isVirtualRegister(Op0) &&
"Cannot yet extract from physregs");
assert(Op0.isVirtual() && "Cannot yet extract from physregs");
const TargetRegisterClass *RC = MRI.getRegClass(Op0);
MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
@ -2240,7 +2239,7 @@ Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
/// Emit MachineInstrs to compute the value of Op with all but the least
/// significant bit set to zero.
Register FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0) {
Register FastISel::fastEmitZExtFromI1(MVT VT, Register Op0) {
return fastEmit_ri(VT, VT, ISD::AND, Op0, 1);
}

2
llvm/utils/TableGen/FastISelEmitter.cpp
View File

@ -306,7 +306,7 @@ struct OperandsSignature {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
OS << LS;
if (Operands[i].isReg()) {
OS << "unsigned Op" << i;
OS << "Register Op" << i;
} else if (Operands[i].isImm()) {
OS << "uint64_t imm" << i;
} else if (Operands[i].isFP()) {