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Revert rG58de1e2c5eee548a9b365e3b1554d87317072ad9 "Fix stack layout for frames larger than 2gb (#84114)"

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This is failing on some EXPENSIVE_CHECKS buildbots
This commit is contained in:
Simon Pilgrim 2024-03-27 16:16:15 +00:00
parent 313bf28f98
commit 78f0871bee
21 changed files with 86 additions and 116 deletions
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14
llvm/include/llvm/CodeGen/MachineFrameInfo.h
View File

@ -251,7 +251,7 @@ private:
/// targets, this value is only used when generating debug info (via
/// TargetRegisterInfo::getFrameIndexReference); when generating code, the
/// corresponding adjustments are performed directly.
int64_t OffsetAdjustment = 0;
int OffsetAdjustment = 0;
/// The prolog/epilog code inserter may process objects that require greater
/// alignment than the default alignment the target provides.
@ -280,7 +280,7 @@ private:
/// setup/destroy pseudo instructions (as defined in the TargetFrameInfo
/// class). This information is important for frame pointer elimination.
/// It is only valid during and after prolog/epilog code insertion.
uint64_t MaxCallFrameSize = ~UINT64_C(0);
unsigned MaxCallFrameSize = ~0u;
/// The number of bytes of callee saved registers that the target wants to
/// report for the current function in the CodeView S_FRAMEPROC record.
@ -591,10 +591,10 @@ public:
uint64_t estimateStackSize(const MachineFunction &MF) const;
/// Return the correction for frame offsets.
int64_t getOffsetAdjustment() const { return OffsetAdjustment; }
int getOffsetAdjustment() const { return OffsetAdjustment; }
/// Set the correction for frame offsets.
void setOffsetAdjustment(int64_t Adj) { OffsetAdjustment = Adj; }
void setOffsetAdjustment(int Adj) { OffsetAdjustment = Adj; }
/// Return the alignment in bytes that this function must be aligned to,
/// which is greater than the default stack alignment provided by the target.
@ -655,7 +655,7 @@ public:
/// CallFrameSetup/Destroy pseudo instructions are used by the target, and
/// then only during or after prolog/epilog code insertion.
///
uint64_t getMaxCallFrameSize() const {
unsigned getMaxCallFrameSize() const {
// TODO: Enable this assert when targets are fixed.
//assert(isMaxCallFrameSizeComputed() && "MaxCallFrameSize not computed yet");
if (!isMaxCallFrameSizeComputed())
@ -663,9 +663,9 @@ public:
return MaxCallFrameSize;
}
bool isMaxCallFrameSizeComputed() const {
return MaxCallFrameSize != ~UINT64_C(0);
return MaxCallFrameSize != ~0u;
}
void setMaxCallFrameSize(uint64_t S) { MaxCallFrameSize = S; }
void setMaxCallFrameSize(unsigned S) { MaxCallFrameSize = S; }
/// Returns how many bytes of callee-saved registers the target pushed in the
/// prologue. Only used for debug info.

4
llvm/include/llvm/CodeGen/TargetFrameLowering.h
View File

@ -51,7 +51,7 @@ public:
// Maps a callee saved register to a stack slot with a fixed offset.
struct SpillSlot {
unsigned Reg;
int64_t Offset; // Offset relative to stack pointer on function entry.
int Offset; // Offset relative to stack pointer on function entry.
};
struct DwarfFrameBase {
@ -66,7 +66,7 @@ public:
// Used with FrameBaseKind::Register.
unsigned Reg;
// Used with FrameBaseKind::CFA.
int64_t Offset;
int Offset;
struct WasmFrameBase WasmLoc;
} Location;
};

2
llvm/include/llvm/MC/MCAsmBackend.h
View File

@ -232,7 +232,7 @@ public:
virtual void handleAssemblerFlag(MCAssemblerFlag Flag) {}
/// Generate the compact unwind encoding for the CFI instructions.
virtual uint64_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
virtual uint32_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
const MCContext *Ctxt) const {
return 0;
}

40
llvm/include/llvm/MC/MCDwarf.h
View File

@ -508,7 +508,7 @@ private:
MCSymbol *Label;
unsigned Register;
union {
int64_t Offset;
int Offset;
unsigned Register2;
};
unsigned AddressSpace = ~0u;
@ -516,7 +516,7 @@ private:
std::vector<char> Values;
std::string Comment;
MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int64_t O, SMLoc Loc,
MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int O, SMLoc Loc,
StringRef V = "", StringRef Comment = "")
: Operation(Op), Label(L), Register(R), Offset(O), Loc(Loc),
Values(V.begin(), V.end()), Comment(Comment) {
@ -528,7 +528,7 @@ private:
assert(Op == OpRegister);
}
MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int64_t O, unsigned AS,
MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int O, unsigned AS,
SMLoc Loc)
: Operation(Op), Label(L), Register(R), Offset(O), AddressSpace(AS),
Loc(Loc) {
@ -538,8 +538,8 @@ private:
public:
/// .cfi_def_cfa defines a rule for computing CFA as: take address from
/// Register and add Offset to it.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register,
int64_t Offset, SMLoc Loc = {}) {
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset,
SMLoc Loc = {}) {
return MCCFIInstruction(OpDefCfa, L, Register, Offset, Loc);
}
@ -547,13 +547,13 @@ public:
/// on Register will be used instead of the old one. Offset remains the same.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register,
SMLoc Loc = {}) {
return MCCFIInstruction(OpDefCfaRegister, L, Register, INT64_C(0), Loc);
return MCCFIInstruction(OpDefCfaRegister, L, Register, 0, Loc);
}
/// .cfi_def_cfa_offset modifies a rule for computing CFA. Register
/// remains the same, but offset is new. Note that it is the absolute offset
/// that will be added to a defined register to the compute CFA address.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset,
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset,
SMLoc Loc = {}) {
return MCCFIInstruction(OpDefCfaOffset, L, 0, Offset, Loc);
}
@ -561,7 +561,7 @@ public:
/// .cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but
/// Offset is a relative value that is added/subtracted from the previous
/// offset.
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment,
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment,
SMLoc Loc = {}) {
return MCCFIInstruction(OpAdjustCfaOffset, L, 0, Adjustment, Loc);
}
@ -581,7 +581,7 @@ public:
/// .cfi_offset Previous value of Register is saved at offset Offset
/// from CFA.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register,
int64_t Offset, SMLoc Loc = {}) {
int Offset, SMLoc Loc = {}) {
return MCCFIInstruction(OpOffset, L, Register, Offset, Loc);
}
@ -589,7 +589,7 @@ public:
/// Offset from the current CFA register. This is transformed to .cfi_offset
/// using the known displacement of the CFA register from the CFA.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register,
int64_t Offset, SMLoc Loc = {}) {
int Offset, SMLoc Loc = {}) {
return MCCFIInstruction(OpRelOffset, L, Register, Offset, Loc);
}
@ -602,12 +602,12 @@ public:
/// .cfi_window_save SPARC register window is saved.
static MCCFIInstruction createWindowSave(MCSymbol *L, SMLoc Loc = {}) {
return MCCFIInstruction(OpWindowSave, L, 0, INT64_C(0), Loc);
return MCCFIInstruction(OpWindowSave, L, 0, 0, Loc);
}
/// .cfi_negate_ra_state AArch64 negate RA state.
static MCCFIInstruction createNegateRAState(MCSymbol *L, SMLoc Loc = {}) {
return MCCFIInstruction(OpNegateRAState, L, 0, INT64_C(0), Loc);
return MCCFIInstruction(OpNegateRAState, L, 0, 0, Loc);
}
/// .cfi_restore says that the rule for Register is now the same as it
@ -615,31 +615,31 @@ public:
/// by .cfi_startproc were executed.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register,
SMLoc Loc = {}) {
return MCCFIInstruction(OpRestore, L, Register, INT64_C(0), Loc);
return MCCFIInstruction(OpRestore, L, Register, 0, Loc);
}
/// .cfi_undefined From now on the previous value of Register can't be
/// restored anymore.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register,
SMLoc Loc = {}) {
return MCCFIInstruction(OpUndefined, L, Register, INT64_C(0), Loc);
return MCCFIInstruction(OpUndefined, L, Register, 0, Loc);
}
/// .cfi_same_value Current value of Register is the same as in the
/// previous frame. I.e., no restoration is needed.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register,
SMLoc Loc = {}) {
return MCCFIInstruction(OpSameValue, L, Register, INT64_C(0), Loc);
return MCCFIInstruction(OpSameValue, L, Register, 0, Loc);
}
/// .cfi_remember_state Save all current rules for all registers.
static MCCFIInstruction createRememberState(MCSymbol *L, SMLoc Loc = {}) {
return MCCFIInstruction(OpRememberState, L, 0, INT64_C(0), Loc);
return MCCFIInstruction(OpRememberState, L, 0, 0, Loc);
}
/// .cfi_restore_state Restore the previously saved state.
static MCCFIInstruction createRestoreState(MCSymbol *L, SMLoc Loc = {}) {
return MCCFIInstruction(OpRestoreState, L, 0, INT64_C(0), Loc);
return MCCFIInstruction(OpRestoreState, L, 0, 0, Loc);
}
/// .cfi_escape Allows the user to add arbitrary bytes to the unwind
@ -650,7 +650,7 @@ public:
}
/// A special wrapper for .cfi_escape that indicates GNU_ARGS_SIZE
static MCCFIInstruction createGnuArgsSize(MCSymbol *L, int64_t Size,
static MCCFIInstruction createGnuArgsSize(MCSymbol *L, int Size,
SMLoc Loc = {}) {
return MCCFIInstruction(OpGnuArgsSize, L, 0, Size, Loc);
}
@ -677,7 +677,7 @@ public:
return AddressSpace;
}
int64_t getOffset() const {
int getOffset() const {
assert(Operation == OpDefCfa || Operation == OpOffset ||
Operation == OpRelOffset || Operation == OpDefCfaOffset ||
Operation == OpAdjustCfaOffset || Operation == OpGnuArgsSize ||
@ -705,7 +705,7 @@ struct MCDwarfFrameInfo {
unsigned CurrentCfaRegister = 0;
unsigned PersonalityEncoding = 0;
unsigned LsdaEncoding = 0;
uint64_t CompactUnwindEncoding = 0;
uint32_t CompactUnwindEncoding = 0;
bool IsSignalFrame = false;
bool IsSimple = false;
unsigned RAReg = static_cast<unsigned>(INT_MAX);

10
llvm/lib/CodeGen/CFIInstrInserter.cpp
View File

@ -68,9 +68,9 @@ class CFIInstrInserter : public MachineFunctionPass {
struct MBBCFAInfo {
MachineBasicBlock *MBB;
/// Value of cfa offset valid at basic block entry.
int64_t IncomingCFAOffset = -1;
int IncomingCFAOffset = -1;
/// Value of cfa offset valid at basic block exit.
int64_t OutgoingCFAOffset = -1;
int OutgoingCFAOffset = -1;
/// Value of cfa register valid at basic block entry.
unsigned IncomingCFARegister = 0;
/// Value of cfa register valid at basic block exit.
@ -120,7 +120,7 @@ class CFIInstrInserter : public MachineFunctionPass {
/// Return the cfa offset value that should be set at the beginning of a MBB
/// if needed. The negated value is needed when creating CFI instructions that
/// set absolute offset.
int64_t getCorrectCFAOffset(MachineBasicBlock *MBB) {
int getCorrectCFAOffset(MachineBasicBlock *MBB) {
return MBBVector[MBB->getNumber()].IncomingCFAOffset;
}
@ -175,7 +175,7 @@ void CFIInstrInserter::calculateCFAInfo(MachineFunction &MF) {
void CFIInstrInserter::calculateOutgoingCFAInfo(MBBCFAInfo &MBBInfo) {
// Outgoing cfa offset set by the block.
int64_t SetOffset = MBBInfo.IncomingCFAOffset;
int SetOffset = MBBInfo.IncomingCFAOffset;
// Outgoing cfa register set by the block.
unsigned SetRegister = MBBInfo.IncomingCFARegister;
MachineFunction *MF = MBBInfo.MBB->getParent();
@ -188,7 +188,7 @@ void CFIInstrInserter::calculateOutgoingCFAInfo(MBBCFAInfo &MBBInfo) {
for (MachineInstr &MI : *MBBInfo.MBB) {
if (MI.isCFIInstruction()) {
std::optional<unsigned> CSRReg;
std::optional<int64_t> CSROffset;
std::optional<int> CSROffset;
unsigned CFIIndex = MI.getOperand(0).getCFIIndex();
const MCCFIInstruction &CFI = Instrs[CFIIndex];
switch (CFI.getOperation()) {

2
llvm/lib/CodeGen/MachineFrameInfo.cpp
View File

@ -197,7 +197,7 @@ void MachineFrameInfo::computeMaxCallFrameSize(
for (MachineInstr &MI : MBB) {
unsigned Opcode = MI.getOpcode();
if (Opcode == FrameSetupOpcode || Opcode == FrameDestroyOpcode) {
uint64_t Size = TII.getFrameSize(MI);
unsigned Size = TII.getFrameSize(MI);
MaxCallFrameSize = std::max(MaxCallFrameSize, Size);
if (FrameSDOps != nullptr)
FrameSDOps->push_back(&MI);

4
llvm/lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -366,8 +366,8 @@ void PEI::calculateCallFrameInfo(MachineFunction &MF) {
return;
// (Re-)Compute the MaxCallFrameSize.
[[maybe_unused]] uint64_t MaxCFSIn =
MFI.isMaxCallFrameSizeComputed() ? MFI.getMaxCallFrameSize() : UINT64_MAX;
[[maybe_unused]] uint32_t MaxCFSIn =
MFI.isMaxCallFrameSizeComputed() ? MFI.getMaxCallFrameSize() : UINT32_MAX;
std::vector<MachineBasicBlock::iterator> FrameSDOps;
MFI.computeMaxCallFrameSize(MF, &FrameSDOps);
assert(MFI.getMaxCallFrameSize() <= MaxCFSIn &&

6
llvm/lib/MC/MCDwarf.cpp
View File

@ -1298,8 +1298,8 @@ static void EmitPersonality(MCStreamer &streamer, const MCSymbol &symbol,
namespace {
class FrameEmitterImpl {
int64_t CFAOffset = 0;
int64_t InitialCFAOffset = 0;
int CFAOffset = 0;
int InitialCFAOffset = 0;
bool IsEH;
MCObjectStreamer &Streamer;
@ -1413,7 +1413,7 @@ void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) {
if (!IsEH)
Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg);
int64_t Offset = Instr.getOffset();
int Offset = Instr.getOffset();
if (IsRelative)
Offset -= CFAOffset;
Offset = Offset / dataAlignmentFactor;

10
llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
View File

@ -584,7 +584,7 @@ class DarwinAArch64AsmBackend : public AArch64AsmBackend {
/// Encode compact unwind stack adjustment for frameless functions.
/// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
/// The stack size always needs to be 16 byte aligned.
uint64_t encodeStackAdjustment(uint64_t StackSize) const {
uint32_t encodeStackAdjustment(uint32_t StackSize) const {
return (StackSize / 16) << 12;
}
@ -602,7 +602,7 @@ public:
}
/// Generate the compact unwind encoding from the CFI directives.
uint64_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
uint32_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
const MCContext *Ctxt) const override {
ArrayRef<MCCFIInstruction> Instrs = FI->Instructions;
if (Instrs.empty())
@ -612,10 +612,10 @@ public:
return CU::UNWIND_ARM64_MODE_DWARF;
bool HasFP = false;
uint64_t StackSize = 0;
unsigned StackSize = 0;
uint64_t CompactUnwindEncoding = 0;
int64_t CurOffset = 0;
uint32_t CompactUnwindEncoding = 0;
int CurOffset = 0;
for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
const MCCFIInstruction &Inst = Instrs[i];

4
llvm/lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -1165,7 +1165,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
if (STI.splitFramePushPop(MF)) {
unsigned DwarfReg = MRI->getDwarfRegNum(
Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg, true);
uint64_t Offset = MFI.getObjectOffset(FI);
unsigned Offset = MFI.getObjectOffset(FI);
unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
@ -1187,7 +1187,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
(Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
uint64_t Offset = MFI.getObjectOffset(FI);
unsigned Offset = MFI.getObjectOffset(FI);
unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))

2
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
View File

@ -1148,7 +1148,7 @@ enum CompactUnwindEncodings {
/// instructions. If the CFI instructions describe a frame that cannot be
/// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
/// tells the runtime to fallback and unwind using dwarf.
uint64_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
const MCDwarfFrameInfo *FI, const MCContext *Ctxt) const {
DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n");
// Only armv7k uses CFI based unwinding.

2
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
View File

@ -34,7 +34,7 @@ public:
/*Is64Bit=*/false, cantFail(MachO::getCPUType(TT)), Subtype);
}
uint64_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
uint32_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
const MCContext *Ctxt) const override;
};
} // end namespace llvm

4
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
View File

@ -1660,7 +1660,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
using SpillSlot = TargetFrameLowering::SpillSlot;
unsigned NumFixed;
int64_t MinOffset = 0; // CS offsets are negative.
int MinOffset = 0; // CS offsets are negative.
const SpillSlot *FixedSlots = getCalleeSavedSpillSlots(NumFixed);
for (const SpillSlot *S = FixedSlots; S != FixedSlots+NumFixed; ++S) {
if (!SRegs[S->Reg])
@ -1679,7 +1679,7 @@ bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
Register R = x;
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
unsigned Size = TRI->getSpillSize(*RC);
int64_t Off = MinOffset - Size;
int Off = MinOffset - Size;
Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign());
Off &= -Alignment.value();
int FI = MFI.CreateFixedSpillStackObject(Size, Off);

2
llvm/lib/Target/MSP430/MSP430FrameLowering.cpp
View File

@ -294,7 +294,7 @@ void MSP430FrameLowering::emitEpilogue(MachineFunction &MF,
if (!hasFP(MF)) {
MBBI = FirstCSPop;
int64_t Offset = -(int64_t)CSSize - 2;
int64_t Offset = -CSSize - 2;
// Mark callee-saved pop instruction.
// Define the current CFA rule to use the provided offset.
while (MBBI != MBB.end()) {

13
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
View File

@ -1328,7 +1328,7 @@ public:
/// Implementation of algorithm to generate the compact unwind encoding
/// for the CFI instructions.
uint64_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
uint32_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI,
const MCContext *Ctxt) const override {
ArrayRef<MCCFIInstruction> Instrs = FI->Instructions;
if (Instrs.empty()) return 0;
@ -1343,13 +1343,13 @@ public:
bool HasFP = false;
// Encode that we are using EBP/RBP as the frame pointer.
uint64_t CompactUnwindEncoding = 0;
uint32_t CompactUnwindEncoding = 0;
unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
unsigned InstrOffset = 0;
unsigned StackAdjust = 0;
uint64_t StackSize = 0;
int64_t MinAbsOffset = std::numeric_limits<int64_t>::max();
unsigned StackSize = 0;
int MinAbsOffset = std::numeric_limits<int>::max();
for (const MCCFIInstruction &Inst : Instrs) {
switch (Inst.getOperation()) {
@ -1376,7 +1376,7 @@ public:
memset(SavedRegs, 0, sizeof(SavedRegs));
StackAdjust = 0;
SavedRegIdx = 0;
MinAbsOffset = std::numeric_limits<int64_t>::max();
MinAbsOffset = std::numeric_limits<int>::max();
InstrOffset += MoveInstrSize;
break;
}
@ -1419,8 +1419,7 @@ public:
unsigned Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true);
SavedRegs[SavedRegIdx++] = Reg;
StackAdjust += OffsetSize;
MinAbsOffset =
std::min<int64_t>(MinAbsOffset, std::abs(Inst.getOffset()));
MinAbsOffset = std::min(MinAbsOffset, abs(Inst.getOffset()));
InstrOffset += PushInstrSize(Reg);
break;
}

14
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -358,8 +358,7 @@ private:
void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
MCFixupKind FixupKind, uint64_t StartByte,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
int64_t ImmOffset = 0) const;
SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
SmallVectorImpl<char> &CB) const;
@ -413,8 +412,7 @@ static void emitConstant(uint64_t Val, unsigned Size,
/// Determine if this immediate can fit in a disp8 or a compressed disp8 for
/// EVEX instructions. \p will be set to the value to pass to the ImmOffset
/// parameter of emitImmediate.
static bool isDispOrCDisp8(uint64_t TSFlags, int64_t Value,
int64_t &ImmOffset) {
static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) {
bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
unsigned CD8_Scale =
@ -427,7 +425,7 @@ static bool isDispOrCDisp8(uint64_t TSFlags, int64_t Value,
if (Value & (CD8_Scale - 1)) // Unaligned offset
return false;
int64_t CDisp8 = Value / static_cast<int64_t>(CD8_Scale);
int CDisp8 = Value / static_cast<int>(CD8_Scale);
if (!isInt<8>(CDisp8))
return false;
@ -520,7 +518,7 @@ void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
uint64_t StartByte,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
int64_t ImmOffset) const {
int ImmOffset) const {
const MCExpr *Expr = nullptr;
if (DispOp.isImm()) {
// If this is a simple integer displacement that doesn't require a
@ -801,7 +799,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
// This also handles the 0 displacement for [EBP], [R13], [R21] or [R29]. We
// can't use disp8 if the {disp32} pseudo prefix is present.
if (Disp.isImm() && AllowDisp8) {
int64_t ImmOffset = 0;
int ImmOffset = 0;
if (isDispOrCDisp8(TSFlags, Disp.getImm(), ImmOffset)) {
emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CB);
emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, CB, Fixups,
@ -828,7 +826,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
bool ForceDisp32 = false;
bool ForceDisp8 = false;
int64_t ImmOffset = 0;
int ImmOffset = 0;
if (BaseReg == 0) {
// If there is no base register, we emit the special case SIB byte with
// MOD=0, BASE=5, to JUST get the index, scale, and displacement.

28
llvm/lib/Target/X86/X86FrameLowering.cpp
View File

@ -380,9 +380,9 @@ MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
return MI;
}
int64_t X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
bool doMergeWithPrevious) const {
int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
bool doMergeWithPrevious) const {
if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
(!doMergeWithPrevious && MBBI == MBB.end()))
return 0;
@ -405,7 +405,7 @@ int64_t X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
PI = std::prev(PI);
unsigned Opc = PI->getOpcode();
int64_t Offset = 0;
int Offset = 0;
if ((Opc == X86::ADD64ri32 || Opc == X86::ADD32ri) &&
PI->getOperand(0).getReg() == StackPtr) {
@ -473,7 +473,7 @@ void X86FrameLowering::emitCalleeSavedFrameMovesFullCFA(
: FramePtr;
unsigned DwarfReg = MRI->getDwarfRegNum(MachineFramePtr, true);
// Offset = space for return address + size of the frame pointer itself.
int64_t Offset = (Is64Bit ? 8 : 4) + (Uses64BitFramePtr ? 8 : 4);
unsigned Offset = (Is64Bit ? 8 : 4) + (Uses64BitFramePtr ? 8 : 4);
BuildCFI(MBB, MBBI, DebugLoc{},
MCCFIInstruction::createOffset(nullptr, DwarfReg, -Offset));
emitCalleeSavedFrameMoves(MBB, MBBI, DebugLoc{}, true);
@ -1881,7 +1881,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
// For EH funclets, only allocate enough space for outgoing calls. Save the
// NumBytes value that we would've used for the parent frame.
uint64_t ParentFrameNumBytes = NumBytes;
unsigned ParentFrameNumBytes = NumBytes;
if (IsFunclet)
NumBytes = getWinEHFuncletFrameSize(MF);
@ -2430,7 +2430,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
if (HasFP) {
if (X86FI->hasSwiftAsyncContext()) {
// Discard the context.
int64_t Offset = 16 + mergeSPUpdates(MBB, MBBI, true);
int Offset = 16 + mergeSPUpdates(MBB, MBBI, true);
emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue*/ true);
}
// Pop EBP.
@ -2562,7 +2562,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
if (!HasFP && NeedsDwarfCFI) {
MBBI = FirstCSPop;
int64_t Offset = -(int64_t)CSSize - SlotSize;
int64_t Offset = -CSSize - SlotSize;
// Mark callee-saved pop instruction.
// Define the current CFA rule to use the provided offset.
while (MBBI != MBB.end()) {
@ -2591,7 +2591,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
// Add the return addr area delta back since we are not tail calling.
int64_t Offset = -1 * X86FI->getTCReturnAddrDelta();
int Offset = -1 * X86FI->getTCReturnAddrDelta();
assert(Offset >= 0 && "TCDelta should never be positive");
if (Offset) {
// Check for possible merge with preceding ADD instruction.
@ -2625,7 +2625,7 @@ StackOffset X86FrameLowering::getFrameIndexReference(const MachineFunction &MF,
// object.
// We need to factor in additional offsets applied during the prologue to the
// frame, base, and stack pointer depending on which is used.
int64_t Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
unsigned CSSize = X86FI->getCalleeSavedFrameSize();
uint64_t StackSize = MFI.getStackSize();
@ -3919,7 +3919,7 @@ MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHStackPointers(
// FIXME: Don't set FrameSetup flag in catchret case.
int FI = FuncInfo.EHRegNodeFrameIndex;
int64_t EHRegSize = MFI.getObjectSize(FI);
int EHRegSize = MFI.getObjectSize(FI);
if (RestoreSP) {
// MOV32rm -EHRegSize(%ebp), %esp
@ -3929,8 +3929,8 @@ MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHStackPointers(
}
Register UsedReg;
int64_t EHRegOffset = getFrameIndexReference(MF, FI, UsedReg).getFixed();
int64_t EndOffset = -EHRegOffset - EHRegSize;
int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg).getFixed();
int EndOffset = -EHRegOffset - EHRegSize;
FuncInfo.EHRegNodeEndOffset = EndOffset;
if (UsedReg == FramePtr) {
@ -3951,7 +3951,7 @@ MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHStackPointers(
.setMIFlag(MachineInstr::FrameSetup);
// MOV32rm SavedEBPOffset(%esi), %ebp
assert(X86FI->getHasSEHFramePtrSave());
int64_t Offset =
int Offset =
getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg)
.getFixed();
assert(UsedReg == BasePtr);

5
llvm/lib/Target/X86/X86FrameLowering.h
View File

@ -137,9 +137,8 @@ public:
/// it is an ADD/SUB/LEA instruction it is deleted argument and the
/// stack adjustment is returned as a positive value for ADD/LEA and
/// a negative for SUB.
int64_t mergeSPUpdates(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
bool doMergeWithPrevious) const;
int mergeSPUpdates(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
bool doMergeWithPrevious) const;
/// Emit a series of instructions to increment / decrement the stack
/// pointer by a constant value.

10
llvm/lib/Target/X86/X86RegisterInfo.cpp
View File

@ -893,7 +893,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
// Determine base register and offset.
int64_t FIOffset;
int FIOffset;
Register BasePtr;
if (MI.isReturn()) {
assert((!hasStackRealignment(MF) ||
@ -946,11 +946,9 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (MI.getOperand(FIOperandNum+3).isImm()) {
// Offset is a 32-bit integer.
int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
int64_t Offset = FIOffset + Imm;
if (!Is64Bit) {
assert(isInt<32>((long long)FIOffset + Imm) &&
"Requesting 64-bit offset in 32-bit immediate!");
}
int Offset = FIOffset + Imm;
assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
"Requesting 64-bit offset in 32-bit immediate!");
if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
} else {

2
llvm/test/CodeGen/PowerPC/huge-frame-size.ll
View File

@ -18,7 +18,7 @@ define void @foo(i8 %x) {
; CHECK-LE-NEXT: oris 0, 0, 65535
; CHECK-LE-NEXT: ori 0, 0, 65504
; CHECK-LE-NEXT: stdux 1, 1, 0
; CHECK-LE-NEXT: .cfi_def_cfa_offset 4294967328
; CHECK-LE-NEXT: .cfi_def_cfa_offset 32
; CHECK-LE-NEXT: li 4, 1
; CHECK-LE-NEXT: addi 5, 1, 32
; CHECK-LE-NEXT: stb 3, 32(1)

24
llvm/test/CodeGen/X86/huge-stack.ll
View File

@ -1,24 +0,0 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp --version 4
; RUN: llc -O0 -mtriple=x86_64 < %s | FileCheck %s --check-prefix=CHECK
%large = type [4294967295 x i8]
define void @foo() unnamed_addr #0 {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movabsq $8589934462, %rax # imm = 0x1FFFFFF7E
; CHECK-NEXT: subq %rax, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8589934470
; CHECK-NEXT: movb $42, 4294967167(%rsp)
; CHECK-NEXT: movb $43, -128(%rsp)
; CHECK-NEXT: movabsq $8589934462, %rax # imm = 0x1FFFFFF7E
; CHECK-NEXT: addq %rax, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
%1 = alloca %large, align 1
%2 = alloca %large, align 1
%3 = getelementptr inbounds %large, ptr %1, i64 0, i64 0
store i8 42, ptr %3, align 1
%4 = getelementptr inbounds %large, ptr %2, i64 0, i64 0
store i8 43, ptr %4, align 1
ret void
}