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[FMV] Remove feature dgh. (#115363)
It belongs to the HINT space so it can be executed as NOP if the hardware doesn't support it. Reviewed in ACLE -> https://github.com/ARM-software/acle/pull/357
This commit is contained in:
Alexandros Lamprineas
GitHub
parent
ffe49b7bcf
commit
799e520c51
@ -7,7 +7,7 @@ int check_all_feature() {
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return 2;
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else if (__builtin_cpu_supports("aes+pmull+fp16+dit+dpb+dpb2+jscvt"))
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return 3;
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else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts+dgh"))
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else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts"))
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return 4;
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else if (__builtin_cpu_supports("i8mm+bf16+sve"))
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return 5;
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@ -15,9 +15,6 @@ __attribute__((target_version("bti"))) int fmv(void) { return 0; }
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// CHECK: define dso_local i32 @fmv._Mcrc() #[[crc:[0-9]+]] {
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__attribute__((target_version("crc"))) int fmv(void) { return 0; }
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// CHECK: define dso_local i32 @fmv._Mdgh() #[[ATTR0:[0-9]+]] {
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__attribute__((target_version("dgh"))) int fmv(void) { return 0; }
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// CHECK: define dso_local i32 @fmv._Mdit() #[[dit:[0-9]+]] {
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__attribute__((target_version("dit"))) int fmv(void) { return 0; }
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@ -157,7 +154,6 @@ int caller() {
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// CHECK: attributes #[[bf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[bti]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[crc]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[dit]] = { {{.*}} "target-features"="+dit,+fp-armv8,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[dotprod]] = { {{.*}} "target-features"="+dotprod,+fp-armv8,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[dpb]] = { {{.*}} "target-features"="+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a"
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@ -167,6 +163,7 @@ int caller() {
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// CHECK: attributes #[[fcma]] = { {{.*}} "target-features"="+complxnum,+fp-armv8,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[flagm]] = { {{.*}} "target-features"="+flagm,+fp-armv8,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[flagm2]] = { {{.*}} "target-features"="+altnzcv,+flagm,+fp-armv8,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[fp16]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[fp16fml]] = { {{.*}} "target-features"="+fp-armv8,+fp16fml,+fullfp16,+neon,+outline-atomics,+v8a"
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// CHECK: attributes #[[frintts]] = { {{.*}} "target-features"="+fp-armv8,+fptoint,+neon,+outline-atomics,+v8a"
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@ -17,7 +17,6 @@ int __attribute__((target_version("dpb"))) fmv_one(void) { return 2; }
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int __attribute__((target_version("default"))) fmv_one(void) { return 0; }
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int __attribute__((target_version("fp"))) fmv_two(void) { return 1; }
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int __attribute__((target_version("simd"))) fmv_two(void) { return 2; }
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int __attribute__((target_version("dgh"))) fmv_two(void) { return 3; }
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int __attribute__((target_version("fp16+simd"))) fmv_two(void) { return 4; }
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int __attribute__((target_version("default"))) fmv_two(void) { return 0; }
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int foo() {
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@ -255,13 +254,6 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
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//
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//
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// CHECK: Function Attrs: noinline nounwind optnone
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// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mdgh
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// CHECK-SAME: () #[[ATTR9]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret i32 3
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//
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//
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// CHECK: Function Attrs: noinline nounwind optnone
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// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd
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// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
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// CHECK-NEXT: entry:
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@ -576,29 +568,21 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
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// CHECK-NEXT: ret ptr @fmv_two._Mfp16Msimd
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// CHECK: resolver_else:
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 33554432
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 33554432
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 512
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 512
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// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
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// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
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// CHECK: resolver_return1:
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// CHECK-NEXT: ret ptr @fmv_two._Mdgh
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// CHECK-NEXT: ret ptr @fmv_two._Msimd
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// CHECK: resolver_else2:
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// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 512
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// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 512
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// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 256
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// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 256
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// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
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// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
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// CHECK: resolver_return3:
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// CHECK-NEXT: ret ptr @fmv_two._Msimd
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// CHECK: resolver_else4:
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// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 256
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// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 256
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// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
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// CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]]
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// CHECK: resolver_return5:
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// CHECK-NEXT: ret ptr @fmv_two._Mfp
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// CHECK: resolver_else6:
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// CHECK: resolver_else4:
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// CHECK-NEXT: ret ptr @fmv_two.default
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//
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//
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@ -15,7 +15,7 @@ int test_aarch64_features(void) {
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if (__builtin_cpu_supports("sve2,sve"))
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return 4;
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// expected-warning@+1 {{invalid cpu feature string}}
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if (__builtin_cpu_supports("dgh+sve2-pmull"))
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if (__builtin_cpu_supports("aes+sve2-pmull"))
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return 5;
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// expected-warning@+1 {{invalid cpu feature string}}
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if (__builtin_cpu_supports("default"))
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@ -19,10 +19,9 @@ int __attribute__((target_clones("sve+dotprod"))) redecl3(void);
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int redecl3(void);
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int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void);
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// expected-error@+3 {{'target_clones' attribute does not match previous declaration}}
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// expected-error@+2 {{'target_clones' attribute does not match previous declaration}}
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// expected-note@-2 {{previous declaration is here}}
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// expected-warning@+1 {{version list contains entries that don't impact code generation}}
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int __attribute__((target_clones("dgh", "bf16+dpb", "default"))) redecl4(void) { return 1; }
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int __attribute__((target_clones("dit", "bf16+dpb", "default"))) redecl4(void) { return 1; }
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int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
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// expected-error@+2 {{multiversioned function redeclarations require identical target attributes}}
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@ -47,7 +47,7 @@ enum CPUFeatures {
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FEAT_RCPC,
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FEAT_RCPC2,
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FEAT_FRINTTS,
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FEAT_DGH,
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RESERVED_FEAT_DGH, // previously used and now ABI legacy
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FEAT_I8MM,
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FEAT_BF16,
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RESERVED_FEAT_EBF16, // previously used and now ABI legacy
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@ -61,8 +61,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
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setCPUFeature(FEAT_RNG);
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if (hwcap2 & HWCAP2_I8MM)
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setCPUFeature(FEAT_I8MM);
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if (hwcap2 & HWCAP2_DGH)
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setCPUFeature(FEAT_DGH);
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if (hwcap2 & HWCAP2_FRINT)
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setCPUFeature(FEAT_FRINTTS);
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if (hwcap2 & HWCAP2_SVEF32MM)
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@ -47,7 +47,7 @@ enum CPUFeatures {
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FEAT_RCPC,
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FEAT_RCPC2,
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FEAT_FRINTTS,
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FEAT_DGH,
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RESERVED_FEAT_DGH, // previously used and now ABI legacy
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FEAT_I8MM,
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FEAT_BF16,
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RESERVED_FEAT_EBF16, // previously used and now ABI legacy
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@ -41,7 +41,6 @@ def : FMVExtension<"aes", "FEAT_PMULL", "+aes,+fp-armv8,+neon", 150>;
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def : FMVExtension<"bf16", "FEAT_BF16", "+bf16", 280>;
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def : FMVExtension<"bti", "FEAT_BTI", "+bti", 510>;
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def : FMVExtension<"crc", "FEAT_CRC", "+crc", 110>;
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def : FMVExtension<"dgh", "FEAT_DGH", "", 260>;
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def : FMVExtension<"dit", "FEAT_DIT", "+dit", 180>;
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def : FMVExtension<"dotprod", "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
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def : FMVExtension<"dpb", "FEAT_DPB", "+ccpp", 190>;
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