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Support z17 processor name and scheduler description (#135254)

Browse Source 
The recently announced IBM z17 processor implements the architecture
already supported as "arch15" in LLVM. This patch adds support for "z17"
as an alternate architecture name for arch15.

This patch also add the scheduler description for the z17 processor,
provided by Jonas Paulsson.
This commit is contained in:
Ulrich Weigand 2025-04-11 00:20:58 +02:00 committed by GitHub
parent 324083b5fe
commit 80267f8148
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
66 changed files with 1940 additions and 174 deletions
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2
clang/lib/Basic/Targets/SystemZ.cpp
View File

@ -114,7 +114,7 @@ static constexpr ISANameRevision ISARevisions[] = {
{{"arch12"}, 12}, {{"z14"}, 12},
{{"arch13"}, 13}, {{"z15"}, 13},
{{"arch14"}, 14}, {{"z16"}, 14},
{{"arch15"}, 15},
{{"arch15"}, 15}, {{"z17"}, 15},
};
int SystemZTargetInfo::getISARevision(StringRef Name) const {

4
clang/test/CodeGen/SystemZ/builtins-systemz-bitop.c
View File

@ -1,6 +1,6 @@
// REQUIRES: systemz-registered-target
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm -x c++ %s -o - | FileCheck %s
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm -x c++ %s -o - | FileCheck %s
unsigned long test_bdepg(unsigned long a, unsigned long b) {
// CHECK-LABEL: test_bdepg

2
clang/test/CodeGen/SystemZ/builtins-systemz-vector5-error.c
View File

@ -1,5 +1,5 @@
// REQUIRES: systemz-registered-target
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-unknown-unknown \
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-unknown-unknown \
// RUN: -Wall -Wno-unused -Werror -fsyntax-only -verify %s
typedef __attribute__((vector_size(16))) signed char vec_schar;

2
clang/test/CodeGen/SystemZ/builtins-systemz-vector5.c
View File

@ -1,5 +1,5 @@
// REQUIRES: systemz-registered-target
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -flax-vector-conversions=none \
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
typedef __attribute__((vector_size(16))) signed char vec_schar;

2
clang/test/CodeGen/SystemZ/builtins-systemz-zvector5-error.c
View File

@ -1,5 +1,5 @@
// REQUIRES: systemz-registered-target
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
// RUN: -fzvector -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -fsyntax-only -verify %s

4
clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
View File

@ -1,8 +1,8 @@
// REQUIRES: systemz-registered-target
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
// RUN: -O2 -fzvector -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
// RUN: -O2 -fzvector -flax-vector-conversions=none \
// RUN: -Wall -Wno-unused -Werror -S %s -o - | FileCheck %s --check-prefix=CHECK-ASM

2
clang/test/CodeGen/SystemZ/systemz-abi-vector.c
View File

@ -18,6 +18,8 @@
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu z17 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s

2
clang/test/CodeGen/SystemZ/systemz-abi.c
View File

@ -24,6 +24,8 @@
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: -emit-llvm -o - %s -mfloat-abi soft | FileCheck %s \
// RUN: --check-prefixes=CHECK,SOFT-FLOAT
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu z17 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \

2
clang/test/Driver/systemz-march.c
View File

@ -15,6 +15,7 @@
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch13 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH13 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=z16 %s 2>&1 | FileCheck --check-prefix=CHECK-Z16 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch14 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH14 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=z17 %s 2>&1 | FileCheck --check-prefix=CHECK-Z17 %s
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch15 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH15 %s
// CHECK-Z9: error: unknown target CPU 'z9'
@ -32,6 +33,7 @@
// CHECK-ARCH13: "-target-cpu" "arch13"
// CHECK-Z16: "-target-cpu" "z16"
// CHECK-ARCH14: "-target-cpu" "arch14"
// CHECK-Z17: "-target-cpu" "z17"
// CHECK-ARCH15: "-target-cpu" "arch15"
int x;

1
clang/test/Misc/target-invalid-cpu-note/systemz.c
View File

@ -20,4 +20,5 @@
// CHECK-SAME: {{^}}, arch14
// CHECK-SAME: {{^}}, z16
// CHECK-SAME: {{^}}, arch15
// CHECK-SAME: {{^}}, z17
// CHECK-SAME: {{$}}

3
clang/test/Preprocessor/predefined-arch-macros.c
View File

@ -4394,6 +4394,9 @@
// RUN: %clang -march=arch15 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH15
// RUN: %clang -march=z17 -E -dM %s -o - 2>&1 \
// RUN: -target s390x-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH15
// CHECK_SYSTEMZ_ARCH15: #define __ARCH__ 15
// CHECK_SYSTEMZ_ARCH15: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// CHECK_SYSTEMZ_ARCH15: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1

10
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -258,7 +258,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FSHL, MVT::i128, Custom);
setOperationAction(ISD::FSHR, MVT::i128, Custom);
// No special instructions for these before arch15.
// No special instructions for these before z17.
if (!Subtarget.hasVectorEnhancements3()) {
setOperationAction(ISD::MUL, MVT::i128, Expand);
setOperationAction(ISD::MULHS, MVT::i128, Expand);
@ -285,7 +285,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
// Use VPOPCT and add up partial results.
setOperationAction(ISD::CTPOP, MVT::i128, Custom);
// Additional instructions available with arch15.
// Additional instructions available with z17.
if (Subtarget.hasVectorEnhancements3()) {
setOperationAction(ISD::ABS, MVT::i128, Legal);
}
@ -357,7 +357,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
setOperationAction(ISD::CTLZ, MVT::i64, Legal);
// On arch15 we have native support for a 64-bit CTTZ.
// On z17 we have native support for a 64-bit CTTZ.
if (Subtarget.hasMiscellaneousExtensions4()) {
setOperationAction(ISD::CTTZ, MVT::i32, Promote);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Promote);
@ -4526,7 +4526,7 @@ SDValue SystemZTargetLowering::lowerMULH(SDValue Op,
SDLoc DL(Op);
SDValue Even, Odd;
// This custom expander is only used on arch15 and later for 64-bit types.
// This custom expander is only used on z17 and later for 64-bit types.
assert(!is32Bit(VT));
assert(Subtarget.hasMiscellaneousExtensions2());
@ -8733,7 +8733,7 @@ static unsigned detectEvenOddMultiplyOperand(const SelectionDAG &DAG,
}
}
// For arch15, we can also support the v2i64->i128 case, which looks like
// For z17, we can also support the v2i64->i128 case, which looks like
// (sign/zero_extend (extract_vector_elt X 0/1))
if (VT == MVT::i128 && Subtarget.hasVectorEnhancements3() &&
(Op.getOpcode() == ISD::SIGN_EXTEND ||

8
llvm/lib/Target/SystemZ/SystemZInstrVector.td
View File

@ -1995,7 +1995,7 @@ let Predicates = [FeatureVector] in {
(VLEG (VGBM 0), bdxaddr12only:$addr, 1)>;
}
// Zero-extensions from VR element to i128 on arch15.
// Zero-extensions from VR element to i128 on z17.
let Predicates = [FeatureVectorEnhancements3] in {
def : Pat<(i128 (zext (i64 (z_vector_extract (v2i64 VR128:$src), 0)))),
(VUPLHG VR128:$src)>;
@ -2011,7 +2011,7 @@ let Predicates = [FeatureVectorEnhancements3] in {
(VUPLLG (VUPLLF VR128:$src))>;
}
// In-register i128 sign-extensions on arch15.
// In-register i128 sign-extensions on z17.
let Predicates = [FeatureVectorEnhancements3] in {
def : Pat<(i128 (sext_inreg VR128:$x, i8)), (VUPLG (VSEGB VR128:$x))>;
def : Pat<(i128 (sext_inreg VR128:$x, i16)), (VUPLG (VSEGH VR128:$x))>;
@ -2031,7 +2031,7 @@ let Predicates = [FeatureVector] in {
(VSRAB (VREPG VR128:$x, 1), (VREPIB 64))>;
}
// Sign-extensions from GPR to i128 on arch15.
// Sign-extensions from GPR to i128 on z17.
let Predicates = [FeatureVectorEnhancements3] in {
def : Pat<(i128 (sext_inreg (anyext GR32:$x), i8)),
(VUPLG (VLVGP (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32)),
@ -2075,7 +2075,7 @@ let Predicates = [FeatureVector] in {
(VSRAB (VLREPG bdxaddr12only:$addr), (VREPIB 64))>;
}
// Sign-extensions from VR element to i128 on arch15.
// Sign-extensions from VR element to i128 on z17.
let Predicates = [FeatureVectorEnhancements3] in {
def : Pat<(i128 (sext (i64 (z_vector_extract (v2i64 VR128:$src), 0)))),
(VUPHG VR128:$src)>;

3
llvm/lib/Target/SystemZ/SystemZProcessors.td
View File

@ -41,4 +41,5 @@ def : ProcessorModel<"z15", Z15Model, Arch13SupportedFeatures.List>;
def : ProcessorModel<"arch14", Z16Model, Arch14SupportedFeatures.List>;
def : ProcessorModel<"z16", Z16Model, Arch14SupportedFeatures.List>;
def : ProcessorModel<"arch15", Z16Model, Arch15SupportedFeatures.List>;
def : ProcessorModel<"arch15", Z17Model, Arch15SupportedFeatures.List>;
def : ProcessorModel<"z17", Z17Model, Arch15SupportedFeatures.List>;

1
llvm/lib/Target/SystemZ/SystemZSchedule.td
View File

@ -60,6 +60,7 @@ def VBU : SchedWrite; // Virtual branching unit
def MCD : SchedWrite; // Millicode
include "SystemZScheduleZ17.td"
include "SystemZScheduleZ16.td"
include "SystemZScheduleZ15.td"
include "SystemZScheduleZ14.td"

16
llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
View File

@ -1555,12 +1555,12 @@ def : InstRW<[WLat2, VecDFX, NormalGr], (instregex "V(T|C)P$")>;
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VSCH(S|D|X)?P$")>;
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VSCSHP$")>;
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VCSPH")>;
def : InstRW<[WLat2, WLat2, VecXsPm, NormalGr], (instregex "VCLZDP")>;
def : InstRW<[WLat10, WLat10, VecDF2, NormalGr], (instregex "VSRPR")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VPKZR")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZH")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZL")>;
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VCSPH$")>;
def : InstRW<[WLat2, WLat2, VecXsPm, NormalGr], (instregex "VCLZDP$")>;
def : InstRW<[WLat10, WLat10, VecDF2, NormalGr], (instregex "VSRPR$")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VPKZR$")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZH$")>;
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZL$")>;
// -------------------------------- System ---------------------------------- //
@ -1597,8 +1597,8 @@ def : InstRW<[WLat30, MCD], (instregex "S(T)?PX$")>;
// System: Breaking-Event-Address-Register Instructions
//===----------------------------------------------------------------------===//
def : InstRW<[WLat3LSU, LSU2, GroupAlone], (instregex "LBEAR")>;
def : InstRW<[WLat1, LSU2, FXb, GroupAlone], (instregex "STBEAR")>;
def : InstRW<[WLat3LSU, LSU2, GroupAlone], (instregex "LBEAR$")>;
def : InstRW<[WLat1, LSU2, FXb, GroupAlone], (instregex "STBEAR$")>;
//===----------------------------------------------------------------------===//
// System: Storage-Key and Real Memory Instructions

1754
llvm/lib/Target/SystemZ/SystemZScheduleZ17.td Normal file
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File diff suppressed because it is too large Load Diff

2
llvm/lib/TargetParser/Host.cpp
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@ -430,7 +430,7 @@ StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
case 9175:
case 9176:
default:
return HaveVectorSupport? "arch15" : "zEC12";
return HaveVectorSupport? "z17" : "zEC12";
}
}
} // end anonymous namespace

86
llvm/test/Analysis/CostModel/SystemZ/divrem-reg.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=systemz-unknown -mcpu=z13 | FileCheck %s --check-prefixes=CHECK,Z13
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=systemz-unknown -mcpu=arch15 | FileCheck %s --check-prefixes=CHECK,ARC15
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=systemz-unknown -mcpu=z17 | FileCheck %s --check-prefixes=CHECK,Z17
; Check costs of divisions by register
;
@ -52,9 +52,9 @@ define <2 x i64> @fun4(<2 x i64> %a, <2 x i64> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r = sdiv <2 x i64> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
;
; ARC15-LABEL: 'fun4'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = sdiv <2 x i64> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
; Z17-LABEL: 'fun4'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = sdiv <2 x i64> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
;
%r = sdiv <2 x i64> %a, %b
ret <2 x i64> %r
@ -65,9 +65,9 @@ define <4 x i32> @fun5(<4 x i32> %a, <4 x i32> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 94 for instruction: %r = sdiv <4 x i32> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
;
; ARC15-LABEL: 'fun5'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = sdiv <4 x i32> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
; Z17-LABEL: 'fun5'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = sdiv <4 x i32> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
;
%r = sdiv <4 x i32> %a, %b
ret <4 x i32> %r
@ -78,9 +78,9 @@ define <2 x i32> @fun6(<2 x i32> %a, <2 x i32> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %r = sdiv <2 x i32> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
;
; ARC15-LABEL: 'fun6'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = sdiv <2 x i32> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
; Z17-LABEL: 'fun6'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = sdiv <2 x i32> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
;
%r = sdiv <2 x i32> %a, %b
ret <2 x i32> %r
@ -167,9 +167,9 @@ define <2 x i64> @fun15(<2 x i64> %a, <2 x i64> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r = udiv <2 x i64> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
;
; ARC15-LABEL: 'fun15'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = udiv <2 x i64> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
; Z17-LABEL: 'fun15'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = udiv <2 x i64> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
;
%r = udiv <2 x i64> %a, %b
ret <2 x i64> %r
@ -180,9 +180,9 @@ define <4 x i32> @fun16(<4 x i32> %a, <4 x i32> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 94 for instruction: %r = udiv <4 x i32> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
;
; ARC15-LABEL: 'fun16'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = udiv <4 x i32> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
; Z17-LABEL: 'fun16'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = udiv <4 x i32> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
;
%r = udiv <4 x i32> %a, %b
ret <4 x i32> %r
@ -193,9 +193,9 @@ define <2 x i32> @fun17(<2 x i32> %a, <2 x i32> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %r = udiv <2 x i32> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
;
; ARC15-LABEL: 'fun17'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = udiv <2 x i32> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
; Z17-LABEL: 'fun17'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = udiv <2 x i32> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
;
%r = udiv <2 x i32> %a, %b
ret <2 x i32> %r
@ -282,9 +282,9 @@ define <2 x i64> @fun26(<2 x i64> %a, <2 x i64> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r = srem <2 x i64> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
;
; ARC15-LABEL: 'fun26'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = srem <2 x i64> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
; Z17-LABEL: 'fun26'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = srem <2 x i64> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
;
%r = srem <2 x i64> %a, %b
ret <2 x i64> %r
@ -295,9 +295,9 @@ define <4 x i32> @fun27(<4 x i32> %a, <4 x i32> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 94 for instruction: %r = srem <4 x i32> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
;
; ARC15-LABEL: 'fun27'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = srem <4 x i32> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
; Z17-LABEL: 'fun27'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = srem <4 x i32> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
;
%r = srem <4 x i32> %a, %b
ret <4 x i32> %r
@ -308,9 +308,9 @@ define <2 x i32> @fun28(<2 x i32> %a, <2 x i32> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %r = srem <2 x i32> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
;
; ARC15-LABEL: 'fun28'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = srem <2 x i32> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
; Z17-LABEL: 'fun28'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = srem <2 x i32> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
;
%r = srem <2 x i32> %a, %b
ret <2 x i32> %r
@ -397,9 +397,9 @@ define <2 x i64> @fun37(<2 x i64> %a, <2 x i64> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %r = urem <2 x i64> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
;
; ARC15-LABEL: 'fun37'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = urem <2 x i64> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
; Z17-LABEL: 'fun37'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = urem <2 x i64> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i64> %r
;
%r = urem <2 x i64> %a, %b
ret <2 x i64> %r
@ -410,9 +410,9 @@ define <4 x i32> @fun38(<4 x i32> %a, <4 x i32> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 94 for instruction: %r = urem <4 x i32> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
;
; ARC15-LABEL: 'fun38'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = urem <4 x i32> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
; Z17-LABEL: 'fun38'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = urem <4 x i32> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %r
;
%r = urem <4 x i32> %a, %b
ret <4 x i32> %r
@ -423,9 +423,9 @@ define <2 x i32> @fun39(<2 x i32> %a, <2 x i32> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %r = urem <2 x i32> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
;
; ARC15-LABEL: 'fun39'
; ARC15-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = urem <2 x i32> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
; Z17-LABEL: 'fun39'
; Z17-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %r = urem <2 x i32> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x i32> %r
;
%r = urem <2 x i32> %a, %b
ret <2 x i32> %r
@ -473,9 +473,9 @@ define <8 x i64> @fun44(<8 x i64> %a, <8 x i64> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 1000 for instruction: %r = sdiv <8 x i64> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i64> %r
;
; ARC15-LABEL: 'fun44'
; ARC15-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %r = sdiv <8 x i64> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i64> %r
; Z17-LABEL: 'fun44'
; Z17-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %r = sdiv <8 x i64> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i64> %r
;
%r = sdiv <8 x i64> %a, %b
ret <8 x i64> %r
@ -486,9 +486,9 @@ define <8 x i32> @fun45(<8 x i32> %a, <8 x i32> %b) {
; Z13-NEXT: Cost Model: Found an estimated cost of 1000 for instruction: %r = urem <8 x i32> %a, %b
; Z13-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i32> %r
;
; ARC15-LABEL: 'fun45'
; ARC15-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %r = urem <8 x i32> %a, %b
; ARC15-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i32> %r
; Z17-LABEL: 'fun45'
; Z17-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %r = urem <8 x i32> %a, %b
; Z17-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <8 x i32> %r
;
%r = urem <8 x i32> %a, %b
ret <8 x i32> %r

8
llvm/test/Analysis/CostModel/SystemZ/i128-cmp-ext-conv.ll
View File

@ -1,12 +1,12 @@
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=systemz-unknown -mcpu=z13 | FileCheck %s --check-prefixes=CHECK,Z13
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=systemz-unknown -mcpu=arch15 | FileCheck %s --check-prefixes=CHECK,ARC15
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=systemz-unknown -mcpu=z17 | FileCheck %s --check-prefixes=CHECK,Z17
;
define i128 @fun1(i128 %val1, i128 %val2) {
; CHECK-LABEL: 'fun1'
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %cmp = icmp eq i128 %val1, %val2
; Z13: Cost Model: Found an estimated cost of 5 for instruction: %v128 = sext i1 %cmp to i128
; ARC15: Cost Model: Found an estimated cost of 0 for instruction: %v128 = sext i1 %cmp to i128
; Z17: Cost Model: Found an estimated cost of 0 for instruction: %v128 = sext i1 %cmp to i128
%cmp = icmp eq i128 %val1, %val2
%v128 = sext i1 %cmp to i128
ret i128 %v128
@ -27,7 +27,7 @@ define i128 @fun3(i128 %val1, i128 %val2,
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %cmp = icmp eq i128 %val1, %val2
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %add = add i128 %val3, %val4
; Z13: Cost Model: Found an estimated cost of 4 for instruction: %sel = select i1 %cmp, i128 %val3, i128 %add
; ARC15: Cost Model: Found an estimated cost of 1 for instruction: %sel = select i1 %cmp, i128 %val3, i128 %add
; Z17: Cost Model: Found an estimated cost of 1 for instruction: %sel = select i1 %cmp, i128 %val3, i128 %add
%cmp = icmp eq i128 %val1, %val2
%add = add i128 %val3, %val4
%sel = select i1 %cmp, i128 %val3, i128 %add
@ -40,7 +40,7 @@ define i64 @fun3_sel64(i128 %val1, i128 %val2,
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %cmp = icmp ugt i128 %val1, %val2
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %add = add i64 %val3, %val4
; Z13: Cost Model: Found an estimated cost of 4 for instruction: %sel = select i1 %cmp, i64 %val3, i64 %add
; ARC15: Cost Model: Found an estimated cost of 1 for instruction: %sel = select i1 %cmp, i64 %val3, i64 %add
; Z17: Cost Model: Found an estimated cost of 1 for instruction: %sel = select i1 %cmp, i64 %val3, i64 %add
%cmp = icmp ugt i128 %val1, %val2
%add = add i64 %val3, %val4
%sel = select i1 %cmp, i64 %val3, i64 %add

10
llvm/test/Analysis/CostModel/SystemZ/int-arith.ll
View File

@ -1,5 +1,5 @@
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=systemz-unknown -mcpu=z13 | FileCheck %s
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=systemz-unknown -mcpu=arch15 | FileCheck %s -check-prefix=ARC15
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -mtriple=systemz-unknown -mcpu=z17 | FileCheck %s -check-prefix=Z17
;
; Note: The scalarized vector instructions costs are not including any
; extracts, due to the undef operands.
@ -132,22 +132,22 @@ define void @mul() {
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res5 = mul <2 x i16> undef, undef
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res6 = mul <2 x i32> undef, undef
; CHECK: Cost Model: Found an estimated cost of 3 for instruction: %res7 = mul <2 x i64> undef, undef
; ARC15: Cost Model: Found an estimated cost of 1 for instruction: %res7 = mul <2 x i64> undef, undef
; Z17: Cost Model: Found an estimated cost of 1 for instruction: %res7 = mul <2 x i64> undef, undef
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res8 = mul <4 x i8> undef, undef
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res9 = mul <4 x i16> undef, undef
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res10 = mul <4 x i32> undef, undef
; CHECK: Cost Model: Found an estimated cost of 6 for instruction: %res11 = mul <4 x i64> undef, undef
; ARC15: Cost Model: Found an estimated cost of 2 for instruction: %res11 = mul <4 x i64> undef, undef
; Z17: Cost Model: Found an estimated cost of 2 for instruction: %res11 = mul <4 x i64> undef, undef
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res12 = mul <8 x i8> undef, undef
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res13 = mul <8 x i16> undef, undef
; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res14 = mul <8 x i32> undef, undef
; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res15 = mul <8 x i64> undef, undef
; ARC15: Cost Model: Found an estimated cost of 4 for instruction: %res15 = mul <8 x i64> undef, undef
; Z17: Cost Model: Found an estimated cost of 4 for instruction: %res15 = mul <8 x i64> undef, undef
; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %res16 = mul <16 x i8> undef, undef
; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res17 = mul <16 x i16> undef, undef
; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res18 = mul <16 x i32> undef, undef
; CHECK: Cost Model: Found an estimated cost of 24 for instruction: %res19 = mul <16 x i64> undef, undef
; ARC15: Cost Model: Found an estimated cost of 8 for instruction: %res19 = mul <16 x i64> undef, undef
; Z17: Cost Model: Found an estimated cost of 8 for instruction: %res19 = mul <16 x i64> undef, undef
ret void;
}

2
llvm/test/CodeGen/SystemZ/args-12.ll
View File

@ -2,7 +2,7 @@
; Test the handling of i128 argument values
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
declare void @bar(i64, i64, i64, i64, i128,
i64, i64, i64, i64, i128)

2
llvm/test/CodeGen/SystemZ/args-13.ll
View File

@ -2,7 +2,7 @@
; Test incoming i128 arguments.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Do some arithmetic so that we can see the register being used.
define void @f1(ptr %r2, i16 %r3, i32 %r4, i64 %r5, i128 %r6) {

2
llvm/test/CodeGen/SystemZ/bitop-intrinsics.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test bit deposit / extract intrinsics
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
declare i64 @llvm.s390.bdepg(i64, i64)
declare i64 @llvm.s390.bextg(i64, i64)

4
llvm/test/CodeGen/SystemZ/int-abs-03.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test 128-bit absolute value in vector registers on arch15
; Test 128-bit absolute value in vector registers on z17
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
define i128 @f1(i128 %src) {
; CHECK-LABEL: f1:

2
llvm/test/CodeGen/SystemZ/int-add-19.ll
View File

@ -2,7 +2,7 @@
; Test 128-bit addition in vector registers on z13 and later
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
define i128 @f1(i128 %a, i128 %b) {
; CHECK-LABEL: f1:

4
llvm/test/CodeGen/SystemZ/int-cmp-64.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test 128-bit comparisons in vector registers on arch15
; Test 128-bit comparisons in vector registers on z17
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 -verify-machineinstrs | FileCheck %s
; Equality comparison.
define i64 @f1(i128 %value1, i128 %value2, i64 %a, i64 %b) {

4
llvm/test/CodeGen/SystemZ/int-conv-15.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test 128-bit arithmetic in vector registers on arch15
; Test 128-bit arithmetic in vector registers on z17
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Sign extension from i64.
define i128 @f1(i64 %a) {

4
llvm/test/CodeGen/SystemZ/int-div-08.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test 128-bit division and remainder in vector registers on arch15
; Test 128-bit division and remainder in vector registers on z17
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Divide signed.
define i128 @f1(i128 %a, i128 %b) {

4
llvm/test/CodeGen/SystemZ/int-max-02.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test i128 maximum on arch15.
; Test i128 maximum on z17.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Test with slt.
define i128 @f1(i128 %val1, i128 %val2) {

4
llvm/test/CodeGen/SystemZ/int-min-02.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test i128 minimum on arch15.
; Test i128 minimum on z17.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Test with slt.
define i128 @f1(i128 %val1, i128 %val2) {

4
llvm/test/CodeGen/SystemZ/int-mul-14.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test 128-bit multiplication in vector registers on arch15
; Test 128-bit multiplication in vector registers on z17
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Multiplication.
define i128 @f1(i128 %a, i128 %b) {

4
llvm/test/CodeGen/SystemZ/int-mul-15.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; Test high-part i64->i128 multiplications on arch15.
; Test high-part i64->i128 multiplications on z17.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Check zero-extended multiplication in which only the high part is used.
define i64 @f1(i64 %dummy, i64 %a, i64 %b) {

4
llvm/test/CodeGen/SystemZ/int-mul-16.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test high-part i128->i256 multiplications on arch15.
; Test high-part i128->i256 multiplications on z17.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Multiply high signed.
define i128 @f1(i128 %a, i128 %b) {

4
llvm/test/CodeGen/SystemZ/int-neg-04.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test 128-bit negation in vector registers on arch15
; Test 128-bit negation in vector registers on z17
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
define i128 @f1(i128 %src) {
; CHECK-LABEL: f1:

2
llvm/test/CodeGen/SystemZ/int-sub-12.ll
View File

@ -2,7 +2,7 @@
; Test 128-bit subtraction in vector registers on z13 and later
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
define i128 @f1(i128 %a, i128 %b) {
; CHECK-LABEL: f1:

2
llvm/test/CodeGen/SystemZ/llxa-01.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of LOAD LOGICAL INDEXED ADDRESS byte instructions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; DO NOT USE: LLXAB with base and index.
define dso_local ptr @f0(ptr %ptr, i32 %idx) {

2
llvm/test/CodeGen/SystemZ/llxa-02.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of LOAD LOGICAL INDEXED ADDRESS halfword instructions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; LLXAH with base and index.
define dso_local ptr @f0(ptr %ptr, i32 %idx) {

2
llvm/test/CodeGen/SystemZ/llxa-03.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of LOAD LOGICAL INDEXED ADDRESS word instructions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; LLXAF with base and index.
define dso_local ptr @f0(ptr %ptr, i32 %idx) {

2
llvm/test/CodeGen/SystemZ/llxa-04.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of LOAD LOGICAL INDEXED ADDRESS doubleword instructions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; LLXAG with base and index.
define dso_local ptr @f0(ptr %ptr, i32 %idx) {

2
llvm/test/CodeGen/SystemZ/llxa-05.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of LOAD LOGICAL INDEXED ADDRESS quadword instructions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; LLXAQ with base and index.
define dso_local ptr @f0(ptr %ptr, i32 %idx) {

2
llvm/test/CodeGen/SystemZ/lxa-01.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of LOAD INDEXED ADDRESS byte instructions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; DO NOT USE: LXAB with base and index.
define dso_local ptr @f0(ptr %ptr, i32 %idx) {

2
llvm/test/CodeGen/SystemZ/lxa-02.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of LOAD INDEXED ADDRESS halfword instructions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; LXAH with base and index.
define dso_local ptr @f0(ptr %ptr, i32 %idx) {

2
llvm/test/CodeGen/SystemZ/lxa-03.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of LOAD INDEXED ADDRESS word instructions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; LXAF with base and index.
define dso_local ptr @f0(ptr %ptr, i32 %idx) {

2
llvm/test/CodeGen/SystemZ/lxa-04.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of LOAD INDEXED ADDRESS doubleword instructions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; LXAG with base and index.
define dso_local ptr @f0(ptr %ptr, i32 %idx) {

2
llvm/test/CodeGen/SystemZ/lxa-05.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of LOAD INDEXED ADDRESS quadword instructions.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; LXAQ with base and index.
define dso_local ptr @f0(ptr %ptr, i32 %idx) {

2
llvm/test/CodeGen/SystemZ/scalar-ctlz-03.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
;
; FIXME: two consecutive immediate adds not fused in i16/i8 functions.

2
llvm/test/CodeGen/SystemZ/scalar-ctlz-04.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
declare i128 @llvm.ctlz.i128(i128, i1)

2
llvm/test/CodeGen/SystemZ/scalar-cttz-03.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
declare i64 @llvm.cttz.i64(i64, i1)
declare i32 @llvm.cttz.i32(i32, i1)

4
llvm/test/CodeGen/SystemZ/scalar-cttz-04.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test 128-bit arithmetic in vector registers on arch15
; Test 128-bit arithmetic in vector registers on z17
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
declare i128 @llvm.cttz.i128(i128, i1)

4
llvm/test/CodeGen/SystemZ/vec-cmp-09.ll
View File

@ -1,6 +1,6 @@
; Test usage of VBLEND on arch15.
; Test usage of VBLEND on z17.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
; CHECK-LABEL: f1:

4
llvm/test/CodeGen/SystemZ/vec-div-03.ll
View File

@ -1,6 +1,6 @@
; Test vector division on arch15.
; Test vector division on z17.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Test a v4i32 signed division.
define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {

58
llvm/test/CodeGen/SystemZ/vec-eval.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test use of VECTOR EVALUATE for combined boolean operations.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
define <16 x i8> @eval0(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval0:
@ -279,8 +279,8 @@ entry:
define <16 x i8> @eval24(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval24:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v26, %v28, %v24, 2
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v24, %v0, %v24, %v1, 47
; CHECK-NEXT: br %r14
entry:
@ -376,8 +376,8 @@ entry:
define <16 x i8> @eval30(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval30:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vn %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v26, %v28, %v24, 2
; CHECK-NEXT: vn %v1, %v28, %v26
; CHECK-NEXT: veval %v24, %v0, %v24, %v1, 47
; CHECK-NEXT: br %r14
entry:
@ -596,8 +596,8 @@ entry:
define <16 x i8> @eval45(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval45:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vo %v0, %v28, %v24
; CHECK-NEXT: veval %v1, %v26, %v24, %v28, 1
; CHECK-NEXT: vo %v0, %v28, %v24
; CHECK-NEXT: veval %v1, %v1, %v24, %v26, 47
; CHECK-NEXT: veval %v24, %v1, %v26, %v0, 47
; CHECK-NEXT: br %r14
@ -617,8 +617,8 @@ entry:
define <16 x i8> @eval46(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval46:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vn %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v26, %v28, %v24, 8
; CHECK-NEXT: vn %v1, %v28, %v26
; CHECK-NEXT: veval %v24, %v0, %v24, %v1, 47
; CHECK-NEXT: br %r14
entry:
@ -722,8 +722,8 @@ entry:
define <16 x i8> @eval54(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval54:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vn %v1, %v28, %v24
; CHECK-NEXT: veval %v0, %v24, %v28, %v26, 2
; CHECK-NEXT: vn %v1, %v28, %v24
; CHECK-NEXT: veval %v24, %v0, %v26, %v1, 47
; CHECK-NEXT: br %r14
entry:
@ -770,8 +770,8 @@ entry:
define <16 x i8> @eval57(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval57:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vo %v0, %v28, %v26
; CHECK-NEXT: veval %v1, %v26, %v24, %v28, 1
; CHECK-NEXT: vo %v0, %v28, %v26
; CHECK-NEXT: veval %v1, %v1, %v26, %v24, 47
; CHECK-NEXT: veval %v24, %v1, %v24, %v0, 47
; CHECK-NEXT: br %r14
@ -1060,8 +1060,8 @@ define <16 x i8> @eval77(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval77:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vgbm %v0, 65535
; CHECK-NEXT: vn %v1, %v26, %v24
; CHECK-NEXT: veval %v0, %v24, %v0, %v26, 40
; CHECK-NEXT: vn %v1, %v26, %v24
; CHECK-NEXT: veval %v0, %v28, %v0, %v1, 7
; CHECK-NEXT: veval %v24, %v0, %v24, %v26, 47
; CHECK-NEXT: br %r14
@ -1540,10 +1540,10 @@ define <16 x i8> @eval109(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval109:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vgbm %v0, 65535
; CHECK-NEXT: vn %v2, %v26, %v24
; CHECK-NEXT: veval %v0, %v24, %v0, %v26, 40
; CHECK-NEXT: vo %v1, %v28, %v24
; CHECK-NEXT: vn %v2, %v26, %v24
; CHECK-NEXT: veval %v0, %v28, %v0, %v2, 7
; CHECK-NEXT: vo %v1, %v28, %v24
; CHECK-NEXT: veval %v0, %v0, %v24, %v26, 47
; CHECK-NEXT: veval %v24, %v0, %v26, %v1, 47
; CHECK-NEXT: br %r14
@ -1621,8 +1621,8 @@ define <16 x i8> @eval113(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval113:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vgbm %v0, 65535
; CHECK-NEXT: vn %v1, %v26, %v24
; CHECK-NEXT: veval %v0, %v24, %v0, %v26, 40
; CHECK-NEXT: vn %v1, %v26, %v24
; CHECK-NEXT: veval %v0, %v28, %v0, %v1, 7
; CHECK-NEXT: veval %v24, %v0, %v26, %v24, 47
; CHECK-NEXT: br %r14
@ -1731,8 +1731,8 @@ define <16 x i8> @eval120(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vno %v0, %v24, %v24
; CHECK-NEXT: veval %v0, %v0, %v28, %v26, 2
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v0, %v26, %v24, 47
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v24, %v0, %v24, %v1, 47
; CHECK-NEXT: br %r14
entry:
@ -1753,10 +1753,10 @@ define <16 x i8> @eval121(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval121:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vgbm %v0, 65535
; CHECK-NEXT: vn %v2, %v26, %v24
; CHECK-NEXT: veval %v0, %v24, %v0, %v26, 40
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: vn %v2, %v26, %v24
; CHECK-NEXT: veval %v0, %v28, %v0, %v2, 7
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v0, %v26, %v24, 47
; CHECK-NEXT: veval %v24, %v0, %v24, %v1, 47
; CHECK-NEXT: br %r14
@ -1802,8 +1802,8 @@ define <16 x i8> @eval123(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vno %v0, %v24, %v24
; CHECK-NEXT: veval %v0, %v0, %v28, %v26, 2
; CHECK-NEXT: voc %v1, %v26, %v28
; CHECK-NEXT: veval %v0, %v0, %v26, %v24, 47
; CHECK-NEXT: voc %v1, %v26, %v28
; CHECK-NEXT: veval %v24, %v0, %v1, %v24, 31
; CHECK-NEXT: br %r14
entry:
@ -2084,8 +2084,8 @@ entry:
define <16 x i8> @eval141(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval141:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vo %v0, %v26, %v24
; CHECK-NEXT: veval %v1, %v26, %v24, %v28, 1
; CHECK-NEXT: vo %v0, %v26, %v24
; CHECK-NEXT: veval %v1, %v1, %v24, %v26, 47
; CHECK-NEXT: veval %v24, %v1, %v0, %v28, 143
; CHECK-NEXT: br %r14
@ -2105,8 +2105,8 @@ entry:
define <16 x i8> @eval142(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval142:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vn %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v26, %v24, %v28, 127
; CHECK-NEXT: vn %v1, %v28, %v26
; CHECK-NEXT: veval %v24, %v24, %v1, %v0, 174
; CHECK-NEXT: br %r14
entry:
@ -2253,8 +2253,8 @@ entry:
define <16 x i8> @eval151(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval151:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vx %v0, %v28, %v26
; CHECK-NEXT: veval %v1, %v24, %v28, %v26, 2
; CHECK-NEXT: vx %v0, %v28, %v26
; CHECK-NEXT: veval %v1, %v1, %v26, %v24, 31
; CHECK-NEXT: veval %v24, %v1, %v0, %v24, 143
; CHECK-NEXT: br %r14
@ -2289,8 +2289,8 @@ entry:
define <16 x i8> @eval153(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval153:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v24, %v28, %v26, 111
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v2, %v26, %v24, %v28, 1
; CHECK-NEXT: veval %v24, %v2, %v0, %v1, 239
; CHECK-NEXT: br %r14
@ -2309,8 +2309,8 @@ entry:
define <16 x i8> @eval154(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval154:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v24, %v28, %v26, 111
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v2, %v24, %v26, %v28, 2
; CHECK-NEXT: veval %v24, %v2, %v0, %v1, 239
; CHECK-NEXT: br %r14
@ -2330,9 +2330,9 @@ entry:
define <16 x i8> @eval155(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval155:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: veval %v0, %v24, %v28, %v26, 111
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: vn %v2, %v26, %v24
; CHECK-NEXT: veval %v0, %v24, %v28, %v26, 111
; CHECK-NEXT: veval %v24, %v2, %v0, %v1, 239
; CHECK-NEXT: br %r14
entry:
@ -2365,8 +2365,8 @@ entry:
define <16 x i8> @eval157(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval157:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vx %v0, %v28, %v26
; CHECK-NEXT: veval %v1, %v26, %v24, %v28, 1
; CHECK-NEXT: vx %v0, %v28, %v26
; CHECK-NEXT: veval %v1, %v1, %v24, %v26, 47
; CHECK-NEXT: veval %v24, %v1, %v0, %v24, 143
; CHECK-NEXT: br %r14
@ -2386,8 +2386,8 @@ entry:
define <16 x i8> @eval158(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval158:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vn %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v24, %v28, %v26, 111
; CHECK-NEXT: vn %v1, %v28, %v26
; CHECK-NEXT: veval %v24, %v24, %v1, %v0, 174
; CHECK-NEXT: br %r14
entry:
@ -2685,8 +2685,8 @@ entry:
define <16 x i8> @eval178(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval178:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vn %v1, %v26, %v24
; CHECK-NEXT: veval %v0, %v26, %v28, %v24, 138
; CHECK-NEXT: vn %v1, %v26, %v24
; CHECK-NEXT: veval %v24, %v0, %v1, %v28, 47
; CHECK-NEXT: br %r14
entry:
@ -2778,8 +2778,8 @@ entry:
define <16 x i8> @eval183(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval183:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: voc %v0, %v26, %v28
; CHECK-NEXT: veval %v1, %v24, %v28, %v26, 2
; CHECK-NEXT: voc %v0, %v26, %v28
; CHECK-NEXT: veval %v1, %v1, %v26, %v24, 31
; CHECK-NEXT: veval %v24, %v1, %v0, %v24, 47
; CHECK-NEXT: br %r14
@ -2884,8 +2884,8 @@ entry:
define <16 x i8> @eval189(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval189:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: voc %v0, %v26, %v28
; CHECK-NEXT: veval %v1, %v26, %v24, %v28, 1
; CHECK-NEXT: voc %v0, %v26, %v28
; CHECK-NEXT: veval %v1, %v1, %v24, %v26, 47
; CHECK-NEXT: veval %v24, %v1, %v0, %v24, 47
; CHECK-NEXT: br %r14
@ -3480,8 +3480,8 @@ define <16 x i8> @eval228(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval228:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vno %v0, %v26, %v26
; CHECK-NEXT: vo %v1, %v28, %v24
; CHECK-NEXT: veval %v2, %v24, %v28, %v26, 2
; CHECK-NEXT: vo %v1, %v28, %v24
; CHECK-NEXT: veval %v0, %v2, %v0, %v24, 47
; CHECK-NEXT: veval %v24, %v0, %v26, %v1, 47
; CHECK-NEXT: br %r14
@ -3564,8 +3564,8 @@ entry:
define <16 x i8> @eval232(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval232:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v24, %v28, %v26, 31
; CHECK-NEXT: vo %v1, %v28, %v26
; CHECK-NEXT: veval %v24, %v24, %v1, %v0, 174
; CHECK-NEXT: br %r14
entry:
@ -3582,8 +3582,8 @@ entry:
define <16 x i8> @eval233(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %src3) {
; CHECK-LABEL: eval233:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vx %v1, %v28, %v26
; CHECK-NEXT: veval %v0, %v24, %v28, %v26, 31
; CHECK-NEXT: vx %v1, %v28, %v26
; CHECK-NEXT: veval %v24, %v24, %v1, %v0, 174
; CHECK-NEXT: br %r14
entry:

4
llvm/test/CodeGen/SystemZ/vec-intrinsics-05.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; Test vector intrinsics added with arch15.
; Test vector intrinsics added with z17.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
declare <16 x i8> @llvm.s390.vgemb(<8 x i16>)
declare <8 x i16> @llvm.s390.vgemh(<16 x i8>)

4
llvm/test/CodeGen/SystemZ/vec-mul-06.ll
View File

@ -1,6 +1,6 @@
; Test vector multiplication on arch15.
; Test vector multiplication on z17.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Test a v2i64 multiplication.
define <2 x i64> @f1(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {

4
llvm/test/CodeGen/SystemZ/vec-mul-08.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test widening vector multiplication on arch15.
; Test widening vector multiplication on z17.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Test a v2i64 (even) -> i128 unsigned widening multiplication.
define i128 @f1(<2 x i64> %val1, <2 x i64> %val2) {

4
llvm/test/CodeGen/SystemZ/vec-mul-10.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test widening vector multiply-and-add on arch15.
; Test widening vector multiply-and-add on z17.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Test a v2i64 (even) -> i128 unsigned widening multiply-and-add.
define i128 @f1(<2 x i64> %val1, <2 x i64> %val2, i128 %val3) {

4
llvm/test/CodeGen/SystemZ/vec-mul-12.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test high-part vector multiplication on arch15
; Test high-part vector multiplication on z17
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Test a v2i64 unsigned high-part multiplication.
define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {

4
llvm/test/CodeGen/SystemZ/vec-mul-14.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test high-part vector multiply-and-add on arch15
; Test high-part vector multiply-and-add on z17
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
; Test a v2i64 unsigned high-part multiply-and-add.
define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {

2
llvm/test/CodeGen/SystemZ/vec-unpack-02.ll
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@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
define i128 @f1(<2 x i64> %a) {
; CHECK-LABEL: f1:

2
llvm/test/CodeGen/SystemZ/vec-unpack-04.ll
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@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
define i128 @f1(<2 x i64> %a) {
; CHECK-LABEL: f1:

4
llvm/test/MC/Disassembler/SystemZ/insns-arch15.txt → llvm/test/MC/Disassembler/SystemZ/insns-z17.txt
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@ -1,5 +1,5 @@
# Test arch15 instructions that don't have PC-relative operands.
# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=arch15 \
# Test z17 instructions that don't have PC-relative operands.
# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z17 \
# RUN: | FileCheck %s
# CHECK: bdepg %r0, %r0, %r0

4
llvm/test/MC/SystemZ/insn-bad-arch15.s → llvm/test/MC/SystemZ/insn-bad-z17.s
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@ -1,5 +1,5 @@
# For arch15 only.
# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=arch15 < %s 2> %t
# For z17 only.
# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z17 < %s 2> %t
# RUN: FileCheck < %t %s
#CHECK: error: invalid use of indexed addressing

4
llvm/test/MC/SystemZ/insn-good-arch15.s → llvm/test/MC/SystemZ/insn-good-z17.s
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@ -1,5 +1,5 @@
# For arch15 and above.
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch15 -show-encoding %s \
# For z17 and above.
# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z17 -show-encoding %s \
# RUN: | FileCheck %s
#CHECK: bdepg %r0, %r0, %r0 # encoding: [0xb9,0x6d,0x00,0x00]

2
llvm/test/Transforms/SLPVectorizer/SystemZ/revec-fix-128169.ll
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@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=s390x-unknown-linux-gnu -mcpu=arch15 -passes=slp-vectorizer -S -slp-revec %s | FileCheck %s
; RUN: opt -mtriple=s390x-unknown-linux-gnu -mcpu=z17 -passes=slp-vectorizer -S -slp-revec %s | FileCheck %s
define void @e(<4 x i16> %0) {
; CHECK-LABEL: @e(

2
llvm/unittests/TargetParser/Host.cpp
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@ -348,7 +348,7 @@ TEST(getLinuxHostCPUName, s390x) {
// Model Id: 9175
ExpectedCPUs.push_back("zEC12");
ExpectedCPUs.push_back("arch15");
ExpectedCPUs.push_back("z17");
// Model Id: 3931
ExpectedCPUs.push_back("zEC12");