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AMDGPU/GlobalISel: Implement select for 32-bit G_ADD

Browse Source 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58804

llvm-svn: 364797
This commit is contained in:
Tom Stellard 2019-07-01 16:09:33 +00:00
parent 8b2e304bc5
commit 9e9dd30de3
3 changed files with 50 additions and 2 deletions
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3
llvm/lib/Target/AMDGPU/AMDGPUGISel.td
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@ -128,6 +128,9 @@ multiclass GISelVop2IntrPat <
def : GISelSop2Pat <or, S_OR_B32, i32>;
def : GISelVop2Pat <or, V_OR_B32_e32, i32>;
def : GISelSop2Pat <add, S_ADD_I32, i32>;
def : GISelVop2Pat <add, V_ADD_I32_e32, i32>;
def : GISelSop2Pat <sra, S_ASHR_I32, i32>;
let AddedComplexity = 100 in {
let SubtargetPredicate = isGFX6GFX7 in {

6
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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@ -1056,10 +1056,12 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
}
switch (I.getOpcode()) {
case TargetOpcode::G_ADD:
if (selectG_ADD(I))
return true;
LLVM_FALLTHROUGH;
default:
return selectImpl(I, CoverageInfo);
case TargetOpcode::G_ADD:
return selectG_ADD(I);
case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_BITCAST:
return selectCOPY(I);

43
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir Normal file
View File

@ -0,0 +1,43 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
---
name: add_i32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GCN-LABEL: name: add_i32
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GCN: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_ADD_I32_]], [[COPY2]], implicit-def $vcc, implicit $exec
; GCN: [[V_ADD_I32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_ADD_I32_]], [[V_ADD_I32_e32_]], implicit-def $vcc, implicit $exec
; GCN: [[V_ADD_I32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[V_ADD_I32_e32_1]], [[COPY2]], implicit-def $vcc, implicit $exec
; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_ADD_I32_e32_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:vgpr(s32) = COPY $vgpr0
%3:vgpr(p1) = COPY $vgpr3_vgpr4
%4:sgpr(s32) = G_CONSTANT i32 1
%5:sgpr(s32) = G_CONSTANT i32 4096
; add ss
%6:sgpr(s32) = G_ADD %0, %1
; add vs
%7:vgpr(s32) = G_ADD %2, %6
; add sv
%8:vgpr(s32) = G_ADD %6, %7
; add vv
%9:vgpr(s32) = G_ADD %8, %2
G_STORE %9, %3 :: (store 4, addrspace 1)
...