[llvm-mca] Remove redundant namespace prefixes. NFC

We are already "using" namespace llvm in all the files modified by this change.

llvm-svn: 343312

llvm/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp

@@ -24,8 +24,8 @@ using namespace llvm;
 
 namespace mca {
 
-RegisterFile::RegisterFile(const llvm::MCSchedModel &SM,
+RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
-                           const llvm::MCRegisterInfo &mri, unsigned NumRegs)
+                           unsigned NumRegs)
     : MRI(mri),
       RegisterMappings(mri.getNumRegs(), {WriteRef(), RegisterRenamingInfo()}),
       ZeroRegisters(mri.getNumRegs(), false) {
@@ -281,7 +281,7 @@ void RegisterFile::collectWrites(SmallVectorImpl<WriteRef> &Writes,
   }
 
   // Remove duplicate entries and resize the input vector.
-  llvm::sort(Writes, [](const WriteRef &Lhs, const WriteRef &Rhs) {
+  sort(Writes, [](const WriteRef &Lhs, const WriteRef &Rhs) {
     return Lhs.getWriteState() < Rhs.getWriteState();
   });
   auto It = std::unique(Writes.begin(), Writes.end());

llvm/tools/llvm-mca/lib/HardwareUnits/ResourceManager.cpp

@@ -35,10 +35,10 @@ void DefaultResourceStrategy::skipMask(uint64_t Mask) {
 
 uint64_t DefaultResourceStrategy::select(uint64_t ReadyMask) {
   // This method assumes that ReadyMask cannot be zero.
-  uint64_t CandidateMask = llvm::PowerOf2Floor(NextInSequenceMask);
+  uint64_t CandidateMask = PowerOf2Floor(NextInSequenceMask);
   while (!(ReadyMask & CandidateMask)) {
     skipMask(CandidateMask);
-    CandidateMask = llvm::PowerOf2Floor(NextInSequenceMask);
+    CandidateMask = PowerOf2Floor(NextInSequenceMask);
   }
   return CandidateMask;
 }
@@ -55,8 +55,8 @@ ResourceState::ResourceState(const MCProcResourceDesc &Desc, unsigned Index,
                              uint64_t Mask)
     : ProcResourceDescIndex(Index), ResourceMask(Mask),
       BufferSize(Desc.BufferSize) {
-  if (llvm::countPopulation(ResourceMask) > 1)
+  if (countPopulation(ResourceMask) > 1)
-    ResourceSizeMask = ResourceMask ^ llvm::PowerOf2Floor(ResourceMask);
+    ResourceSizeMask = ResourceMask ^ PowerOf2Floor(ResourceMask);
   else
     ResourceSizeMask = (1ULL << Desc.NumUnits) - 1;
   ReadyMask = ResourceSizeMask;
@@ -66,7 +66,7 @@ ResourceState::ResourceState(const MCProcResourceDesc &Desc, unsigned Index,
 
 bool ResourceState::isReady(unsigned NumUnits) const {
   return (!isReserved() || isADispatchHazard()) &&
-         llvm::countPopulation(ReadyMask) >= NumUnits;
+         countPopulation(ReadyMask) >= NumUnits;
 }
 
 ResourceStateEvent ResourceState::isBufferAvailable() const {
@@ -87,7 +87,7 @@ void ResourceState::dump() const {
 #endif
 
 static unsigned getResourceStateIndex(uint64_t Mask) {
-  return std::numeric_limits<uint64_t>::digits - llvm::countLeadingZeros(Mask);
+  return std::numeric_limits<uint64_t>::digits - countLeadingZeros(Mask);
 }
 
 static std::unique_ptr<ResourceStrategy>

llvm/tools/llvm-mca/lib/HardwareUnits/RetireControlUnit.cpp

@@ -21,7 +21,7 @@ using namespace llvm;
 
 namespace mca {
 
-RetireControlUnit::RetireControlUnit(const llvm::MCSchedModel &SM)
+RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
     : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
       AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0) {
   // Check if the scheduling model provides extra information about the machine

llvm/tools/llvm-mca/lib/InstrBuilder.cpp

@@ -64,8 +64,7 @@ static void initializeUsedResources(InstrDesc &ID,
 
   // Sort elements by mask popcount, so that we prioritize resource units over
   // resource groups, and smaller groups over larger groups.
-  llvm::sort(Worklist,
+  sort(Worklist, [](const ResourcePlusCycles &A, const ResourcePlusCycles &B) {
-             [](const ResourcePlusCycles &A, const ResourcePlusCycles &B) {
     unsigned popcntA = countPopulation(A.first);
     unsigned popcntB = countPopulation(B.first);
     if (popcntA < popcntB)
@@ -351,7 +350,7 @@ InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
   const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
   if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
     std::string ToString;
-    llvm::raw_string_ostream OS(ToString);
+    raw_string_ostream OS(ToString);
     WithColor::error() << "found an unsupported instruction in the input"
                        << " assembly sequence.\n";
     MCIP.printInst(&MCI, OS, "", STI);

llvm/tools/llvm-mca/lib/Instruction.cpp

@@ -133,7 +133,7 @@ void Instruction::execute() {
 void Instruction::update() {
   assert(isDispatched() && "Unexpected instruction stage found!");
 
-  if (!llvm::all_of(Uses, [](const UniqueUse &Use) { return Use->isReady(); }))
+  if (!all_of(Uses, [](const UniqueUse &Use) { return Use->isReady(); }))
     return;
 
   // A partial register write cannot complete before a dependent write.
@@ -147,7 +147,7 @@ void Instruction::update() {
     return true;
   };
 
-  if (llvm::all_of(Defs, IsDefReady))
+  if (all_of(Defs, IsDefReady))
     Stage = IS_READY;
 }
 

llvm/tools/llvm-mca/lib/Pipeline.cpp

@@ -31,26 +31,26 @@ void Pipeline::addEventListener(HWEventListener *Listener) {
 }
 
 bool Pipeline::hasWorkToProcess() {
-  return llvm::any_of(Stages, [](const std::unique_ptr<Stage> &S) {
+  return any_of(Stages, [](const std::unique_ptr<Stage> &S) {
     return S->hasWorkToComplete();
   });
 }
 
-llvm::Error Pipeline::run() {
+Error Pipeline::run() {
   assert(!Stages.empty() && "Unexpected empty pipeline found!");
 
   while (hasWorkToProcess()) {
     notifyCycleBegin();
-    if (llvm::Error Err = runCycle())
+    if (Error Err = runCycle())
       return Err;
     notifyCycleEnd();
     ++Cycles;
   }
-  return llvm::ErrorSuccess();
+  return ErrorSuccess();
 }
 
-llvm::Error Pipeline::runCycle() {
+Error Pipeline::runCycle() {
-  llvm::Error Err = llvm::ErrorSuccess();
+  Error Err = ErrorSuccess();
   // Update stages before we start processing new instructions.
   for (auto I = Stages.rbegin(), E = Stages.rend(); I != E && !Err; ++I) {
     const std::unique_ptr<Stage> &S = *I;

llvm/tools/llvm-mca/lib/Stages/DispatchStage.cpp

@@ -85,7 +85,7 @@ void DispatchStage::updateRAWDependencies(ReadState &RS,
   }
 }
 
-llvm::Error DispatchStage::dispatch(InstRef IR) {
+Error DispatchStage::dispatch(InstRef IR) {
   assert(!CarryOver && "Cannot dispatch another instruction!");
   Instruction &IS = *IR.getInstruction();
   const InstrDesc &Desc = IS.getDesc();
@@ -128,10 +128,10 @@ llvm::Error DispatchStage::dispatch(InstRef IR) {
   return moveToTheNextStage(IR);
 }
 
-llvm::Error DispatchStage::cycleStart() {
+Error DispatchStage::cycleStart() {
   if (!CarryOver) {
     AvailableEntries = DispatchWidth;
-    return llvm::ErrorSuccess();
+    return ErrorSuccess();
   }
 
   AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
@@ -143,7 +143,7 @@ llvm::Error DispatchStage::cycleStart() {
   notifyInstructionDispatched(CarriedOver, RegisterFiles, DispatchedOpcodes);
   if (!CarryOver)
     CarriedOver = InstRef();
-  return llvm::ErrorSuccess();
+  return ErrorSuccess();
 }
 
 bool DispatchStage::isAvailable(const InstRef &IR) const {
@@ -157,7 +157,7 @@ bool DispatchStage::isAvailable(const InstRef &IR) const {
   return canDispatch(IR);
 }
 
-llvm::Error DispatchStage::execute(InstRef &IR) {
+Error DispatchStage::execute(InstRef &IR) {
   assert(canDispatch(IR) && "Cannot dispatch another instruction!");
   return dispatch(IR);
 }

llvm/tools/llvm-mca/lib/Stages/ExecuteStage.cpp

@@ -85,9 +85,9 @@ Error ExecuteStage::issueReadyInstructions() {
 }
 
 Error ExecuteStage::cycleStart() {
-  llvm::SmallVector<ResourceRef, 8> Freed;
+  SmallVector<ResourceRef, 8> Freed;
-  llvm::SmallVector<InstRef, 4> Executed;
+  SmallVector<InstRef, 4> Executed;
-  llvm::SmallVector<InstRef, 4> Ready;
+  SmallVector<InstRef, 4> Ready;
 
   HWS.cycleEvent(Freed, Executed, Ready);