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[LoongArch] Pre-commit test for vreplgr2vr + vinsgr2vr intrinsics (#115702)

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Inspired by https://github.com/llvm/llvm-project/issues/101624.

A later commit will optimize it.
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ZhaoQi 2024-11-12 10:27:37 +08:00 committed by GitHub
parent de2fad3251
commit aad256598d
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39
llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl-ins-gr2vr.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define <8 x i32> @xvrepl_ins_w(i32 %a, i32 %b) {
; CHECK-LABEL: xvrepl_ins_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 0
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 1
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 2
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 3
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 4
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 5
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 6
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 7
; CHECK-NEXT: ret
entry:
%0 = call <8 x i32> @llvm.loongarch.lasx.xvreplgr2vr.w(i32 %a)
%1 = call <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32> %0, i32 %b, i32 1)
ret <8 x i32> %1
}
define <4 x i64> @xvrepl_ins_d(i64 %a, i64 %b) {
; CHECK-LABEL: xvrepl_ins_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 0
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 1
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 2
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 3
; CHECK-NEXT: ret
entry:
%0 = call <4 x i64> @llvm.loongarch.lasx.xvreplgr2vr.d(i64 %a)
%1 = call <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64> %0, i64 %b, i32 1)
ret <4 x i64> %1
}
declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32 immarg)
declare <8 x i32> @llvm.loongarch.lasx.xvreplgr2vr.w(i32)
declare <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64>, i64, i32 immarg)
declare <4 x i64> @llvm.loongarch.lasx.xvreplgr2vr.d(i64)

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llvm/test/CodeGen/LoongArch/lsx/intrinsic-repl-ins-gr2vr.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define <16 x i8> @vrepl_ins_b(i32 %a, i32 %b) {
; CHECK-LABEL: vrepl_ins_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 1
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 2
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 3
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 4
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 5
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 6
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 7
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 8
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 9
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 10
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 11
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 12
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 13
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 14
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 15
; CHECK-NEXT: ret
entry:
%0 = call <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32 %a)
%1 = call <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8> %0, i32 %b, i32 1)
ret <16 x i8> %1
}
define <8 x i16> @vrepl_ins_h(i32 %a, i32 %b) {
; CHECK-LABEL: vrepl_ins_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 1
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 2
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 3
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 4
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 5
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 6
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 7
; CHECK-NEXT: ret
entry:
%0 = call <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32 %a)
%1 = call <8 x i16> @llvm.loongarch.lsx.vinsgr2vr.h(<8 x i16> %0, i32 %b, i32 1)
ret <8 x i16> %1
}
define <4 x i32> @vrepl_ins_w(i32 %a, i32 %b) {
; CHECK-LABEL: vrepl_ins_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 1
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 2
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
; CHECK-NEXT: ret
entry:
%0 = call <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32 %a)
%1 = call <4 x i32> @llvm.loongarch.lsx.vinsgr2vr.w(<4 x i32> %0, i32 %b, i32 1)
ret <4 x i32> %1
}
define <2 x i64> @vrepl_ins_d(i64 %a, i64 %b) {
; CHECK-LABEL: vrepl_ins_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 1
; CHECK-NEXT: ret
entry:
%0 = call <2 x i64> @llvm.loongarch.lsx.vreplgr2vr.d(i64 %a)
%1 = call <2 x i64> @llvm.loongarch.lsx.vinsgr2vr.d(<2 x i64> %0, i64 %b, i32 1)
ret <2 x i64> %1
}
declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32 immarg)
declare <16 x i8> @llvm.loongarch.lsx.vreplgr2vr.b(i32)
declare <8 x i16> @llvm.loongarch.lsx.vinsgr2vr.h(<8 x i16>, i32, i32 immarg)
declare <8 x i16> @llvm.loongarch.lsx.vreplgr2vr.h(i32)
declare <4 x i32> @llvm.loongarch.lsx.vinsgr2vr.w(<4 x i32>, i32, i32 immarg)
declare <4 x i32> @llvm.loongarch.lsx.vreplgr2vr.w(i32)
declare <2 x i64> @llvm.loongarch.lsx.vinsgr2vr.d(<2 x i64>, i64, i32 immarg)
declare <2 x i64> @llvm.loongarch.lsx.vreplgr2vr.d(i64)