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[RISCV] Improve Errors for X1/X5/X1X5 Reg Classes (#126184)

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LLVM has functionality for producing a register-class-specific error
message in the assembly parser, rather than just emitting the generic
"invalid operand for instruction" error.

This starts the gradual adoption of this functionality for RISC-V, with
some lesser-used shadow-stack register classes:
- GPRX1 (only contains `ra`)
- GPRX5 (only contains `t0`)
- GPRX1X5 (only contains `ra` and `t0`)

LLVM is reasonably conservative about when these errors are used, in
particular you have to have all the features for the relevant mnemonic
enabled before it will do, hence the test updates.

This also merges a pair of almost identical rv32/rv64 test files into a
single file with one run line.
This commit is contained in:
Sam Elliott 2025-02-09 21:35:32 -08:00 committed by GitHub
parent 70fdd9f0a2
commit aebe6c5d7f
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GPG Key ID: B5690EEEBB952194
4 changed files with 33 additions and 37 deletions
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17
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
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@ -247,8 +247,16 @@ def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17),
(sequence "X%u", 0, 4))>;
def GPRX0 : GPRRegisterClass<(add X0)>;
def GPRX1 : GPRRegisterClass<(add X1)>;
def GPRX5 : GPRRegisterClass<(add X5)>;
def GPRX1 : GPRRegisterClass<(add X1)> {
let DiagnosticType = "InvalidRegClassGPRX1";
let DiagnosticString = "register must be ra (x1)";
}
def GPRX5 : GPRRegisterClass<(add X5)> {
let DiagnosticType = "InvalidRegClassGPRX5";
let DiagnosticString = "register must be t0 (x5)";
}
def GPRNoX0 : GPRRegisterClass<(sub GPR, X0)>;
@ -282,7 +290,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
def GPRX1X5 : GPRRegisterClass<(add X1, X5)>;
def GPRX1X5 : GPRRegisterClass<(add X1, X5)> {
let DiagnosticType = "InvalidRegClassGPRX1X5";
let DiagnosticString = "register must be ra or t0 (x1 or x5)";
}
//===----------------------------------------------------------------------===//
// Even-Odd GPR Pairs

17
llvm/test/MC/RISCV/rv32zicfiss-invalid.s
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@ -1,17 +0,0 @@
# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+c -M no-aliases -show-encoding \
# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
# CHECK-ERR: error: invalid operand for instruction
sspopchk a1
# CHECK-ERR: error: invalid operand for instruction
c.sspush t0
# CHECK-ERR: error: invalid operand for instruction
c.sspopchk ra
# CHECK-ERR: error: invalid operand for instruction
sspush a0
# CHECK-ERR: error: invalid operand for instruction
ssrdp zero

17
llvm/test/MC/RISCV/rv64zicfiss-invalid.s
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@ -1,17 +0,0 @@
# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+c -M no-aliases -show-encoding \
# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
# CHECK-ERR: error: invalid operand for instruction
sspopchk a1
# CHECK-ERR: error: invalid operand for instruction
c.sspush t0
# CHECK-ERR: error: invalid operand for instruction
c.sspopchk ra
# CHECK-ERR: error: invalid operand for instruction
sspush a0
# CHECK-ERR: error: invalid operand for instruction
ssrdp zero

19
llvm/test/MC/RISCV/zicfiss-invalid.s Normal file
View File

@ -0,0 +1,19 @@
# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+zcmop,+c -M no-aliases -show-encoding \
# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+zcmop,+c -M no-aliases -show-encoding \
# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
# CHECK-ERR: error: register must be ra or t0 (x1 or x5)
sspopchk a1
# CHECK-ERR: error: register must be ra (x1)
c.sspush t0
# CHECK-ERR: error: register must be t0 (x5)
c.sspopchk ra
# CHECK-ERR: error: register must be ra or t0 (x1 or x5)
sspush a0
# CHECK-ERR: error: invalid operand for instruction
ssrdp zero