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[RISCV] Add support for XCVbi extension in CV32E40P

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Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @paolos, @simoncook, @xmj.

bf2ad26b4ff856aab9a62ad168e6bdefeedc374f originally commited.
e4777dc4b9cb371971523cc603e1b8a5c7255e7e reverted due to test failures caused by a merge conflict marker in llvm/test/CodeGen/RISCV/attributes that was accidentally checked in.
This commit removed the conflict marker and recommitted.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154412
This commit is contained in:
melonedo 2023-07-28 21:32:46 +08:00
parent 37ca2f56e0
commit afb9c04a5a
9 changed files with 152 additions and 0 deletions
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3
llvm/docs/RISCVUsage.rst
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@ -277,5 +277,8 @@ The current vendor extensions supported are:
``XCVsimd``
LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification.
``XCVbi``
LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
``XSfcie``
LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive. All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.

1
llvm/lib/Support/RISCVISAInfo.cpp
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@ -67,6 +67,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
// vendor-defined ('X') extensions
{"xcvalu", RISCVExtensionVersion{1, 0}},
{"xcvbi", RISCVExtensionVersion{1, 0}},
{"xcvbitmanip", RISCVExtensionVersion{1, 0}},
{"xcvmac", RISCVExtensionVersion{1, 0}},
{"xcvsimd", RISCVExtensionVersion{1, 0}},

2
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
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@ -569,6 +569,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
"CORE-V ALU custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableCoreVSIMD32,
"CORE-V SIMD extensions custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
"CORE-V Immediate Branching custom opcode table");
TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
return MCDisassembler::Fail;

7
llvm/lib/Target/RISCV/RISCVFeatures.td
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@ -816,6 +816,13 @@ def HasVendorXCVsimd
AssemblerPredicate<(any_of FeatureVendorXCVsimd),
"'XCVsimd' (CORE-V SIMD ALU)">;
def FeatureVendorXCVbi
: SubtargetFeature<"xcvbi", "HasVendorXCVbi", "true",
"'XCVbi' (CORE-V Immediate Branching)">;
def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">,
AssemblerPredicate<(all_of FeatureVendorXCVbi),
"'XCVbi' (CORE-V Immediate Branching)">;
//===----------------------------------------------------------------------===//
// LLVM specific features and extensions
//===----------------------------------------------------------------------===//

19
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
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@ -519,3 +519,22 @@ let Predicates = [HasVendorXCVsimd, IsRV32],
def CV_SUB_DIV4 : CVSIMDRR<0b01110, 1, 0, 0b100, "cv.sub.div4">;
def CV_SUB_DIV8 : CVSIMDRR<0b01110, 1, 0, 0b110, "cv.sub.div8">;
}
class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
string opcodestr, string argstr>
: RVInstB<funct3, OPC_CUSTOM_0, outs, ins, opcodestr, argstr> {
bits<5> imm5;
let rs2 = imm5;
let DecoderNamespace = "XCVbi";
}
let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, isBranch = 1, isTerminator = 1 in {
// Immediate branching operations
def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
(ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
"cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
def CV_BNEIMM : CVInstImmBranch<0b111, (outs),
(ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
"cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
}

2
llvm/test/CodeGen/RISCV/attributes.ll
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@ -45,6 +45,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvmac %s -o - | FileCheck --check-prefix=RV32XCVMAC %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvsimd %s -o - | FileCheck --check-prefix=RV32XCVSIMD %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvbi %s -o - | FileCheck --check-prefix=RV32XCVBI %s
; RUN: llc -mtriple=riscv32 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV32XTHEADCMO %s
; RUN: llc -mtriple=riscv32 -mattr=+xtheadcondmov %s -o - | FileCheck --check-prefix=RV32XTHEADCONDMOV %s
; RUN: llc -mtriple=riscv32 -mattr=+xtheadfmemidx %s -o - | FileCheck --check-prefix=RV32XTHEADFMEMIDX %s
@ -220,6 +221,7 @@
; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
; RV32XCVMAC: .attribute 5, "rv32i2p1_xcvmac1p0"
; RV32XCVSIMD: .attribute 5, "rv32i2p1_xcvsimd1p0"
; RV32XCVBI: .attribute 5, "rv32i2p1_xcvbi1p0"
; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"

3
llvm/test/MC/RISCV/attribute-arch.s
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@ -296,3 +296,6 @@
.attribute arch, "rv32i_xcvsimd"
# CHECK: attribute 5, "rv32i2p1_xcvsimd1p0"
.attribute arch, "rv32i_xcvbi"
# CHECK: attribute 5, "rv32i2p1_xcvbi1p0"

58
llvm/test/MC/RISCV/corev/XCVbi-invalid.s Normal file
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@ -0,0 +1,58 @@
# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvbi %s 2>&1 \
# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
//===----------------------------------------------------------------------===//
// cv.beqimm
//===----------------------------------------------------------------------===//
cv.beqimm 0, 0, 0
# CHECK-ERROR: invalid operand for instruction
cv.beqimm t0, t1, 0
# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
cv.beqimm t0, 0, t1
# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
cv.beqimm t0, 16, 0
# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
cv.beqimm t0, -17, 0
# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
cv.beqimm t0, 0, 1
# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
cv.beqimm t0, 0, 4096
# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
cv.beqimm t0, 0, -4098
# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
//===----------------------------------------------------------------------===//
// cv.bneimm
//===----------------------------------------------------------------------===//
cv.bneimm 0, 0, 0
# CHECK-ERROR: invalid operand for instruction
cv.bneimm t0, t1, 0
# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
cv.bneimm t0, 0, t1
# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
cv.bneimm t0, 16, 0
# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
cv.bneimm t0, -17, 0
# CHECK-ERROR: immediate must be an integer in the range [-16, 15]
cv.bneimm t0, 0, 1
# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
cv.bneimm t0, 0, 4096
# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]
cv.bneimm t0, 0, -4098
# CHECK-ERROR: immediate must be a multiple of 2 bytes in the range [-4096, 4094]

57
llvm/test/MC/RISCV/corev/XCVbi.s Normal file
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@ -0,0 +1,57 @@
# RUN: llvm-mc -triple=riscv32 --mattr=+xcvbi -show-encoding %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvbi < %s \
# RUN: | llvm-objdump --mattr=+xcvbi -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-OBJDUMP %s
# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s
//===----------------------------------------------------------------------===//
// cv.beqimm
//===----------------------------------------------------------------------===//
label1:
cv.beqimm t0, 0, 0
# CHECK-INSTR: cv.beqimm t0, 0, 0
# CHECK-OBJDUMP: cv.beqimm t0, 0, 0x0 <label1>
# CHECK-ENCODING: [0x0b,0xe0,0x02,0x00]
# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}
cv.beqimm a0, 5, 42
# CHECK-INSTR: cv.beqimm a0, 5, 42
# CHECK-OBJDUMP: cv.beqimm a0, 5, 0x2e <label2+0x22>
# CHECK-ENCODING: [0x0b,0x65,0x55,0x02]
# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}
cv.beqimm a0, -5, label1
# CHECK-INSTR: cv.beqimm a0, -5, label1
# CHECK-OBJDUMP: cv.beqimm a0, -5, 0x0 <label1>
# CHECK-ENCODING: [0x0b'A',0x60'A',0xb5'A',0x01'A']
# CHECK-ENCODING: fixup A - offset: 0, value: label1, kind: fixup_riscv_branch
# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}
//===----------------------------------------------------------------------===//
// cv.bneimm
//===----------------------------------------------------------------------===//
label2:
cv.bneimm t0, 0, 0
# CHECK-INSTR: cv.bneimm t0, 0, 0
# CHECK-OBJDUMP: cv.bneimm t0, 0, 0xc <label2>
# CHECK-ENCODING: [0x0b,0xf0,0x02,0x00]
# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}
cv.bneimm a0, 5, 42
# CHECK-INSTR: cv.bneimm a0, 5, 42
# CHECK-OBJDUMP: cv.bneimm a0, 5, 0x3a <label2+0x2e>
# CHECK-ENCODING: [0x0b,0x75,0x55,0x02]
# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}
cv.bneimm a0, -5, label2
# CHECK-INSTR: cv.bneimm a0, -5, label2
# CHECK-OBJDUMP: cv.bneimm a0, -5, 0xc <label2>
# CHECK-ENCODING: [0x0b'A',0x70'A',0xb5'A',0x01'A']
# CHECK-ENCODING: fixup A - offset: 0, value: label2, kind: fixup_riscv_branch
# CHECK-NO-EXT: instruction requires the following: 'XCVbi' (CORE-V Immediate Branching){{$}}