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[AMDGPU] Set Convergent property for image.(getlod/sample*) intrinsics which uses WQM (#122908)
This change adds IntrConvergent property to image.getlod intrinsic and to several image.sample intrinsics. All image.sample intrinsics apart from LOD(_L), Level 0(_LZ), Derivative(_D) will be marked as Convergent.
This commit is contained in:
Mariusz Sikora
GitHub
parent
04b002bbb8
commit
b3924cb9ec
@ -876,6 +876,8 @@ class AMDGPUSampleVariant<string ucmod, string lcmod, list<AMDGPUArg> extra_addr
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// Name of the {lod} or {clamp} argument that is appended to the coordinates,
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// if any.
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string LodOrClamp = "";
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bit UsesWQM = false;
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}
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// AMDGPUSampleVariants: all variants supported by IMAGE_SAMPLE
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@ -905,8 +907,9 @@ defset list<AMDGPUSampleVariant> AMDGPUSampleVariants = {
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}
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defset list<AMDGPUSampleVariant> AMDGPUSampleVariantsNoGradients = {
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let UsesWQM = true in
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defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"", "", []>;
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let Bias = true in
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let Bias = true, UsesWQM = true in
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defm AMDGPUSample : AMDGPUSampleHelper_Clamp<
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"_B", "_b", [AMDGPUArg<llvm_anyfloat_ty, "bias">]>;
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let LodOrClamp = "lod" in
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@ -1172,7 +1175,8 @@ defset list<AMDGPUImageDimIntrinsic> AMDGPUImageDimIntrinsics = {
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foreach dim = AMDGPUDims.NoMsaa in {
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def !strconcat(NAME, "_", dim.Name) : AMDGPUImageDimIntrinsic<
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AMDGPUDimSampleProfile<opmod, dim, sample>,
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!if(NoMem, [IntrNoMem], [IntrReadMem]),
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!listconcat(!if(NoMem, [IntrNoMem], [IntrReadMem]),
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!if(sample.UsesWQM, [IntrConvergent], [])),
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!if(NoMem, [], [SDNPMemOperand])>;
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}
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}
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@ -1188,7 +1192,8 @@ defset list<AMDGPUImageDimIntrinsic> AMDGPUImageDimIntrinsics = {
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foreach dim = AMDGPUDims.NoMsaa in {
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def !strconcat(NAME, "_", dim.Name, "_nortn") : AMDGPUImageDimIntrinsic<
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AMDGPUDimSampleNoReturnProfile<opmod, dim, sample>,
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[IntrWillReturn], [SDNPMemOperand]>;
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!listconcat([IntrWillReturn], !if(sample.UsesWQM, [IntrConvergent], [])),
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[SDNPMemOperand]>;
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}
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}
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foreach sample = AMDGPUSampleVariants in {
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@ -1,34 +1,143 @@
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; Test that image.sample instruction is sunk across the branch and not left in the first block. Since the kill may terminate the shader there might be no need for sampling the image.
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; Test that image.sample LOD(_L), Level 0(_LZ), Derivative(_D) instructions are sunk across the branch and not left in the first block. Since the kill may terminate the shader there might be no need for sampling the image.
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; GCN-LABEL: {{^}}sinking_img_sample:
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; GCN-NOT: image_sample
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; GCN-NOT: image_sample_l v
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; GCN-NOT: image_sample_lz v
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; GCN-NOT: image_sample_c_lz v
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; GCN-NOT: image_sample_c_l v
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; GCN-NOT: image_sample_d v
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; GCN-NOT: image_sample_c_d v
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; GCN-NOT: image_sample_d_cl v
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; GCN-NOT: image_sample_c_d_cl v
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; GCN: branch
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; GCN: image_sample
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; GCN: image_sample_l v
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; GCN: image_sample_lz v
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; GCN: image_sample_c_lz v
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; GCN: image_sample_c_l v
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; GCN: image_sample_d v
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; GCN: image_sample_c_d v
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; GCN: image_sample_d_cl v
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; GCN: image_sample_c_d_cl v
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; GCN: exp null
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define amdgpu_ps float @sinking_img_sample() {
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define amdgpu_ps float @sinking_img_sample(i1 %cond) {
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main_body:
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%i = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
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br i1 undef, label %endif1, label %if1
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%i1 = call <3 x float> @llvm.amdgcn.image.sample.l.2d.v3f32.f32(i32 7, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i2 = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i3 = call <3 x float> @llvm.amdgcn.image.sample.c.lz.2d.v3f32.f32(i32 7, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i4 = call <3 x float> @llvm.amdgcn.image.sample.c.l.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i5 = call <3 x float> @llvm.amdgcn.image.sample.d.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i6 = call <3 x float> @llvm.amdgcn.image.sample.c.d.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i7 = call <3 x float> @llvm.amdgcn.image.sample.d.cl.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i8 = call <3 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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br i1 %cond, label %endif1, label %if1
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if1: ; preds = %main_body
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call void @llvm.amdgcn.kill(i1 false) #4
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br label %exit
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endif1: ; preds = %main_body
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%i22 = extractelement <3 x float> %i, i32 2
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%i22 = extractelement <3 x float> %i1, i32 1
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%i23 = call nsz arcp contract float @llvm.fma.f32(float %i22, float 0.000000e+00, float 0.000000e+00) #1
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%i24 = extractelement <3 x float> %i2, i32 1
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%i25 = call nsz arcp contract float @llvm.fma.f32(float %i23, float %i24, float 0.000000e+00) #1
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%i26 = extractelement <3 x float> %i3, i32 1
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%i27 = call nsz arcp contract float @llvm.fma.f32(float %i25, float %i26, float 0.000000e+00) #1
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%i28 = extractelement <3 x float> %i4, i32 1
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%i29 = call nsz arcp contract float @llvm.fma.f32(float %i27, float %i28, float 0.000000e+00) #1
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%i30 = extractelement <3 x float> %i5, i32 1
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%i31 = call nsz arcp contract float @llvm.fma.f32(float %i29, float %i30, float 0.000000e+00) #1
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%i32 = extractelement <3 x float> %i6, i32 1
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%i33 = call nsz arcp contract float @llvm.fma.f32(float %i31, float %i32, float 0.000000e+00) #1
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%i34 = extractelement <3 x float> %i7, i32 1
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%i35 = call nsz arcp contract float @llvm.fma.f32(float %i33, float %i34, float 0.000000e+00) #1
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%i36 = extractelement <3 x float> %i8, i32 1
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%i37 = call nsz arcp contract float @llvm.fma.f32(float %i35, float %i36, float 0.000000e+00) #1
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br label %exit
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exit: ; preds = %endif1, %if1
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%i24 = phi float [ undef, %if1 ], [ %i23, %endif1 ]
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ret float %i24
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%i38 = phi float [ poison, %if1 ], [ %i37, %endif1 ]
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ret float %i38
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}
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; Test that image.sample instructions which use WQM are marked as Convergent and will be left in the first block.
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; GCN-LABEL: {{^}}no_sinking_img_sample:
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; GCN: image_sample v
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; GCN: image_sample_c v
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; GCN: image_sample_cl v
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; GCN: image_sample_c_cl v
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; GCN: image_sample_b v
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; GCN: image_sample_c_b v
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; GCN: image_sample_b_cl v
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; GCN: branch
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; GCN-NOT: image_sample v
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; GCN-NOT: image_sample_c v
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; GCN-NOT: image_sample_cl v
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; GCN-NOT: image_sample_c_cl v
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; GCN-NOT: image_sample_b v
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; GCN-NOT: image_sample_c_b v
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; GCN-NOT: image_sample_b_cl v
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; GCN: exp null
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define amdgpu_ps float @no_sinking_img_sample(i1 %cond) {
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main_body:
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%i1 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i2 = call <3 x float> @llvm.amdgcn.image.sample.c.2d.v3f32.f32(i32 7, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i3 = call <3 x float> @llvm.amdgcn.image.sample.cl.2d.v3f32.f32(i32 7, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i4 = call <3 x float> @llvm.amdgcn.image.sample.c.cl.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i5 = call <3 x float> @llvm.amdgcn.image.sample.b.2d.v3f32.f32(i32 7, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i6 = call <3 x float> @llvm.amdgcn.image.sample.c.b.2d.v3f32.f32(i32 7, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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%i7 = call <3 x float> @llvm.amdgcn.image.sample.b.cl.2d.v3f32.f32.f32(i32 7, float poison, float poison, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
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br i1 %cond, label %endif1, label %if1
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if1: ; preds = %main_body
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call void @llvm.amdgcn.kill(i1 false) #4
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br label %exit
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endif1: ; preds = %main_body
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%i22 = extractelement <3 x float> %i1, i32 2
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%i23 = call nsz arcp contract float @llvm.fma.f32(float %i22, float 0.000000e+00, float 0.000000e+00) #1
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%i24 = extractelement <3 x float> %i2, i32 2
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%i25 = call nsz arcp contract float @llvm.fma.f32(float %i23, float %i24, float 0.000000e+00) #1
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%i26 = extractelement <3 x float> %i3, i32 2
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%i27 = call nsz arcp contract float @llvm.fma.f32(float %i25, float %i26, float 0.000000e+00) #1
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%i28 = extractelement <3 x float> %i4, i32 2
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%i29 = call nsz arcp contract float @llvm.fma.f32(float %i27, float %i28, float 0.000000e+00) #1
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%i30 = extractelement <3 x float> %i5, i32 2
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%i31 = call nsz arcp contract float @llvm.fma.f32(float %i29, float %i30, float 0.000000e+00) #1
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%i32 = extractelement <3 x float> %i6, i32 2
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%i33 = call nsz arcp contract float @llvm.fma.f32(float %i31, float %i32, float 0.000000e+00) #1
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%i34 = extractelement <3 x float> %i7, i32 2
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%i35 = call nsz arcp contract float @llvm.fma.f32(float %i33, float %i34, float 0.000000e+00) #1
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br label %exit
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exit: ; preds = %endif1, %if1
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%i36 = phi float [ poison, %if1 ], [ %i35, %endif1 ]
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ret float %i36
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}
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; Function Attrs: nounwind readonly willreturn
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declare <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.c.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.cl.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.c.cl.2d.v3f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.b.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.c.b.2d.v3f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.b.cl.2d.v3f32.f32.(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v3f32.f32(i32 immarg, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.l.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.c.lz.2d.v3f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.c.l.2d.v3f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.d.2d.v3f32.f32.f32(i32 immarg, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.c.d.2d.v3f32.f32.f32(i32 immarg, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.d.cl.2d.v3f32.f32.f32(i32 immarg, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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declare <3 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v3f32.f32.f32(i32 immarg, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #3
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; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
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declare float @llvm.fma.f32(float, float, float) #2
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