From b51cdfaddab2d19dca5a7b44988a0dfae166e24b Mon Sep 17 00:00:00 2001 From: Misha Brukman Date: Wed, 7 Jan 2009 23:07:29 +0000 Subject: [PATCH] Fix off-by-one error in traversing an array; this fixes a test. The error was reported by gcc-4.3.0 during compilation. llvm-svn: 61896 --- llvm/lib/Target/CellSPU/SPUInstrInfo.cpp | 2 +- llvm/test/CodeGen/CellSPU/shift_ops.ll | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp index 06ad50762f7a..fa6e33b075e8 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -678,7 +678,7 @@ SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl &Cond) unsigned Opc = unsigned(Cond[0].getImm()); // Pretty dull mapping between the two conditions that SPU can generate: - for (int i = sizeof(revconds)/sizeof(revconds[0]); i >= 0; --i) { + for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) { if (revconds[i].Opc == Opc) { Cond[0].setImm(revconds[i].RevCondOpc); return false; diff --git a/llvm/test/CodeGen/CellSPU/shift_ops.ll b/llvm/test/CodeGen/CellSPU/shift_ops.ll index 928e4904b403..5b60dc178fa8 100644 --- a/llvm/test/CodeGen/CellSPU/shift_ops.ll +++ b/llvm/test/CodeGen/CellSPU/shift_ops.ll @@ -16,8 +16,6 @@ ; RUN: grep -w rotqbybi %t1.s | count 1 ; RUN: grep -w sfi %t1.s | count 3 -; XFAIL: alpha|linux|sparc|ia64|arm - target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu"