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Fix subreg value numbers in handleMoveUp
The problem can occur in presence of subregs. If we are swapping two instructions defining different subregs of the same register we will get a new liveout from a block. We need to preserve value number for block's liveout for successor block's livein to match. Differential Revision: https://reviews.llvm.org/D30558 llvm-svn: 297534
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@ -1232,10 +1232,12 @@ private:
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LiveRange::iterator NewIdxIn = NewIdxOut;
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assert(NewIdxIn == LR.find(NewIdx.getBaseIndex()));
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const SlotIndex SplitPos = NewIdxDef;
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OldIdxVNI = OldIdxIn->valno;
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// Merge the OldIdxIn and OldIdxOut segments into OldIdxOut.
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OldIdxOut->valno->def = OldIdxIn->start;
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*OldIdxOut = LiveRange::Segment(OldIdxIn->start, OldIdxOut->end,
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OldIdxIn->valno);
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OldIdxOut->valno);
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// OldIdxIn and OldIdxVNI are now undef and can be overridden.
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// We Slide [NewIdxIn, OldIdxIn) down one position.
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// |- X0/NewIdxIn -| ... |- Xn-1 -||- Xn/OldIdxIn -||- OldIdxOut -|
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@ -382,6 +382,24 @@ TEST(LiveIntervalTest, SubRegMoveDown) {
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});
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}
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TEST(LiveIntervalTest, SubRegMoveUp) {
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// handleMoveUp had a bug not updating valno of segment incoming to bb.2
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// after swapping subreg definitions.
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liveIntervalTest(R"MIR(
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successors: %bb.1, %bb.2
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undef %0.sub0 = IMPLICIT_DEF
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%0.sub1 = IMPLICIT_DEF
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S_CBRANCH_VCCNZ %bb.2, implicit undef %vcc
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S_BRANCH %bb.1
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bb.1:
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S_NOP 0, implicit %0.sub1
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bb.2:
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S_NOP 0, implicit %0.sub1
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)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
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testHandleMove(MF, LIS, 1, 0);
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});
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}
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int main(int argc, char **argv) {
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::testing::InitGoogleTest(&argc, argv);
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initLLVM();
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