[RISCV][GlobalISel] Zbkb support for G_BSWAP (#77050)

This instructions is legal in the presence of Zbkb extension.
This commit is contained in:
Mikhail Gudim 2024-01-05 23:19:46 -05:00 committed by GitHub
parent 1637c07925
commit ba3ef331b4
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 77 additions and 71 deletions

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@ -113,7 +113,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
getActionDefinitionsBuilder(G_BITREVERSE).maxScalar(0, sXLen).lower();
auto &BSWAPActions = getActionDefinitionsBuilder(G_BSWAP);
if (ST.hasStdExtZbb())
if (ST.hasStdExtZbb() || ST.hasStdExtZbkb())
BSWAPActions.legalFor({sXLen}).clampScalar(0, sXLen, sXLen);
else
BSWAPActions.maxScalar(0, sXLen).lower();

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@ -1,7 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
---
name: bswap_s32
@ -9,11 +10,11 @@ legalized: true
regBankSelected: true
body: |
bb.0.entry:
; RV32I-LABEL: name: bswap_s32
; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV32I-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]]
; RV32I-NEXT: $x10 = COPY [[REV8_RV32_]]
; RV32I-NEXT: PseudoRET implicit $x10
; CHECK-LABEL: name: bswap_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]]
; CHECK-NEXT: $x10 = COPY [[REV8_RV32_]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s32) = COPY $x10
%1:gprb(s32) = G_BSWAP %0
$x10 = COPY %1(s32)

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@ -1,7 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV64I %s
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
---
name: bswap_s64
@ -9,11 +10,11 @@ legalized: true
regBankSelected: true
body: |
bb.0.entry:
; RV64I-LABEL: name: bswap_s64
; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
; RV64I-NEXT: [[REV8_RV64_:%[0-9]+]]:gpr = REV8_RV64 [[COPY]]
; RV64I-NEXT: $x10 = COPY [[REV8_RV64_]]
; RV64I-NEXT: PseudoRET implicit $x10
; CHECK-LABEL: name: bswap_s64
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[REV8_RV64_:%[0-9]+]]:gpr = REV8_RV64 [[COPY]]
; CHECK-NEXT: $x10 = COPY [[REV8_RV64_]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(s64) = COPY $x10
%1:gprb(s64) = G_BSWAP %0
$x10 = COPY %1(s64)

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@ -2,7 +2,9 @@
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV32I
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV32ZBB
# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB
# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB
---
name: bswap_i16
@ -23,16 +25,16 @@ body: |
; RV32I-NEXT: $x10 = COPY [[AND]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
; RV32ZBB-LABEL: name: bswap_i16
; RV32ZBB: liveins: $x10
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; RV32ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
; RV32ZBB-NEXT: $x10 = COPY [[LSHR]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10
; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i16
; RV32ZBB_OR_RV32ZBKB: liveins: $x10
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB_OR_RV32ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]
; RV32ZBB_OR_RV32ZBKB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; RV32ZBB_OR_RV32ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[LSHR]](s32)
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = G_ASSERT_ZEXT %0, 16
%2:_(s16) = G_TRUNC %1(s32)
@ -65,13 +67,13 @@ body: |
; RV32I-NEXT: $x10 = COPY [[OR2]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
;
; RV32ZBB-LABEL: name: bswap_i32
; RV32ZBB: liveins: $x10
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10
; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i32
; RV32ZBB_OR_RV32ZBKB: liveins: $x10
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
%0:_(s32) = COPY $x10
%1:_(s32) = G_BSWAP %0
$x10 = COPY %1(s32)
@ -115,16 +117,16 @@ body: |
; RV32I-NEXT: $x11 = COPY [[OR5]](s32)
; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
;
; RV32ZBB-LABEL: name: bswap_i64
; RV32ZBB: liveins: $x10, $x11
; RV32ZBB-NEXT: {{ $}}
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
; RV32ZBB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32)
; RV32ZBB-NEXT: $x11 = COPY [[BSWAP1]](s32)
; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11
; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i64
; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)
; RV32ZBB_OR_RV32ZBKB-NEXT: $x11 = COPY [[BSWAP1]](s32)
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10, implicit $x11
%0:_(s32) = COPY $x10
%1:_(s32) = COPY $x11
%2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)

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@ -2,7 +2,9 @@
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV64I
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV64ZBB
# RUN: | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB
# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB
---
name: bswap_i16
@ -27,16 +29,16 @@ body: |
; RV64I-NEXT: $x10 = COPY [[AND]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: bswap_i16
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16
; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; RV64ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
; RV64ZBB-NEXT: $x10 = COPY [[LSHR]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i16
; RV64ZBB_OR_RV64ZBKB: liveins: $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16
; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
; RV64ZBB_OR_RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64)
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = G_ASSERT_ZEXT %0, 16
%2:_(s16) = G_TRUNC %1(s64)
@ -74,16 +76,16 @@ body: |
; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: bswap_i32
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32
; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; RV64ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
; RV64ZBB-NEXT: $x10 = COPY [[LSHR]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i32
; RV64ZBB_OR_RV64ZBKB: liveins: $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32
; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; RV64ZBB_OR_RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64)
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = G_ASSERT_ZEXT %0, 32
%2:_(s32) = G_TRUNC %1(s64)
@ -132,13 +134,13 @@ body: |
; RV64I-NEXT: $x10 = COPY [[OR6]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: bswap_i64
; RV64ZBB: liveins: $x10
; RV64ZBB-NEXT: {{ $}}
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]]
; RV64ZBB-NEXT: $x10 = COPY [[BSWAP]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i64
; RV64ZBB_OR_RV64ZBKB: liveins: $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]]
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[BSWAP]](s64)
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = G_BSWAP %0
$x10 = COPY %1(s64)